source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ 22ddca1f

4.104.114.84.95
Last change on this file since 22ddca1f was 22ddca1f, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/19/05 at 06:29:39

2005-02-19 Ralf Corsepius <ralf.corsepius@…>

  • rtems/score/cpu.h: Remove traces from NO_CPU.
  • Property mode set to 100644
File size: 32.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the
7 *  UNIX port of RTEMS.
8 *
9 *  COPYRIGHT (c) 1994 by Division Incorporated
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef _RTEMS_SCORE_CPU_H
19#define _RTEMS_SCORE_CPU_H
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25#include <rtems/score/unix.h>              /* pick up machine definitions */
26#ifndef ASM
27#include <rtems/score/types.h>
28#endif
29
30#if defined(linux)
31#define MALLOC_0_RETURNS_NULL
32#endif
33
34/* conditional compilation parameters */
35
36/*
37 *  Should the calls to _Thread_Enable_dispatch be inlined?
38 *
39 *  If TRUE, then they are inlined.
40 *  If FALSE, then a subroutine call is made.
41 *
42 *  Basically this is an example of the classic trade-off of size
43 *  versus speed.  Inlining the call (TRUE) typically increases the
44 *  size of RTEMS while speeding up the enabling of dispatching.
45 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
46 *  only be 0 or 1 unless you are in an interrupt handler and that
47 *  interrupt handler invokes the executive.]  When not inlined
48 *  something calls _Thread_Enable_dispatch which in turns calls
49 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
50 *  one subroutine call is avoided entirely.]
51 */
52
53#define CPU_INLINE_ENABLE_DISPATCH       FALSE
54
55/*
56 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
57 *  be unrolled one time?  In unrolled each iteration of the loop examines
58 *  two "nodes" on the chain being searched.  Otherwise, only one node
59 *  is examined per iteration.
60 *
61 *  If TRUE, then the loops are unrolled.
62 *  If FALSE, then the loops are not unrolled.
63 *
64 *  The primary factor in making this decision is the cost of disabling
65 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
66 *  body of the loop.  On some CPUs, the flash is more expensive than
67 *  one iteration of the loop body.  In this case, it might be desirable
68 *  to unroll the loop.  It is important to note that on some CPUs, this
69 *  code is the longest interrupt disable period in RTEMS.  So it is
70 *  necessary to strike a balance when setting this parameter.
71 */
72
73#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
74
75/*
76 *  Does RTEMS manage a dedicated interrupt stack in software?
77 *
78 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
79 *  If FALSE, nothing is done.
80 *
81 *  If the CPU supports a dedicated interrupt stack in hardware,
82 *  then it is generally the responsibility of the BSP to allocate it
83 *  and set it up.
84 *
85 *  If the CPU does not support a dedicated interrupt stack, then
86 *  the porter has two options: (1) execute interrupts on the
87 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
88 *  interrupt stack.
89 *
90 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
91 *
92 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
93 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
94 *  possible that both are FALSE for a particular CPU.  Although it
95 *  is unclear what that would imply about the interrupt processing
96 *  procedure on that CPU.
97 */
98
99#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
100
101/*
102 *  Does this CPU have hardware support for a dedicated interrupt stack?
103 *
104 *  If TRUE, then it must be installed during initialization.
105 *  If FALSE, then no installation is performed.
106 *
107 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 */
115
116#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
117
118/*
119 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
120 *
121 *  If TRUE, then the memory is allocated during initialization.
122 *  If FALSE, then the memory is allocated during initialization.
123 *
124 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
125 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
126 */
127
128#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
129
130/*
131 *  Does the RTEMS invoke the user's ISR with the vector number and
132 *  a pointer to the saved interrupt frame (1) or just the vector
133 *  number (0)?
134 */
135
136#define CPU_ISR_PASSES_FRAME_POINTER 0
137
138/*
139 *  Does the CPU have hardware floating point?
140 *
141 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
142 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
143 *
144 *  If there is a FP coprocessor such as the i387 or mc68881, then
145 *  the answer is TRUE.
146 *
147 *  The macro name "UNIX_HAS_FPU" should be made CPU specific.
148 *  It indicates whether or not this CPU model has FP support.  For
149 *  example, it would be possible to have an i386_nofp CPU model
150 *  which set this to false to indicate that you have an i386 without
151 *  an i387 and wish to leave floating point support out of RTEMS.
152 */
153
154#define CPU_HARDWARE_FP     TRUE
155#define CPU_SOFTWARE_FP     FALSE
156
157/*
158 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
159 *
160 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
161 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
162 *
163 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
164 */
165
166#define CPU_ALL_TASKS_ARE_FP     FALSE
167
168/*
169 *  Should the IDLE task have a floating point context?
170 *
171 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
172 *  and it has a floating point context which is switched in and out.
173 *  If FALSE, then the IDLE task does not have a floating point context.
174 *
175 *  Setting this to TRUE negatively impacts the time required to preempt
176 *  the IDLE task from an interrupt because the floating point context
177 *  must be saved as part of the preemption.
178 */
179
180#define CPU_IDLE_TASK_IS_FP      FALSE
181
182/*
183 *  Should the saving of the floating point registers be deferred
184 *  until a context switch is made to another different floating point
185 *  task?
186 *
187 *  If TRUE, then the floating point context will not be stored until
188 *  necessary.  It will remain in the floating point registers and not
189 *  disturned until another floating point task is switched to.
190 *
191 *  If FALSE, then the floating point context is saved when a floating
192 *  point task is switched out and restored when the next floating point
193 *  task is restored.  The state of the floating point registers between
194 *  those two operations is not specified.
195 *
196 *  If the floating point context does NOT have to be saved as part of
197 *  interrupt dispatching, then it should be safe to set this to TRUE.
198 *
199 *  Setting this flag to TRUE results in using a different algorithm
200 *  for deciding when to save and restore the floating point context.
201 *  The deferred FP switch algorithm minimizes the number of times
202 *  the FP context is saved and restored.  The FP context is not saved
203 *  until a context switch is made to another, different FP task.
204 *  Thus in a system with only one FP task, the FP context will never
205 *  be saved or restored.
206 */
207
208#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
209
210/*
211 *  Does this port provide a CPU dependent IDLE task implementation?
212 *
213 *  If TRUE, then the routine _CPU_Thread_Idle_body
214 *  must be provided and is the default IDLE thread body instead of
215 *  _CPU_Thread_Idle_body.
216 *
217 *  If FALSE, then use the generic IDLE thread body if the BSP does
218 *  not provide one.
219 *
220 *  This is intended to allow for supporting processors which have
221 *  a low power or idle mode.  When the IDLE thread is executed, then
222 *  the CPU can be powered down.
223 *
224 *  The order of precedence for selecting the IDLE thread body is:
225 *
226 *    1.  BSP provided
227 *    2.  CPU dependent (if provided)
228 *    3.  generic (if no BSP and no CPU dependent)
229 */
230
231#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
232
233/*
234 *  Does the stack grow up (toward higher addresses) or down
235 *  (toward lower addresses)?
236 *
237 *  If TRUE, then the grows upward.
238 *  If FALSE, then the grows toward smaller addresses.
239 */
240
241#if defined(__hppa__)
242#define CPU_STACK_GROWS_UP               TRUE
243#elif defined(__sparc__) || defined(__i386__)
244#define CPU_STACK_GROWS_UP               FALSE
245#else
246#error "unknown CPU!!"
247#endif
248
249
250/*
251 *  The following is the variable attribute used to force alignment
252 *  of critical RTEMS structures.  On some processors it may make
253 *  sense to have these aligned on tighter boundaries than
254 *  the minimum requirements of the compiler in order to have as
255 *  much of the critical data area as possible in a cache line.
256 *
257 *  The placement of this macro in the declaration of the variables
258 *  is based on the syntactically requirements of the GNU C
259 *  "__attribute__" extension.  For example with GNU C, use
260 *  the following to force a structures to a 32 byte boundary.
261 *
262 *      __attribute__ ((aligned (32)))
263 *
264 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
265 *         To benefit from using this, the data must be heavily
266 *         used so it will stay in the cache and used frequently enough
267 *         in the executive to justify turning this on.
268 *
269 *  This is really not critical on the POSIX simulator ports as
270 *  performance is not the goal here.
271 */
272
273#define CPU_STRUCTURE_ALIGNMENT
274
275/*
276 *  Define what is required to specify how the network to host conversion
277 *  routines are handled.
278 */
279
280#if defined(__hppa__) || defined(__sparc__)
281#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
282#define CPU_BIG_ENDIAN                           TRUE
283#define CPU_LITTLE_ENDIAN                        FALSE
284#elif defined(__i386__)
285#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
286#define CPU_BIG_ENDIAN                           FALSE
287#define CPU_LITTLE_ENDIAN                        TRUE
288#else
289#error "Unknown CPU!!!"
290#endif
291
292/*
293 *  The following defines the number of bits actually used in the
294 *  interrupt field of the task mode.  How those bits map to the
295 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
296 */
297
298#define CPU_MODES_INTERRUPT_MASK   0x00000001
299
300#define CPU_NAME "UNIX"
301
302/*
303 *  Processor defined structures required for cpukit/score.
304 */
305
306/* may need to put some structures here.  */
307
308#if defined(__hppa__)
309/*
310 * Word indices within a jmp_buf structure
311 */
312
313#ifdef RTEMS_NEWLIB_SETJMP
314#define RP_OFF       6
315#define SP_OFF       2
316#define R3_OFF      10
317#define R4_OFF      11
318#define R5_OFF      12
319#define R6_OFF      13
320#define R7_OFF      14
321#define R8_OFF      15
322#define R9_OFF      16
323#define R10_OFF     17
324#define R11_OFF     18
325#define R12_OFF     19
326#define R13_OFF     20
327#define R14_OFF     21
328#define R15_OFF     22
329#define R16_OFF     23
330#define R17_OFF     24
331#define R18_OFF     25
332#define DP_OFF      26
333#endif
334
335#ifdef RTEMS_UNIXLIB_SETJMP
336#define RP_OFF       0
337#define SP_OFF       1
338#define R3_OFF       4
339#define R4_OFF       5
340#define R5_OFF       6
341#define R6_OFF       7
342#define R7_OFF       8
343#define R8_OFF       9
344#define R9_OFF      10
345#define R10_OFF     11
346#define R11_OFF     12
347#define R12_OFF     13
348#define R13_OFF     14
349#define R14_OFF     15
350#define R15_OFF     16
351#define R16_OFF     17
352#define R17_OFF     18
353#define R18_OFF     19
354#define DP_OFF      20
355#endif
356#endif
357
358#if defined(__i386__)
359 
360#ifdef RTEMS_NEWLIB
361#error "Newlib not installed"
362#endif
363 
364/*
365 *  For i386 targets
366 */
367 
368#ifdef RTEMS_UNIXLIB
369#if defined(__FreeBSD__)
370#define RET_OFF    0
371#define EBX_OFF    1
372#define EBP_OFF    2
373#define ESP_OFF    3
374#define ESI_OFF    4
375#define EDI_OFF    5
376#elif defined(__CYGWIN__)
377#define EAX_OFF    0
378#define EBX_OFF    1
379#define ECX_OFF    2
380#define EDX_OFF    3
381#define ESI_OFF    4
382#define EDI_OFF    5
383#define EBP_OFF    6
384#define ESP_OFF    7
385#define RET_OFF    8
386#else
387/* Linux */
388#define EBX_OFF    0
389#define ESI_OFF    1
390#define EDI_OFF    2
391#define EBP_OFF    3
392#define ESP_OFF    4
393#define RET_OFF    5
394#endif
395#endif
396 
397#endif
398 
399#if defined(__sparc__)
400
401/*
402 *  Word indices within a jmp_buf structure
403 */
404 
405#ifdef RTEMS_NEWLIB
406#define ADDR_ADJ_OFFSET -8
407#define SP_OFF    0
408#define RP_OFF    1
409#define FP_OFF    2
410#endif
411
412#ifdef RTEMS_UNIXLIB
413#define ADDR_ADJ_OFFSET 0
414#define G0_OFF    0
415#define SP_OFF    1
416#define RP_OFF    2   
417#define FP_OFF    3
418#define I7_OFF    4
419#endif
420
421#endif
422
423/*
424 * Contexts
425 *
426 *  Generally there are 2 types of context to save.
427 *     1. Interrupt registers to save
428 *     2. Task level registers to save
429 *
430 *  This means we have the following 3 context items:
431 *     1. task level context stuff::  Context_Control
432 *     2. floating point task stuff:: Context_Control_fp
433 *     3. special interrupt level context :: Context_Control_interrupt
434 *
435 *  On some processors, it is cost-effective to save only the callee
436 *  preserved registers during a task context switch.  This means
437 *  that the ISR code needs to save those registers which do not
438 *  persist across function calls.  It is not mandatory to make this
439 *  distinctions between the caller/callee saves registers for the
440 *  purpose of minimizing context saved during task switch and on interrupts.
441 *  If the cost of saving extra registers is minimal, simplicity is the
442 *  choice.  Save the same context on interrupt entry as for tasks in
443 *  this case.
444 *
445 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
446 *  care should be used in designing the context area.
447 *
448 *  On some CPUs with hardware floating point support, the Context_Control_fp
449 *  structure will not be used or it simply consist of an array of a
450 *  fixed number of bytes.   This is done when the floating point context
451 *  is dumped by a "FP save context" type instruction and the format
452 *  is not really defined by the CPU.  In this case, there is no need
453 *  to figure out the exact format -- only the size.  Of course, although
454 *  this is enough information for RTEMS, it is probably not enough for
455 *  a debugger such as gdb.  But that is another problem.
456 */
457
458/*
459 *  This is really just the area for the following fields.
460 *
461 *    jmp_buf    regs;
462 *    uint32_t   isr_level;
463 *
464 *  Doing it this way avoids conflicts between the native stuff and the
465 *  RTEMS stuff.
466 *
467 *  NOTE:
468 *      hpux9 setjmp is optimized for the case where the setjmp buffer
469 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
470 *      8 byte copies, especially for the float registers.
471 *      So we always align them on 8 byte boundaries.
472 */
473
474#ifdef __GNUC__
475#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
476#else
477#define CONTEXT_STRUCTURE_ALIGNMENT
478#endif
479
480typedef struct {
481  char      Area[ SIZEOF_CPU_CONTEXT ] CONTEXT_STRUCTURE_ALIGNMENT;
482} Context_Control;
483
484typedef struct {
485} Context_Control_fp;
486
487typedef struct {
488} CPU_Interrupt_frame;
489
490
491/*
492 *  The following table contains the information required to configure
493 *  the UNIX Simulator specific parameters.
494 */
495
496typedef struct {
497  void       (*pretasking_hook)( void );
498  void       (*predriver_hook)( void );
499  void       (*postdriver_hook)( void );
500  void       (*idle_task)( void );
501  boolean      do_zero_of_workspace;
502  uint32_t     idle_task_stack_size;
503  uint32_t     interrupt_stack_size;
504  uint32_t     extra_mpci_receive_server_stack;
505  void *     (*stack_allocate_hook)( uint32_t   );
506  void       (*stack_free_hook)( void* );
507  /* end of required fields */
508}   rtems_cpu_table;
509
510/*
511 *  Macros to access required entires in the CPU Table are in
512 *  the file rtems/system.h.
513 */
514
515/*
516 *  Macros to access UNIX specific additions to the CPU Table
517 */
518
519/* There are no CPU specific additions to the CPU Table for this port. */
520
521/*
522 *  This variable is optional.  It is used on CPUs on which it is difficult
523 *  to generate an "uninitialized" FP context.  It is filled in by
524 *  _CPU_Initialize and copied into the task's FP context area during
525 *  _CPU_Context_Initialize.
526 */
527
528SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
529
530/*
531 *  On some CPUs, RTEMS supports a software managed interrupt stack.
532 *  This stack is allocated by the Interrupt Manager and the switch
533 *  is performed in _ISR_Handler.  These variables contain pointers
534 *  to the lowest and highest addresses in the chunk of memory allocated
535 *  for the interrupt stack.  Since it is unknown whether the stack
536 *  grows up or down (in general), this give the CPU dependent
537 *  code the option of picking the version it wants to use.
538 *
539 *  NOTE: These two variables are required if the macro
540 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
541 */
542
543SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
544SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
545
546/*
547 *  With some compilation systems, it is difficult if not impossible to
548 *  call a high-level language routine from assembly language.  This
549 *  is especially true of commercial Ada compilers and name mangling
550 *  C++ ones.  This variable can be optionally defined by the CPU porter
551 *  and contains the address of the routine _Thread_Dispatch.  This
552 *  can make it easier to invoke that routine at the end of the interrupt
553 *  sequence (if a dispatch is necessary).
554 */
555
556SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
557
558/*
559 *  Nothing prevents the porter from declaring more CPU specific variables.
560 */
561
562/* XXX: if needed, put more variables here */
563
564/*
565 *  The size of the floating point context area.  On some CPUs this
566 *  will not be a "sizeof" because the format of the floating point
567 *  area is not defined -- only the size is.  This is usually on
568 *  CPUs with a "floating point save context" instruction.
569 */
570
571#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
572
573/*
574 * The size of a frame on the stack
575 */
576
577#if defined(__hppa__)
578#define CPU_FRAME_SIZE  (32 * 4)
579#elif defined(__sparc__)
580#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
581#elif defined(__i386__)
582#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
583#else
584#error "Unknown CPU!!!"
585#endif
586
587/*
588 *  Amount of extra stack (above minimum stack size) required by
589 *  MPCI receive server thread.  Remember that in a multiprocessor
590 *  system this thread must exist and be able to process all directives.
591 */
592
593#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
594
595/*
596 *  This defines the number of entries in the ISR_Vector_table managed
597 *  by RTEMS.
598 */
599
600#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
601#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
602
603/*
604 *  This is defined if the port has a special way to report the ISR nesting
605 *  level.  Most ports maintain the variable _ISR_Nest_level.
606 */
607
608#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
609
610/*
611 *  Should be large enough to run all RTEMS tests.  This insures
612 *  that a "reasonable" small application should not have any problems.
613 */
614
615#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
616
617/*
618 *  CPU's worst alignment requirement for data types on a byte boundary.  This
619 *  alignment does not take into account the requirements for the stack.
620 */
621
622#define CPU_ALIGNMENT              8
623
624/*
625 *  This number corresponds to the byte alignment requirement for the
626 *  heap handler.  This alignment requirement may be stricter than that
627 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
628 *  common for the heap to follow the same alignment requirement as
629 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
630 *  then this should be set to CPU_ALIGNMENT.
631 *
632 *  NOTE:  This does not have to be a power of 2.  It does have to
633 *         be greater or equal to than CPU_ALIGNMENT.
634 */
635
636#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
637
638/*
639 *  This number corresponds to the byte alignment requirement for memory
640 *  buffers allocated by the partition manager.  This alignment requirement
641 *  may be stricter than that for the data types alignment specified by
642 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
643 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
644 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
645 *
646 *  NOTE:  This does not have to be a power of 2.  It does have to
647 *         be greater or equal to than CPU_ALIGNMENT.
648 */
649
650#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
651
652/*
653 *  This number corresponds to the byte alignment requirement for the
654 *  stack.  This alignment requirement may be stricter than that for the
655 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
656 *  is strict enough for the stack, then this should be set to 0.
657 *
658 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
659 */
660
661#define CPU_STACK_ALIGNMENT        64
662
663/*
664 *  ISR handler macros
665 */
666
667/*
668 *  Support routine to initialize the RTEMS vector table after it is allocated.
669 */
670
671void _CPU_Initialize_vectors(void);
672
673/*
674 *  Disable all interrupts for an RTEMS critical section.  The previous
675 *  level is returned in _level.
676 */
677
678extern uint32_t   _CPU_ISR_Disable_support(void);
679
680#define _CPU_ISR_Disable( _level ) \
681    do { \
682      (_level) = _CPU_ISR_Disable_support(); \
683    } while ( 0 )
684
685/*
686 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
687 *  This indicates the end of an RTEMS critical section.  The parameter
688 *  _level is not modified.
689 */
690
691void _CPU_ISR_Enable(uint32_t   level);
692
693/*
694 *  This temporarily restores the interrupt to _level before immediately
695 *  disabling them again.  This is used to divide long RTEMS critical
696 *  sections into two or more parts.  The parameter _level is not
697 * modified.
698 */
699
700#define _CPU_ISR_Flash( _level ) \
701  do { \
702      register uint32_t   _ignored = 0; \
703      _CPU_ISR_Enable( (_level) ); \
704      _CPU_ISR_Disable( _ignored ); \
705  } while ( 0 )
706
707/*
708 *  Map interrupt level in task mode onto the hardware that the CPU
709 *  actually provides.  Currently, interrupt levels which do not
710 *  map onto the CPU in a generic fashion are undefined.  Someday,
711 *  it would be nice if these were "mapped" by the application
712 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
713 *  8 - 255 would be available for bsp/application specific meaning.
714 *  This could be used to manage a programmable interrupt controller
715 *  via the rtems_task_mode directive.
716 */
717
718#define _CPU_ISR_Set_level( new_level ) \
719  { \
720    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
721    else                  _CPU_ISR_Enable( 1 ); \
722  }
723
724uint32_t   _CPU_ISR_Get_level( void );
725
726/* end of ISR handler macros */
727
728/* Context handler macros */
729
730/*
731 *  This routine is responsible for somehow restarting the currently
732 *  executing task.  If you are lucky, then all that is necessary
733 *  is restoring the context.  Otherwise, there will need to be
734 *  a special assembly routine which does something special in this
735 *  case.  Context_Restore should work most of the time.  It will
736 *  not work if restarting self conflicts with the stack frame
737 *  assumptions of restoring a context.
738 */
739
740#define _CPU_Context_Restart_self( _the_context ) \
741   _CPU_Context_restore( (_the_context) );
742
743/*
744 *  The purpose of this macro is to allow the initial pointer into
745 *  a floating point context area (used to save the floating point
746 *  context) to be at an arbitrary place in the floating point
747 *  context area.
748 *
749 *  This is necessary because some FP units are designed to have
750 *  their context saved as a stack which grows into lower addresses.
751 *  Other FP units can be saved by simply moving registers into offsets
752 *  from the base of the context area.  Finally some FP units provide
753 *  a "dump context" instruction which could fill in from high to low
754 *  or low to high based on the whim of the CPU designers.
755 */
756
757#define _CPU_Context_Fp_start( _base, _offset ) \
758   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
759
760/*
761 *  This routine initializes the FP context area passed to it to.
762 *  There are a few standard ways in which to initialize the
763 *  floating point context.  The code included for this macro assumes
764 *  that this is a CPU in which a "initial" FP context was saved into
765 *  _CPU_Null_fp_context and it simply copies it to the destination
766 *  context passed to it.
767 *
768 *  Other models include (1) not doing anything, and (2) putting
769 *  a "null FP status word" in the correct place in the FP context.
770 */
771
772#define _CPU_Context_Initialize_fp( _destination ) \
773  { \
774   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
775  }
776
777#define _CPU_Context_save_fp( _fp_context ) \
778    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
779
780#define _CPU_Context_restore_fp( _fp_context ) \
781    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
782
783extern void _CPU_Context_Initialize(
784  Context_Control  *_the_context,
785  uint32_t         *_stack_base,
786  uint32_t          _size,
787  uint32_t          _new_level,
788  void             *_entry_point,
789  boolean           _is_fp
790);
791
792/* end of Context handler macros */
793
794/* Fatal Error manager macros */
795
796/*
797 *  This routine copies _error into a known place -- typically a stack
798 *  location or a register, optionally disables interrupts, and
799 *  halts/stops the CPU.
800 */
801
802#define _CPU_Fatal_halt( _error ) \
803    _CPU_Fatal_error( _error )
804
805/* end of Fatal Error manager macros */
806
807/* Bitfield handler macros */
808
809/*
810 *  This routine sets _output to the bit number of the first bit
811 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
812 *  This type may be either 16 or 32 bits wide although only the 16
813 *  least significant bits will be used.
814 *
815 *  There are a number of variables in using a "find first bit" type
816 *  instruction.
817 *
818 *    (1) What happens when run on a value of zero?
819 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
820 *    (3) The numbering may be zero or one based.
821 *    (4) The "find first bit" instruction may search from MSB or LSB.
822 *
823 *  RTEMS guarantees that (1) will never happen so it is not a concern.
824 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
825 *  _CPU_Priority_bits_index().  These three form a set of routines
826 *  which must logically operate together.  Bits in the _value are
827 *  set and cleared based on masks built by _CPU_Priority_mask().
828 *  The basic major and minor values calculated by _Priority_Major()
829 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
830 *  to properly range between the values returned by the "find first bit"
831 *  instruction.  This makes it possible for _Priority_Get_highest() to
832 *  calculate the major and directly index into the minor table.
833 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
834 *  is the first bit found.
835 *
836 *  This entire "find first bit" and mapping process depends heavily
837 *  on the manner in which a priority is broken into a major and minor
838 *  components with the major being the 4 MSB of a priority and minor
839 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
840 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
841 *  to the lowest priority.
842 *
843 *  If your CPU does not have a "find first bit" instruction, then
844 *  there are ways to make do without it.  Here are a handful of ways
845 *  to implement this in software:
846 *
847 *    - a series of 16 bit test instructions
848 *    - a "binary search using if's"
849 *    - _number = 0
850 *      if _value > 0x00ff
851 *        _value >>=8
852 *        _number = 8;
853 *
854 *      if _value > 0x0000f
855 *        _value >=8
856 *        _number += 4
857 *
858 *      _number += bit_set_table[ _value ]
859 *
860 *    where bit_set_table[ 16 ] has values which indicate the first
861 *      bit set
862 */
863
864/*
865 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
866 *  dependencies on either a native bitscan instruction or an ffs() in the
867 *  C library.
868 */
869 
870#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
871#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
872 
873/* end of Bitfield handler macros */
874 
875/* Priority handler handler macros */
876 
877/*
878 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
879 *  dependencies on either a native bitscan instruction or an ffs() in the
880 *  C library.
881 */
882 
883/* end of Priority handler macros */
884
885/* functions */
886
887/*
888 *  _CPU_Initialize
889 *
890 *  This routine performs CPU dependent initialization.
891 */
892
893void _CPU_Initialize(
894  rtems_cpu_table  *cpu_table,
895  void      (*thread_dispatch)
896);
897
898/*
899 *  _CPU_ISR_install_raw_handler
900 *
901 *  This routine installs a "raw" interrupt handler directly into the
902 *  processor's vector table.
903 */
904 
905void _CPU_ISR_install_raw_handler(
906  uint32_t    vector,
907  proc_ptr    new_handler,
908  proc_ptr   *old_handler
909);
910
911/*
912 *  _CPU_ISR_install_vector
913 *
914 *  This routine installs an interrupt vector.
915 */
916
917void _CPU_ISR_install_vector(
918  uint32_t    vector,
919  proc_ptr    new_handler,
920  proc_ptr   *old_handler
921);
922
923/*
924 *  _CPU_Install_interrupt_stack
925 *
926 *  This routine installs the hardware interrupt stack pointer.
927 *
928 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
929 *         is TRUE.
930 */
931
932void _CPU_Install_interrupt_stack( void );
933
934/*
935 *  _CPU_Thread_Idle_body
936 *
937 *  This routine is the CPU dependent IDLE thread body.
938 *
939 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
940 *         is TRUE.
941 */
942
943void _CPU_Thread_Idle_body( void );
944
945/*
946 *  _CPU_Context_switch
947 *
948 *  This routine switches from the run context to the heir context.
949 */
950
951void _CPU_Context_switch(
952  Context_Control  *run,
953  Context_Control  *heir
954);
955
956/*
957 *  _CPU_Context_restore
958 *
959 *  This routine is generally used only to restart self in an
960 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
961 *
962 *  NOTE: May be unnecessary to reload some registers.
963 */
964
965void _CPU_Context_restore(
966  Context_Control *new_context
967);
968
969/*
970 *  _CPU_Save_float_context
971 *
972 *  This routine saves the floating point context passed to it.
973 */
974
975void _CPU_Save_float_context(
976  Context_Control_fp *fp_context_ptr
977);
978
979/*
980 *  _CPU_Restore_float_context
981 *
982 *  This routine restores the floating point context passed to it.
983 */
984
985void _CPU_Restore_float_context(
986  Context_Control_fp *fp_context_ptr
987);
988
989
990void _CPU_ISR_Set_signal_level(
991  uint32_t   level
992);
993
994void _CPU_Fatal_error(
995  uint32_t   _error
996);
997
998/*  The following routine swaps the endian format of an unsigned int.
999 *  It must be static because it is referenced indirectly.
1000 *
1001 *  This version will work on any processor, but if there is a better
1002 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1003 *
1004 *     swap least significant two bytes with 16-bit rotate
1005 *     swap upper and lower 16-bits
1006 *     swap most significant two bytes with 16-bit rotate
1007 *
1008 *  Some CPUs have special instructions which swap a 32-bit quantity in
1009 *  a single instruction (e.g. i486).  It is probably best to avoid
1010 *  an "endian swapping control bit" in the CPU.  One good reason is
1011 *  that interrupts would probably have to be disabled to insure that
1012 *  an interrupt does not try to access the same "chunk" with the wrong
1013 *  endian.  Another good reason is that on some CPUs, the endian bit
1014 *  endianness for ALL fetches -- both code and data -- so the code
1015 *  will be fetched incorrectly.
1016 */
1017 
1018static inline uint32_t CPU_swap_u32(
1019  uint32_t value
1020)
1021{
1022  uint32_t   byte1, byte2, byte3, byte4, swapped;
1023 
1024  byte4 = (value >> 24) & 0xff;
1025  byte3 = (value >> 16) & 0xff;
1026  byte2 = (value >> 8)  & 0xff;
1027  byte1 =  value        & 0xff;
1028 
1029  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1030  return( swapped );
1031}
1032
1033#define CPU_swap_u16( value ) \
1034  (((value&0xff) << 8) | ((value >> 8)&0xff))
1035
1036/*
1037 *  Special Purpose Routines to hide the use of UNIX system calls.
1038 */
1039
1040
1041/*
1042 *  Pointer to a sync io  Handler
1043 */
1044
1045typedef void ( *rtems_sync_io_handler )(
1046  int fd,
1047  boolean read,
1048  boolean wrtie,
1049  boolean except
1050);
1051
1052/* returns -1 if fd to large, 0 is successful */
1053int _CPU_Set_sync_io_handler(
1054  int fd,
1055  boolean read,
1056  boolean write,
1057  boolean except,
1058  rtems_sync_io_handler handler
1059);
1060
1061/* returns -1 if fd to large, o if successful */
1062int _CPU_Clear_sync_io_handler(
1063  int fd
1064);
1065
1066int _CPU_Get_clock_vector( void );
1067
1068void _CPU_Start_clock(
1069  int microseconds
1070);
1071
1072void _CPU_Stop_clock( void );
1073
1074#if defined(RTEMS_MULTIPROCESSING)
1075
1076void _CPU_SHM_Init(
1077  uint32_t     maximum_nodes,
1078  boolean      is_master_node,
1079  void       **shm_address,
1080  uint32_t    *shm_length
1081);
1082
1083int _CPU_Get_pid( void );
1084 
1085int _CPU_SHM_Get_vector( void );
1086 
1087void _CPU_SHM_Send_interrupt(
1088  int pid,
1089  int vector
1090);
1091 
1092void _CPU_SHM_Lock(
1093  int semaphore
1094);
1095
1096void _CPU_SHM_Unlock(
1097  int semaphore
1098);
1099#endif
1100
1101#ifdef __cplusplus
1102}
1103#endif
1104
1105#endif
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