source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ 1292ba4

4.104.114.84.95
Last change on this file since 1292ba4 was 1292ba4, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 3, 2003 at 8:08:14 PM

2003-01-03 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Per PR315, eliminate warning for structure alignment requests that are too large.
  • Property mode set to 100644
File size: 32.6 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/types.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#endif
33
34#if defined(linux)
35#define MALLOC_0_RETURNS_NULL
36#endif
37
38/* conditional compilation parameters */
39
40/*
41 *  Should the calls to _Thread_Enable_dispatch be inlined?
42 *
43 *  If TRUE, then they are inlined.
44 *  If FALSE, then a subroutine call is made.
45 *
46 *  Basically this is an example of the classic trade-off of size
47 *  versus speed.  Inlining the call (TRUE) typically increases the
48 *  size of RTEMS while speeding up the enabling of dispatching.
49 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
50 *  only be 0 or 1 unless you are in an interrupt handler and that
51 *  interrupt handler invokes the executive.]  When not inlined
52 *  something calls _Thread_Enable_dispatch which in turns calls
53 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
54 *  one subroutine call is avoided entirely.]
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 */
76
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/*
80 *  Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
83 *  If FALSE, nothing is done.
84 *
85 *  If the CPU supports a dedicated interrupt stack in hardware,
86 *  then it is generally the responsibility of the BSP to allocate it
87 *  and set it up.
88 *
89 *  If the CPU does not support a dedicated interrupt stack, then
90 *  the porter has two options: (1) execute interrupts on the
91 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 *  interrupt stack.
93 *
94 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 *  possible that both are FALSE for a particular CPU.  Although it
99 *  is unclear what that would imply about the interrupt processing
100 *  procedure on that CPU.
101 */
102
103#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
104
105/*
106 *  Does this CPU have hardware support for a dedicated interrupt stack?
107 *
108 *  If TRUE, then it must be installed during initialization.
109 *  If FALSE, then no installation is performed.
110 *
111 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
112 *
113 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
114 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
115 *  possible that both are FALSE for a particular CPU.  Although it
116 *  is unclear what that would imply about the interrupt processing
117 *  procedure on that CPU.
118 */
119
120#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
121
122/*
123 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
124 *
125 *  If TRUE, then the memory is allocated during initialization.
126 *  If FALSE, then the memory is allocated during initialization.
127 *
128 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
129 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
130 */
131
132#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
133
134/*
135 *  Does the RTEMS invoke the user's ISR with the vector number and
136 *  a pointer to the saved interrupt frame (1) or just the vector
137 *  number (0)?
138 */
139
140#define CPU_ISR_PASSES_FRAME_POINTER 0
141
142/*
143 *  Does the CPU have hardware floating point?
144 *
145 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
146 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
147 *
148 *  If there is a FP coprocessor such as the i387 or mc68881, then
149 *  the answer is TRUE.
150 *
151 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
152 *  It indicates whether or not this CPU model has FP support.  For
153 *  example, it would be possible to have an i386_nofp CPU model
154 *  which set this to false to indicate that you have an i386 without
155 *  an i387 and wish to leave floating point support out of RTEMS.
156 */
157
158#define CPU_HARDWARE_FP     TRUE
159#define CPU_SOFTWARE_FP     FALSE
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  So far, the only CPU in which this option has been used is the
168 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
169 *  floating point registers to perform integer multiplies.  If
170 *  a function which you would not think utilize the FP unit DOES,
171 *  then one can not easily predict which tasks will use the FP hardware.
172 *  In this case, this option should be TRUE.
173 *
174 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
175 */
176
177#define CPU_ALL_TASKS_ARE_FP     FALSE
178
179/*
180 *  Should the IDLE task have a floating point context?
181 *
182 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
183 *  and it has a floating point context which is switched in and out.
184 *  If FALSE, then the IDLE task does not have a floating point context.
185 *
186 *  Setting this to TRUE negatively impacts the time required to preempt
187 *  the IDLE task from an interrupt because the floating point context
188 *  must be saved as part of the preemption.
189 */
190
191#define CPU_IDLE_TASK_IS_FP      FALSE
192
193/*
194 *  Should the saving of the floating point registers be deferred
195 *  until a context switch is made to another different floating point
196 *  task?
197 *
198 *  If TRUE, then the floating point context will not be stored until
199 *  necessary.  It will remain in the floating point registers and not
200 *  disturned until another floating point task is switched to.
201 *
202 *  If FALSE, then the floating point context is saved when a floating
203 *  point task is switched out and restored when the next floating point
204 *  task is restored.  The state of the floating point registers between
205 *  those two operations is not specified.
206 *
207 *  If the floating point context does NOT have to be saved as part of
208 *  interrupt dispatching, then it should be safe to set this to TRUE.
209 *
210 *  Setting this flag to TRUE results in using a different algorithm
211 *  for deciding when to save and restore the floating point context.
212 *  The deferred FP switch algorithm minimizes the number of times
213 *  the FP context is saved and restored.  The FP context is not saved
214 *  until a context switch is made to another, different FP task.
215 *  Thus in a system with only one FP task, the FP context will never
216 *  be saved or restored.
217 */
218
219#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
220
221/*
222 *  Does this port provide a CPU dependent IDLE task implementation?
223 *
224 *  If TRUE, then the routine _CPU_Thread_Idle_body
225 *  must be provided and is the default IDLE thread body instead of
226 *  _CPU_Thread_Idle_body.
227 *
228 *  If FALSE, then use the generic IDLE thread body if the BSP does
229 *  not provide one.
230 *
231 *  This is intended to allow for supporting processors which have
232 *  a low power or idle mode.  When the IDLE thread is executed, then
233 *  the CPU can be powered down.
234 *
235 *  The order of precedence for selecting the IDLE thread body is:
236 *
237 *    1.  BSP provided
238 *    2.  CPU dependent (if provided)
239 *    3.  generic (if no BSP and no CPU dependent)
240 */
241
242#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
243
244/*
245 *  Does the stack grow up (toward higher addresses) or down
246 *  (toward lower addresses)?
247 *
248 *  If TRUE, then the grows upward.
249 *  If FALSE, then the grows toward smaller addresses.
250 */
251
252#if defined(__hppa__)
253#define CPU_STACK_GROWS_UP               TRUE
254#elif defined(__sparc__) || defined(__i386__)
255#define CPU_STACK_GROWS_UP               FALSE
256#else
257#error "unknown CPU!!"
258#endif
259
260
261/*
262 *  The following is the variable attribute used to force alignment
263 *  of critical RTEMS structures.  On some processors it may make
264 *  sense to have these aligned on tighter boundaries than
265 *  the minimum requirements of the compiler in order to have as
266 *  much of the critical data area as possible in a cache line.
267 *
268 *  The placement of this macro in the declaration of the variables
269 *  is based on the syntactically requirements of the GNU C
270 *  "__attribute__" extension.  For example with GNU C, use
271 *  the following to force a structures to a 32 byte boundary.
272 *
273 *      __attribute__ ((aligned (32)))
274 *
275 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
276 *         To benefit from using this, the data must be heavily
277 *         used so it will stay in the cache and used frequently enough
278 *         in the executive to justify turning this on.
279 *
280 *  This is really not critical on the POSIX simulator ports as
281 *  performance is not the goal here.
282 */
283
284#define CPU_STRUCTURE_ALIGNMENT
285
286/*
287 *  Define what is required to specify how the network to host conversion
288 *  routines are handled.
289 */
290
291#if defined(__hppa__) || defined(__sparc__)
292#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
293#define CPU_BIG_ENDIAN                           TRUE
294#define CPU_LITTLE_ENDIAN                        FALSE
295#elif defined(__i386__)
296#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
297#define CPU_BIG_ENDIAN                           FALSE
298#define CPU_LITTLE_ENDIAN                        TRUE
299#else
300#error "Unknown CPU!!!"
301#endif
302
303/*
304 *  The following defines the number of bits actually used in the
305 *  interrupt field of the task mode.  How those bits map to the
306 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
307 */
308
309#define CPU_MODES_INTERRUPT_MASK   0x00000001
310
311#define CPU_NAME "UNIX"
312
313/*
314 *  Processor defined structures
315 *
316 *  Examples structures include the descriptor tables from the i386
317 *  and the processor control structure on the i960ca.
318 */
319
320/* may need to put some structures here.  */
321
322#if defined(__hppa__)
323/*
324 * Word indices within a jmp_buf structure
325 */
326
327#ifdef RTEMS_NEWLIB_SETJMP
328#define RP_OFF       6
329#define SP_OFF       2
330#define R3_OFF      10
331#define R4_OFF      11
332#define R5_OFF      12
333#define R6_OFF      13
334#define R7_OFF      14
335#define R8_OFF      15
336#define R9_OFF      16
337#define R10_OFF     17
338#define R11_OFF     18
339#define R12_OFF     19
340#define R13_OFF     20
341#define R14_OFF     21
342#define R15_OFF     22
343#define R16_OFF     23
344#define R17_OFF     24
345#define R18_OFF     25
346#define DP_OFF      26
347#endif
348
349#ifdef RTEMS_UNIXLIB_SETJMP
350#define RP_OFF       0
351#define SP_OFF       1
352#define R3_OFF       4
353#define R4_OFF       5
354#define R5_OFF       6
355#define R6_OFF       7
356#define R7_OFF       8
357#define R8_OFF       9
358#define R9_OFF      10
359#define R10_OFF     11
360#define R11_OFF     12
361#define R12_OFF     13
362#define R13_OFF     14
363#define R14_OFF     15
364#define R15_OFF     16
365#define R16_OFF     17
366#define R17_OFF     18
367#define R18_OFF     19
368#define DP_OFF      20
369#endif
370#endif
371
372#if defined(__i386__)
373 
374#ifdef RTEMS_NEWLIB
375#error "Newlib not installed"
376#endif
377 
378/*
379 *  For i386 targets
380 */
381 
382#ifdef RTEMS_UNIXLIB
383#if defined(__FreeBSD__)
384#define RET_OFF    0
385#define EBX_OFF    1
386#define EBP_OFF    2
387#define ESP_OFF    3
388#define ESI_OFF    4
389#define EDI_OFF    5
390#elif defined(__CYGWIN__)
391#define EAX_OFF    0
392#define EBX_OFF    1
393#define ECX_OFF    2
394#define EDX_OFF    3
395#define ESI_OFF    4
396#define EDI_OFF    5
397#define EBP_OFF    6
398#define ESP_OFF    7
399#define RET_OFF    8
400#else
401/* Linux */
402#define EBX_OFF    0
403#define ESI_OFF    1
404#define EDI_OFF    2
405#define EBP_OFF    3
406#define ESP_OFF    4
407#define RET_OFF    5
408#endif
409#endif
410 
411#endif
412 
413#if defined(__sparc__)
414
415/*
416 *  Word indices within a jmp_buf structure
417 */
418 
419#ifdef RTEMS_NEWLIB
420#define ADDR_ADJ_OFFSET -8
421#define SP_OFF    0
422#define RP_OFF    1
423#define FP_OFF    2
424#endif
425
426#ifdef RTEMS_UNIXLIB
427#define ADDR_ADJ_OFFSET 0
428#define G0_OFF    0
429#define SP_OFF    1
430#define RP_OFF    2   
431#define FP_OFF    3
432#define I7_OFF    4
433#endif
434
435#endif
436
437/*
438 * Contexts
439 *
440 *  Generally there are 2 types of context to save.
441 *     1. Interrupt registers to save
442 *     2. Task level registers to save
443 *
444 *  This means we have the following 3 context items:
445 *     1. task level context stuff::  Context_Control
446 *     2. floating point task stuff:: Context_Control_fp
447 *     3. special interrupt level context :: Context_Control_interrupt
448 *
449 *  On some processors, it is cost-effective to save only the callee
450 *  preserved registers during a task context switch.  This means
451 *  that the ISR code needs to save those registers which do not
452 *  persist across function calls.  It is not mandatory to make this
453 *  distinctions between the caller/callee saves registers for the
454 *  purpose of minimizing context saved during task switch and on interrupts.
455 *  If the cost of saving extra registers is minimal, simplicity is the
456 *  choice.  Save the same context on interrupt entry as for tasks in
457 *  this case.
458 *
459 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
460 *  care should be used in designing the context area.
461 *
462 *  On some CPUs with hardware floating point support, the Context_Control_fp
463 *  structure will not be used or it simply consist of an array of a
464 *  fixed number of bytes.   This is done when the floating point context
465 *  is dumped by a "FP save context" type instruction and the format
466 *  is not really defined by the CPU.  In this case, there is no need
467 *  to figure out the exact format -- only the size.  Of course, although
468 *  this is enough information for RTEMS, it is probably not enough for
469 *  a debugger such as gdb.  But that is another problem.
470 */
471
472/*
473 *  This is really just the area for the following fields.
474 *
475 *    jmp_buf    regs;
476 *    unsigned32 isr_level;
477 *
478 *  Doing it this way avoids conflicts between the native stuff and the
479 *  RTEMS stuff.
480 *
481 *  NOTE:
482 *      hpux9 setjmp is optimized for the case where the setjmp buffer
483 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
484 *      8 byte copies, especially for the float registers.
485 *      So we always align them on 8 byte boundaries.
486 */
487
488#ifdef __GNUC__
489#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
490#else
491#define CONTEXT_STRUCTURE_ALIGNMENT
492#endif
493
494typedef struct {
495  char      Area[ SIZEOF_CPU_CONTEXT ] CONTEXT_STRUCTURE_ALIGNMENT;
496} Context_Control;
497
498typedef struct {
499} Context_Control_fp;
500
501typedef struct {
502} CPU_Interrupt_frame;
503
504
505/*
506 *  The following table contains the information required to configure
507 *  the UNIX Simulator specific parameters.
508 */
509
510typedef struct {
511  void       (*pretasking_hook)( void );
512  void       (*predriver_hook)( void );
513  void       (*postdriver_hook)( void );
514  void       (*idle_task)( void );
515  boolean      do_zero_of_workspace;
516  unsigned32   idle_task_stack_size;
517  unsigned32   interrupt_stack_size;
518  unsigned32   extra_mpci_receive_server_stack;
519  void *     (*stack_allocate_hook)( unsigned32 );
520  void       (*stack_free_hook)( void* );
521  /* end of required fields */
522}   rtems_cpu_table;
523
524/*
525 *  Macros to access required entires in the CPU Table are in
526 *  the file rtems/system.h.
527 */
528
529/*
530 *  Macros to access UNIX specific additions to the CPU Table
531 */
532
533/* There are no CPU specific additions to the CPU Table for this port. */
534
535/*
536 *  This variable is optional.  It is used on CPUs on which it is difficult
537 *  to generate an "uninitialized" FP context.  It is filled in by
538 *  _CPU_Initialize and copied into the task's FP context area during
539 *  _CPU_Context_Initialize.
540 */
541
542SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
543
544/*
545 *  On some CPUs, RTEMS supports a software managed interrupt stack.
546 *  This stack is allocated by the Interrupt Manager and the switch
547 *  is performed in _ISR_Handler.  These variables contain pointers
548 *  to the lowest and highest addresses in the chunk of memory allocated
549 *  for the interrupt stack.  Since it is unknown whether the stack
550 *  grows up or down (in general), this give the CPU dependent
551 *  code the option of picking the version it wants to use.
552 *
553 *  NOTE: These two variables are required if the macro
554 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
555 */
556
557SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
558SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
559
560/*
561 *  With some compilation systems, it is difficult if not impossible to
562 *  call a high-level language routine from assembly language.  This
563 *  is especially true of commercial Ada compilers and name mangling
564 *  C++ ones.  This variable can be optionally defined by the CPU porter
565 *  and contains the address of the routine _Thread_Dispatch.  This
566 *  can make it easier to invoke that routine at the end of the interrupt
567 *  sequence (if a dispatch is necessary).
568 */
569
570SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
571
572/*
573 *  Nothing prevents the porter from declaring more CPU specific variables.
574 */
575
576/* XXX: if needed, put more variables here */
577
578/*
579 *  The size of the floating point context area.  On some CPUs this
580 *  will not be a "sizeof" because the format of the floating point
581 *  area is not defined -- only the size is.  This is usually on
582 *  CPUs with a "floating point save context" instruction.
583 */
584
585#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
586
587/*
588 * The size of a frame on the stack
589 */
590
591#if defined(__hppa__)
592#define CPU_FRAME_SIZE  (32 * 4)
593#elif defined(__sparc__)
594#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
595#elif defined(__i386__)
596#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
597#else
598#error "Unknown CPU!!!"
599#endif
600
601/*
602 *  Amount of extra stack (above minimum stack size) required by
603 *  MPCI receive server thread.  Remember that in a multiprocessor
604 *  system this thread must exist and be able to process all directives.
605 */
606
607#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
608
609/*
610 *  This defines the number of entries in the ISR_Vector_table managed
611 *  by RTEMS.
612 */
613
614#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
615#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
616
617/*
618 *  This is defined if the port has a special way to report the ISR nesting
619 *  level.  Most ports maintain the variable _ISR_Nest_level.
620 */
621
622#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
623
624/*
625 *  Should be large enough to run all RTEMS tests.  This insures
626 *  that a "reasonable" small application should not have any problems.
627 */
628
629#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
630
631/*
632 *  CPU's worst alignment requirement for data types on a byte boundary.  This
633 *  alignment does not take into account the requirements for the stack.
634 */
635
636#define CPU_ALIGNMENT              8
637
638/*
639 *  This number corresponds to the byte alignment requirement for the
640 *  heap handler.  This alignment requirement may be stricter than that
641 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
642 *  common for the heap to follow the same alignment requirement as
643 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
644 *  then this should be set to CPU_ALIGNMENT.
645 *
646 *  NOTE:  This does not have to be a power of 2.  It does have to
647 *         be greater or equal to than CPU_ALIGNMENT.
648 */
649
650#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
651
652/*
653 *  This number corresponds to the byte alignment requirement for memory
654 *  buffers allocated by the partition manager.  This alignment requirement
655 *  may be stricter than that for the data types alignment specified by
656 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
657 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
658 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
659 *
660 *  NOTE:  This does not have to be a power of 2.  It does have to
661 *         be greater or equal to than CPU_ALIGNMENT.
662 */
663
664#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
665
666/*
667 *  This number corresponds to the byte alignment requirement for the
668 *  stack.  This alignment requirement may be stricter than that for the
669 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
670 *  is strict enough for the stack, then this should be set to 0.
671 *
672 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
673 */
674
675#define CPU_STACK_ALIGNMENT        64
676
677/*
678 *  ISR handler macros
679 */
680
681/*
682 *  Support routine to initialize the RTEMS vector table after it is allocated.
683 */
684
685void _CPU_Initialize_vectors(void);
686
687/*
688 *  Disable all interrupts for an RTEMS critical section.  The previous
689 *  level is returned in _level.
690 */
691
692extern unsigned32 _CPU_ISR_Disable_support(void);
693
694#define _CPU_ISR_Disable( _level ) \
695    do { \
696      (_level) = _CPU_ISR_Disable_support(); \
697    } while ( 0 )
698
699/*
700 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
701 *  This indicates the end of an RTEMS critical section.  The parameter
702 *  _level is not modified.
703 */
704
705void _CPU_ISR_Enable(unsigned32 level);
706
707/*
708 *  This temporarily restores the interrupt to _level before immediately
709 *  disabling them again.  This is used to divide long RTEMS critical
710 *  sections into two or more parts.  The parameter _level is not
711 * modified.
712 */
713
714#define _CPU_ISR_Flash( _level ) \
715  do { \
716      register unsigned32 _ignored = 0; \
717      _CPU_ISR_Enable( (_level) ); \
718      _CPU_ISR_Disable( _ignored ); \
719  } while ( 0 )
720
721/*
722 *  Map interrupt level in task mode onto the hardware that the CPU
723 *  actually provides.  Currently, interrupt levels which do not
724 *  map onto the CPU in a generic fashion are undefined.  Someday,
725 *  it would be nice if these were "mapped" by the application
726 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
727 *  8 - 255 would be available for bsp/application specific meaning.
728 *  This could be used to manage a programmable interrupt controller
729 *  via the rtems_task_mode directive.
730 */
731
732#define _CPU_ISR_Set_level( new_level ) \
733  { \
734    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
735    else                  _CPU_ISR_Enable( 1 ); \
736  }
737
738unsigned32 _CPU_ISR_Get_level( void );
739
740/* end of ISR handler macros */
741
742/* Context handler macros */
743
744/*
745 *  This routine is responsible for somehow restarting the currently
746 *  executing task.  If you are lucky, then all that is necessary
747 *  is restoring the context.  Otherwise, there will need to be
748 *  a special assembly routine which does something special in this
749 *  case.  Context_Restore should work most of the time.  It will
750 *  not work if restarting self conflicts with the stack frame
751 *  assumptions of restoring a context.
752 */
753
754#define _CPU_Context_Restart_self( _the_context ) \
755   _CPU_Context_restore( (_the_context) );
756
757/*
758 *  The purpose of this macro is to allow the initial pointer into
759 *  a floating point context area (used to save the floating point
760 *  context) to be at an arbitrary place in the floating point
761 *  context area.
762 *
763 *  This is necessary because some FP units are designed to have
764 *  their context saved as a stack which grows into lower addresses.
765 *  Other FP units can be saved by simply moving registers into offsets
766 *  from the base of the context area.  Finally some FP units provide
767 *  a "dump context" instruction which could fill in from high to low
768 *  or low to high based on the whim of the CPU designers.
769 */
770
771#define _CPU_Context_Fp_start( _base, _offset ) \
772   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
773
774/*
775 *  This routine initializes the FP context area passed to it to.
776 *  There are a few standard ways in which to initialize the
777 *  floating point context.  The code included for this macro assumes
778 *  that this is a CPU in which a "initial" FP context was saved into
779 *  _CPU_Null_fp_context and it simply copies it to the destination
780 *  context passed to it.
781 *
782 *  Other models include (1) not doing anything, and (2) putting
783 *  a "null FP status word" in the correct place in the FP context.
784 */
785
786#define _CPU_Context_Initialize_fp( _destination ) \
787  { \
788   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
789  }
790
791#define _CPU_Context_save_fp( _fp_context ) \
792    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
793
794#define _CPU_Context_restore_fp( _fp_context ) \
795    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
796
797extern void _CPU_Context_Initialize(
798  Context_Control  *_the_context,
799  unsigned32       *_stack_base,
800  unsigned32        _size,
801  unsigned32        _new_level,
802  void             *_entry_point,
803  boolean           _is_fp
804);
805
806/* end of Context handler macros */
807
808/* Fatal Error manager macros */
809
810/*
811 *  This routine copies _error into a known place -- typically a stack
812 *  location or a register, optionally disables interrupts, and
813 *  halts/stops the CPU.
814 */
815
816#define _CPU_Fatal_halt( _error ) \
817    _CPU_Fatal_error( _error )
818
819/* end of Fatal Error manager macros */
820
821/* Bitfield handler macros */
822
823/*
824 *  This routine sets _output to the bit number of the first bit
825 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
826 *  This type may be either 16 or 32 bits wide although only the 16
827 *  least significant bits will be used.
828 *
829 *  There are a number of variables in using a "find first bit" type
830 *  instruction.
831 *
832 *    (1) What happens when run on a value of zero?
833 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
834 *    (3) The numbering may be zero or one based.
835 *    (4) The "find first bit" instruction may search from MSB or LSB.
836 *
837 *  RTEMS guarantees that (1) will never happen so it is not a concern.
838 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
839 *  _CPU_Priority_bits_index().  These three form a set of routines
840 *  which must logically operate together.  Bits in the _value are
841 *  set and cleared based on masks built by _CPU_Priority_mask().
842 *  The basic major and minor values calculated by _Priority_Major()
843 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
844 *  to properly range between the values returned by the "find first bit"
845 *  instruction.  This makes it possible for _Priority_Get_highest() to
846 *  calculate the major and directly index into the minor table.
847 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
848 *  is the first bit found.
849 *
850 *  This entire "find first bit" and mapping process depends heavily
851 *  on the manner in which a priority is broken into a major and minor
852 *  components with the major being the 4 MSB of a priority and minor
853 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
854 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
855 *  to the lowest priority.
856 *
857 *  If your CPU does not have a "find first bit" instruction, then
858 *  there are ways to make do without it.  Here are a handful of ways
859 *  to implement this in software:
860 *
861 *    - a series of 16 bit test instructions
862 *    - a "binary search using if's"
863 *    - _number = 0
864 *      if _value > 0x00ff
865 *        _value >>=8
866 *        _number = 8;
867 *
868 *      if _value > 0x0000f
869 *        _value >=8
870 *        _number += 4
871 *
872 *      _number += bit_set_table[ _value ]
873 *
874 *    where bit_set_table[ 16 ] has values which indicate the first
875 *      bit set
876 */
877
878/*
879 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
880 *  dependencies on either a native bitscan instruction or an ffs() in the
881 *  C library.
882 */
883 
884#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
885#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
886 
887/* end of Bitfield handler macros */
888 
889/* Priority handler handler macros */
890 
891/*
892 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
893 *  dependencies on either a native bitscan instruction or an ffs() in the
894 *  C library.
895 */
896 
897/* end of Priority handler macros */
898
899/* functions */
900
901/*
902 *  _CPU_Initialize
903 *
904 *  This routine performs CPU dependent initialization.
905 */
906
907void _CPU_Initialize(
908  rtems_cpu_table  *cpu_table,
909  void      (*thread_dispatch)
910);
911
912/*
913 *  _CPU_ISR_install_raw_handler
914 *
915 *  This routine installs a "raw" interrupt handler directly into the
916 *  processor's vector table.
917 */
918 
919void _CPU_ISR_install_raw_handler(
920  unsigned32  vector,
921  proc_ptr    new_handler,
922  proc_ptr   *old_handler
923);
924
925/*
926 *  _CPU_ISR_install_vector
927 *
928 *  This routine installs an interrupt vector.
929 */
930
931void _CPU_ISR_install_vector(
932  unsigned32  vector,
933  proc_ptr    new_handler,
934  proc_ptr   *old_handler
935);
936
937/*
938 *  _CPU_Install_interrupt_stack
939 *
940 *  This routine installs the hardware interrupt stack pointer.
941 *
942 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
943 *         is TRUE.
944 */
945
946void _CPU_Install_interrupt_stack( void );
947
948/*
949 *  _CPU_Thread_Idle_body
950 *
951 *  This routine is the CPU dependent IDLE thread body.
952 *
953 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
954 *         is TRUE.
955 */
956
957void _CPU_Thread_Idle_body( void );
958
959/*
960 *  _CPU_Context_switch
961 *
962 *  This routine switches from the run context to the heir context.
963 */
964
965void _CPU_Context_switch(
966  Context_Control  *run,
967  Context_Control  *heir
968);
969
970/*
971 *  _CPU_Context_restore
972 *
973 *  This routine is generally used only to restart self in an
974 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
975 *
976 *  NOTE: May be unnecessary to reload some registers.
977 */
978
979void _CPU_Context_restore(
980  Context_Control *new_context
981);
982
983/*
984 *  _CPU_Save_float_context
985 *
986 *  This routine saves the floating point context passed to it.
987 */
988
989void _CPU_Save_float_context(
990  Context_Control_fp *fp_context_ptr
991);
992
993/*
994 *  _CPU_Restore_float_context
995 *
996 *  This routine restores the floating point context passed to it.
997 */
998
999void _CPU_Restore_float_context(
1000  Context_Control_fp *fp_context_ptr
1001);
1002
1003
1004void _CPU_ISR_Set_signal_level(
1005  unsigned32 level
1006);
1007
1008void _CPU_Fatal_error(
1009  unsigned32 _error
1010);
1011
1012/*  The following routine swaps the endian format of an unsigned int.
1013 *  It must be static because it is referenced indirectly.
1014 *
1015 *  This version will work on any processor, but if there is a better
1016 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1017 *
1018 *     swap least significant two bytes with 16-bit rotate
1019 *     swap upper and lower 16-bits
1020 *     swap most significant two bytes with 16-bit rotate
1021 *
1022 *  Some CPUs have special instructions which swap a 32-bit quantity in
1023 *  a single instruction (e.g. i486).  It is probably best to avoid
1024 *  an "endian swapping control bit" in the CPU.  One good reason is
1025 *  that interrupts would probably have to be disabled to insure that
1026 *  an interrupt does not try to access the same "chunk" with the wrong
1027 *  endian.  Another good reason is that on some CPUs, the endian bit
1028 *  endianness for ALL fetches -- both code and data -- so the code
1029 *  will be fetched incorrectly.
1030 */
1031 
1032static inline unsigned int CPU_swap_u32(
1033  unsigned int value
1034)
1035{
1036  unsigned32 byte1, byte2, byte3, byte4, swapped;
1037 
1038  byte4 = (value >> 24) & 0xff;
1039  byte3 = (value >> 16) & 0xff;
1040  byte2 = (value >> 8)  & 0xff;
1041  byte1 =  value        & 0xff;
1042 
1043  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1044  return( swapped );
1045}
1046
1047#define CPU_swap_u16( value ) \
1048  (((value&0xff) << 8) | ((value >> 8)&0xff))
1049
1050/*
1051 *  Special Purpose Routines to hide the use of UNIX system calls.
1052 */
1053
1054
1055/*
1056 *  Pointer to a sync io  Handler
1057 */
1058
1059typedef void ( *rtems_sync_io_handler )(
1060  int fd,
1061  boolean read,
1062  boolean wrtie,
1063  boolean except
1064);
1065
1066/* returns -1 if fd to large, 0 is successful */
1067int _CPU_Set_sync_io_handler(
1068  int fd,
1069  boolean read,
1070  boolean write,
1071  boolean except,
1072  rtems_sync_io_handler handler
1073);
1074
1075/* returns -1 if fd to large, o if successful */
1076int _CPU_Clear_sync_io_handler(
1077  int fd
1078);
1079
1080int _CPU_Get_clock_vector( void );
1081
1082void _CPU_Start_clock( 
1083  int microseconds
1084);
1085
1086void _CPU_Stop_clock( void );
1087
1088#if defined(RTEMS_MULTIPROCESSING)
1089
1090void _CPU_SHM_Init( 
1091  unsigned32   maximum_nodes,
1092  boolean      is_master_node,
1093  void       **shm_address,
1094  unsigned32  *shm_length
1095);
1096
1097int _CPU_Get_pid( void );
1098 
1099int _CPU_SHM_Get_vector( void );
1100 
1101void _CPU_SHM_Send_interrupt(
1102  int pid,
1103  int vector
1104);
1105 
1106void _CPU_SHM_Lock( 
1107  int semaphore
1108);
1109
1110void _CPU_SHM_Unlock(
1111  int semaphore
1112);
1113#endif
1114
1115#ifdef __cplusplus
1116}
1117#endif
1118
1119#endif
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