source: rtems/cpukit/score/cpu/unix/cpu.c @ e71ce071

4.104.114.84.95
Last change on this file since e71ce071 was e71ce071, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 22, 1997 at 5:47:16 PM

updated with new license information per Tony Bennett.

  • Property mode set to 100644
File size: 20.3 KB
Line 
1/*
2 *  UNIX Simulator Dependent Source
3 *
4 *  COPYRIGHT (c) 1994,95 by Division Incorporated
5 *
6 *  The license and distribution terms for this file may in
7 *  the file LICENSE in this distribution or at
8 *  http://www.OARcorp.com/rtems/license.html.
9 *
10 *  $Id$
11 */
12
13#include <rtems/system.h>
14#include <rtems/score/isr.h>
15#include <rtems/score/interr.h>
16
17#if defined(solaris2)
18/*
19#undef  _POSIX_C_SOURCE
20#define _POSIX_C_SOURCE 3
21#undef  __STRICT_ANSI__
22#define __STRICT_ANSI__
23*/
24#define __EXTENSIONS__
25#endif
26
27#if defined(linux)
28#define MALLOC_0_RETURNS_NULL
29#endif
30
31#include <sys/types.h>
32#include <sys/times.h>
33#include <stdio.h>
34#include <stdlib.h>
35#include <setjmp.h>
36#include <signal.h>
37#include <time.h>
38#include <sys/time.h>
39#include <errno.h>
40#include <unistd.h>
41#include <sys/ipc.h>
42#include <sys/shm.h>
43#include <sys/sem.h>
44#include <string.h>   /* memset */
45
46#ifndef SA_RESTART
47#define SA_RESTART 0
48#endif
49
50typedef struct {
51  jmp_buf   regs;
52  unsigned32  isr_level;
53} Context_Control_overlay;
54
55void  _CPU_Signal_initialize(void);
56void  _CPU_Stray_signal(int);
57void  _CPU_ISR_Handler(int);
58
59static sigset_t         _CPU_Signal_mask;
60static Context_Control_overlay
61          _CPU_Context_Default_with_ISRs_enabled CPU_STRUCTURE_ALIGNMENT;
62static Context_Control_overlay
63          _CPU_Context_Default_with_ISRs_disabled CPU_STRUCTURE_ALIGNMENT;
64
65/*
66 * Which cpu are we? Used by libcpu and libbsp.
67 */
68
69int cpu_number;
70
71/*PAGE
72 *
73 *  _CPU_ISR_From_CPU_Init
74 */
75
76sigset_t  posix_empty_mask;
77
78void _CPU_ISR_From_CPU_Init()
79{
80  unsigned32        i;
81  proc_ptr          old_handler;
82
83  /*
84   * Generate an empty mask to be used by disable_support
85   */
86
87  sigemptyset(&posix_empty_mask);
88
89  /*
90   * Block all the signals except SIGTRAP for the debugger
91   * and fatal error signals.
92   */
93
94  (void) sigfillset(&_CPU_Signal_mask);
95  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
96  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
97  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
98  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
99  (void) sigdelset(&_CPU_Signal_mask, SIGSEGV);
100  (void) sigdelset(&_CPU_Signal_mask, SIGBUS);
101  (void) sigdelset(&_CPU_Signal_mask, SIGFPE);
102
103  _CPU_ISR_Enable(1);
104
105  /*
106   * Set the handler for all signals to be signal_handler
107   * which will then vector out to the correct handler
108   * for whichever signal actually happened. Initially
109   * set the vectors to the stray signal handler.
110   */
111
112  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
113      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
114
115  _CPU_Signal_initialize();
116}
117
118void _CPU_Signal_initialize( void )
119{
120  struct sigaction  act;
121  sigset_t          mask;
122
123  /* mark them all active except for TraceTrap  and Abort */
124
125  mask = _CPU_Signal_mask;
126  sigprocmask(SIG_UNBLOCK, &mask, 0);
127
128  act.sa_handler = _CPU_ISR_Handler;
129  act.sa_mask = mask;
130  act.sa_flags = SA_RESTART;
131
132  sigaction(SIGHUP, &act, 0);
133  sigaction(SIGINT, &act, 0);
134  sigaction(SIGQUIT, &act, 0);
135  sigaction(SIGILL, &act, 0);
136#ifdef SIGEMT
137  sigaction(SIGEMT, &act, 0);
138#endif
139  sigaction(SIGFPE, &act, 0);
140  sigaction(SIGKILL, &act, 0);
141  sigaction(SIGBUS, &act, 0);
142  sigaction(SIGSEGV, &act, 0);
143#ifdef SIGSYS
144  sigaction(SIGSYS, &act, 0);
145#endif
146  sigaction(SIGPIPE, &act, 0);
147  sigaction(SIGALRM, &act, 0);
148  sigaction(SIGTERM, &act, 0);
149  sigaction(SIGUSR1, &act, 0);
150  sigaction(SIGUSR2, &act, 0);
151  sigaction(SIGCHLD, &act, 0);
152  sigaction(SIGCLD, &act, 0);
153  sigaction(SIGPWR, &act, 0);
154  sigaction(SIGVTALRM, &act, 0);
155  sigaction(SIGPROF, &act, 0);
156  sigaction(SIGIO, &act, 0);
157  sigaction(SIGWINCH, &act, 0);
158  sigaction(SIGSTOP, &act, 0);
159  sigaction(SIGTTIN, &act, 0);
160  sigaction(SIGTTOU, &act, 0);
161  sigaction(SIGURG, &act, 0);
162#ifdef SIGLOST
163    sigaction(SIGLOST, &act, 0);
164#endif
165}
166
167/*PAGE
168 *
169 *  _CPU_Context_From_CPU_Init
170 */
171
172void _CPU_Context_From_CPU_Init()
173{
174
175#if defined(hppa1_1) && defined(RTEMS_UNIXLIB_SETJMP)
176    /*
177     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
178     * will handle the full 32 floating point registers.
179     */
180
181    {
182      extern unsigned32 _SYSTEM_ID;
183
184      _SYSTEM_ID = 0x20c;
185    }
186#endif
187
188  /*
189   *  get default values to use in _CPU_Context_Initialize()
190   */
191
192
193  (void) memset(
194    &_CPU_Context_Default_with_ISRs_enabled,
195    0,
196    sizeof(Context_Control)
197  );
198  (void) memset(
199    &_CPU_Context_Default_with_ISRs_disabled,
200    0,
201    sizeof(Context_Control)
202  );
203
204  _CPU_ISR_Set_level( 0 );
205  _CPU_Context_switch(
206    (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled,
207    (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled
208  );
209
210  _CPU_ISR_Set_level( 1 );
211  _CPU_Context_switch(
212    (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled,
213    (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled
214  );
215}
216
217/*PAGE
218 *
219 *  _CPU_ISR_Get_level
220 */
221
222unsigned32 _CPU_ISR_Get_level( void )
223{
224  sigset_t old_mask;
225
226  sigprocmask(SIG_BLOCK, 0, &old_mask);
227
228  if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)))
229      return 1;
230
231  return 0;
232}
233
234/*  _CPU_Initialize
235 *
236 *  This routine performs processor dependent initialization.
237 *
238 *  INPUT PARAMETERS:
239 *    cpu_table       - CPU table to initialize
240 *    thread_dispatch - address of disptaching routine
241 */
242
243
244void _CPU_Initialize(
245  rtems_cpu_table  *cpu_table,
246  void            (*thread_dispatch)      /* ignored on this CPU */
247)
248{
249  /*
250   *  The thread_dispatch argument is the address of the entry point
251   *  for the routine called at the end of an ISR once it has been
252   *  decided a context switch is necessary.  On some compilation
253   *  systems it is difficult to call a high-level language routine
254   *  from assembly.  This allows us to trick these systems.
255   *
256   *  If you encounter this problem save the entry point in a CPU
257   *  dependent variable.
258   */
259
260  _CPU_Thread_dispatch_pointer = thread_dispatch;
261
262  /*
263   * XXX; If there is not an easy way to initialize the FP context
264   *      during Context_Initialize, then it is usually easier to
265   *      save an "uninitialized" FP context here and copy it to
266   *      the task's during Context_Initialize.
267   */
268
269  /* XXX: FP context initialization support */
270
271  _CPU_Table = *cpu_table;
272
273  _CPU_ISR_From_CPU_Init();
274
275  _CPU_Context_From_CPU_Init();
276
277}
278
279/*PAGE
280 *
281 *  _CPU_ISR_install_raw_handler
282 */
283
284void _CPU_ISR_install_raw_handler(
285  unsigned32  vector,
286  proc_ptr    new_handler,
287  proc_ptr   *old_handler
288)
289{
290  _CPU_Fatal_halt( 0xdeaddead );
291}
292
293/*PAGE
294 *
295 *  _CPU_ISR_install_vector
296 *
297 *  This kernel routine installs the RTEMS handler for the
298 *  specified vector.
299 *
300 *  Input parameters:
301 *    vector      - interrupt vector number
302 *    old_handler - former ISR for this vector number
303 *    new_handler - replacement ISR for this vector number
304 *
305 *  Output parameters:  NONE
306 *
307 */
308
309
310void _CPU_ISR_install_vector(
311  unsigned32  vector,
312  proc_ptr    new_handler,
313  proc_ptr   *old_handler
314)
315{
316   *old_handler = _ISR_Vector_table[ vector ];
317
318   /*
319    *  If the interrupt vector table is a table of pointer to isr entry
320    *  points, then we need to install the appropriate RTEMS interrupt
321    *  handler for this vector number.
322    */
323
324   /*
325    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
326    *  be used by the _CPU_ISR_Handler so the user gets control.
327    */
328
329    _ISR_Vector_table[ vector ] = new_handler;
330}
331
332/*PAGE
333 *
334 *  _CPU_Install_interrupt_stack
335 */
336
337void _CPU_Install_interrupt_stack( void )
338{
339}
340
341/*PAGE
342 *
343 *  _CPU_Thread_Idle_body
344 *
345 *  Stop until we get a signal which is the logically the same thing
346 *  entering low-power or sleep mode on a real processor and waiting for
347 *  an interrupt.  This significantly reduces the consumption of host
348 *  CPU cycles which is again similar to low power mode.
349 */
350
351void _CPU_Thread_Idle_body( void )
352{
353  while (1) {
354#ifdef RTEMS_DEBUG
355    /* interrupts had better be enabled at this point! */
356    if (_CPU_ISR_Get_level() != 0)
357       abort();
358#endif
359    pause();
360  }
361
362}
363
364/*PAGE
365 *
366 *  _CPU_Context_Initialize
367 */
368
369void _CPU_Context_Initialize(
370  Context_Control  *_the_context,
371  unsigned32       *_stack_base,
372  unsigned32        _size,
373  unsigned32        _new_level,
374  void             *_entry_point,
375  boolean           _is_fp
376)
377{
378  unsigned32  *addr;
379  unsigned32   jmp_addr;
380  unsigned32   _stack_low;   /* lowest "stack aligned" address */
381  unsigned32   _stack_high;  /* highest "stack aligned" address */
382  unsigned32   _the_size;
383
384  jmp_addr = (unsigned32) _entry_point;
385
386  /*
387   *  On CPUs with stacks which grow down, we build the stack
388   *  based on the _stack_high address.  On CPUs with stacks which
389   *  grow up, we build the stack based on the _stack_low address.
390   */
391
392  _stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1;
393  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
394
395  _stack_high = (unsigned32)(_stack_base) + _size;
396  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
397
398  if (_stack_high > _stack_low)
399    _the_size = _stack_high - _stack_low;
400  else
401    _the_size = _stack_low - _stack_high;
402
403  /*
404   * Slam our jmp_buf template into the context we are creating
405   */
406
407  if ( _new_level == 0 )
408      *_the_context = *(Context_Control *)
409                         &_CPU_Context_Default_with_ISRs_enabled;
410  else
411      *_the_context = *(Context_Control *)
412                         &_CPU_Context_Default_with_ISRs_disabled;
413
414  addr = (unsigned32 *)_the_context;
415
416#if defined(hppa1_1)
417  *(addr + RP_OFF) = jmp_addr;
418  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
419
420  /*
421   * See if we are using shared libraries by checking
422   * bit 30 in 24 off of newp. If bit 30 is set then
423   * we are using shared libraries and the jump address
424   * points to the pointer, so we put that into rp instead.
425   */
426
427  if (jmp_addr & 0x40000000) {
428    jmp_addr &= 0xfffffffc;
429     *(addr + RP_OFF) = *(unsigned32 *)jmp_addr;
430  }
431#elif defined(sparc)
432
433  /*
434   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
435   *  diagram of the stack.
436   */
437
438  asm ("ta  0x03");            /* flush registers */
439
440  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
441  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
442  *(addr + FP_OFF) = (unsigned32)(_stack_high);
443
444#elif defined(i386) || defined(__i386__)
445
446    /*
447     *  This information was gathered by disassembling setjmp().
448     */
449
450    {
451      unsigned32 stack_ptr;
452
453      stack_ptr = _stack_high - CPU_FRAME_SIZE;
454
455      *(addr + EBX_OFF) = 0xFEEDFEED;
456      *(addr + ESI_OFF) = 0xDEADDEAD;
457      *(addr + EDI_OFF) = 0xDEAFDEAF;
458      *(addr + EBP_OFF) = stack_ptr;
459      *(addr + ESP_OFF) = stack_ptr;
460      *(addr + RET_OFF) = jmp_addr;
461
462      addr = (unsigned32 *) stack_ptr;
463
464      addr[ 0 ] = jmp_addr;
465      addr[ 1 ] = (unsigned32) stack_ptr;
466      addr[ 2 ] = (unsigned32) stack_ptr;
467    }
468
469#else
470#error "UNKNOWN CPU!!!"
471#endif
472
473}
474
475/*PAGE
476 *
477 *  _CPU_Context_restore
478 */
479
480void _CPU_Context_restore(
481  Context_Control  *next
482)
483{
484  Context_Control_overlay *nextp = (Context_Control_overlay *)next;
485
486  _CPU_ISR_Enable(nextp->isr_level);
487  longjmp( nextp->regs, 0 );
488}
489
490/*PAGE
491 *
492 *  _CPU_Context_switch
493 */
494
495static void do_jump(
496  Context_Control_overlay *currentp,
497  Context_Control_overlay *nextp
498);
499
500void _CPU_Context_switch(
501  Context_Control  *current,
502  Context_Control  *next
503)
504{
505  Context_Control_overlay *currentp = (Context_Control_overlay *)current;
506  Context_Control_overlay *nextp = (Context_Control_overlay *)next;
507#if 0
508  int status;
509#endif
510
511  currentp->isr_level = _CPU_ISR_Disable_support();
512
513  do_jump( currentp, nextp );
514
515#if 0
516  if (sigsetjmp(currentp->regs, 1) == 0) {    /* Save the current context */
517     siglongjmp(nextp->regs, 0);           /* Switch to the new context */
518     _Internal_error_Occurred(
519         INTERNAL_ERROR_CORE,
520         TRUE,
521         status
522       );
523  }
524#endif
525
526#ifdef RTEMS_DEBUG
527    if (_CPU_ISR_Get_level() == 0)
528       abort();
529#endif
530
531  _CPU_ISR_Enable(currentp->isr_level);
532}
533
534static void do_jump(
535  Context_Control_overlay *currentp,
536  Context_Control_overlay *nextp
537)
538{
539  int status;
540
541  if (setjmp(currentp->regs) == 0) {    /* Save the current context */
542     longjmp(nextp->regs, 0);           /* Switch to the new context */
543     _Internal_error_Occurred(
544         INTERNAL_ERROR_CORE,
545         TRUE,
546         status
547       );
548  }
549}
550
551/*PAGE
552 *
553 *  _CPU_Save_float_context
554 */
555
556void _CPU_Save_float_context(
557  Context_Control_fp *fp_context
558)
559{
560}
561
562/*PAGE
563 *
564 *  _CPU_Restore_float_context
565 */
566
567void _CPU_Restore_float_context(
568  Context_Control_fp *fp_context
569)
570{
571}
572
573/*PAGE
574 *
575 *  _CPU_ISR_Disable_support
576 */
577
578unsigned32 _CPU_ISR_Disable_support(void)
579{
580  int status;
581  sigset_t  old_mask;
582
583  status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
584  if ( status )
585    _Internal_error_Occurred(
586      INTERNAL_ERROR_CORE,
587      TRUE,
588      status
589    );
590
591  if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)))
592    return 1;
593
594  return 0;
595}
596
597/*PAGE
598 *
599 *  _CPU_ISR_Enable
600 */
601
602void _CPU_ISR_Enable(
603  unsigned32 level
604)
605{
606  int status;
607
608  if (level == 0)
609    status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
610  else
611    status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
612
613  if ( status )
614    _Internal_error_Occurred(
615      INTERNAL_ERROR_CORE,
616      TRUE,
617      status
618    );
619}
620
621/*PAGE
622 *
623 *  _CPU_ISR_Handler
624 *
625 *  External interrupt handler.
626 *  This is installed as a UNIX signal handler.
627 *  It vectors out to specific user interrupt handlers.
628 */
629
630void _CPU_ISR_Handler(int vector)
631{
632  extern void        _Thread_Dispatch(void);
633  extern unsigned32  _Thread_Dispatch_disable_level;
634  extern boolean     _Context_Switch_necessary;
635
636  if (_ISR_Nest_level++ == 0) {
637      /* switch to interrupt stack */
638  }
639
640  _Thread_Dispatch_disable_level++;
641
642  if (_ISR_Vector_table[vector]) {
643     _ISR_Vector_table[vector](vector);
644  } else {
645     _CPU_Stray_signal(vector);
646  }
647
648  if (_ISR_Nest_level-- == 0) {
649      /* switch back to original stack */
650  }
651
652  _Thread_Dispatch_disable_level--;
653
654  if (_Thread_Dispatch_disable_level == 0 &&
655      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
656      _ISR_Signals_to_thread_executing = FALSE;
657      _CPU_ISR_Enable(0);
658      _Thread_Dispatch();
659  }
660}
661
662/*PAGE
663 *
664 *  _CPU_Stray_signal
665 */
666
667void _CPU_Stray_signal(int sig_num)
668{
669  char buffer[ 4 ];
670
671  /*
672   * print "stray" msg about ones which that might mean something
673   * Avoid using the stdio section of the library.
674   * The following is generally safe.
675   */
676
677  switch (sig_num)
678  {
679      case SIGCLD:
680          break;
681
682      default:
683      {
684        /*
685         *  We avoid using the stdio section of the library.
686         *  The following is generally safe
687         */
688
689        int digit;
690        int number = sig_num;
691        int len = 0;
692
693        digit = number / 100;
694        number %= 100;
695        if (digit) buffer[len++] = '0' + digit;
696
697        digit = number / 10;
698        number %= 10;
699        if (digit || len) buffer[len++] = '0' + digit;
700
701        digit = number;
702        buffer[len++] = '0' + digit;
703
704        buffer[ len++ ] = '\n';
705
706        write( 2, "Stray signal ", 13 );
707        write( 2, buffer, len );
708
709      }
710  }
711
712  /*
713   * If it was a "fatal" signal, then exit here
714   * If app code has installed a hander for one of these, then
715   * we won't call _CPU_Stray_signal, so this is ok.
716   */
717
718  switch (sig_num) {
719      case SIGINT:
720      case SIGHUP:
721      case SIGQUIT:
722      case SIGILL:
723#ifdef SIGEMT
724      case SIGEMT:
725#endif
726      case SIGKILL:
727      case SIGBUS:
728      case SIGSEGV:
729      case SIGTERM:
730      case SIGIOT:
731        _CPU_Fatal_error(0x100 + sig_num);
732  }
733}
734
735/*PAGE
736 *
737 *  _CPU_Fatal_error
738 */
739
740void _CPU_Fatal_error(unsigned32 error)
741{
742  setitimer(ITIMER_REAL, 0, 0);
743
744  if ( error ) {
745#ifdef RTEMS_DEBUG
746    abort();
747#endif
748    if (getenv("RTEMS_DEBUG"))
749      abort();
750  }
751
752  _exit(error);
753}
754
755/*
756 *  Special Purpose Routines to hide the use of UNIX system calls.
757 */
758
759int _CPU_Get_clock_vector( void )
760{
761  return SIGALRM;
762}
763
764void _CPU_Start_clock(
765  int microseconds
766)
767{
768  struct itimerval  new;
769
770  new.it_value.tv_sec = 0;
771  new.it_value.tv_usec = microseconds;
772  new.it_interval.tv_sec = 0;
773  new.it_interval.tv_usec = microseconds;
774
775  setitimer(ITIMER_REAL, &new, 0);
776}
777
778void _CPU_Stop_clock( void )
779{
780  struct itimerval  new;
781  struct sigaction  act;
782
783  /*
784   * Set the SIGALRM signal to ignore any last
785   * signals that might come in while we are
786   * disarming the timer and removing the interrupt
787   * vector.
788   */
789
790  (void) memset(&act, 0, sizeof(act));
791  act.sa_handler = SIG_IGN;
792
793  sigaction(SIGALRM, &act, 0);
794
795  (void) memset(&new, 0, sizeof(new));
796  setitimer(ITIMER_REAL, &new, 0);
797}
798
799int  _CPU_SHM_Semid;
800extern       void fix_syscall_errno( void );
801
802void _CPU_SHM_Init(
803  unsigned32   maximum_nodes,
804  boolean      is_master_node,
805  void       **shm_address,
806  unsigned32  *shm_length
807)
808{
809  int          i;
810  int          shmid;
811  char        *shm_addr;
812  key_t        shm_key;
813  key_t        sem_key;
814  int          status = 0;  /* to avoid unitialized warnings */
815  int          shm_size;
816
817  if (getenv("RTEMS_SHM_KEY"))
818    shm_key = strtol(getenv("RTEMS_SHM_KEY"), 0, 0);
819  else
820#ifdef RTEMS_SHM_KEY
821    shm_key = RTEMS_SHM_KEY;
822#else
823    shm_key = 0xa000;
824#endif
825
826    if (getenv("RTEMS_SHM_SIZE"))
827      shm_size = strtol(getenv("RTEMS_SHM_SIZE"), 0, 0);
828    else
829#ifdef RTEMS_SHM_SIZE
830      shm_size = RTEMS_SHM_SIZE;
831#else
832      shm_size = 64 * 1024;
833#endif
834
835    if (getenv("RTEMS_SHM_SEMAPHORE_KEY"))
836      sem_key = strtol(getenv("RTEMS_SHM_SEMAPHORE_KEY"), 0, 0);
837    else
838#ifdef RTEMS_SHM_SEMAPHORE_KEY
839      sem_key = RTEMS_SHM_SEMAPHORE_KEY;
840#else
841      sem_key = 0xa001;
842#endif
843
844    shmid = shmget(shm_key, shm_size, IPC_CREAT | 0660);
845    if ( shmid == -1 ) {
846      fix_syscall_errno(); /* in case of newlib */
847      perror( "shmget" );
848      _CPU_Fatal_halt( 0xdead0001 );
849    }
850
851    shm_addr = shmat(shmid, (char *)0, SHM_RND);
852    if ( shm_addr == (void *)-1 ) {
853      fix_syscall_errno(); /* in case of newlib */
854      perror( "shmat" );
855      _CPU_Fatal_halt( 0xdead0002 );
856    }
857
858    _CPU_SHM_Semid = semget(sem_key, maximum_nodes + 1, IPC_CREAT | 0660);
859    if ( _CPU_SHM_Semid == -1 ) {
860      fix_syscall_errno(); /* in case of newlib */
861      perror( "semget" );
862      _CPU_Fatal_halt( 0xdead0003 );
863    }
864
865    if ( is_master_node ) {
866      for ( i=0 ; i <= maximum_nodes ; i++ ) {
867#if defined(solaris2)
868        union semun {
869          int val;
870          struct semid_ds *buf;
871          ushort *array;
872        } help;
873
874        help.val = 1;
875        status = semctl( _CPU_SHM_Semid, i, SETVAL, help );
876#endif
877#if defined(hpux)
878        status = semctl( _CPU_SHM_Semid, i, SETVAL, 1 );
879#endif
880
881        fix_syscall_errno(); /* in case of newlib */
882        if ( status == -1 ) {
883          _CPU_Fatal_halt( 0xdead0004 );
884        }
885      }
886    }
887
888  *shm_address = shm_addr;
889  *shm_length = shm_size;
890
891}
892
893int _CPU_Get_pid( void )
894{
895  return getpid();
896}
897
898/*
899 * Define this to use signals for MPCI shared memory driver.
900 * If undefined, the shared memory driver will poll from the
901 * clock interrupt.
902 * Ref: ../shmsupp/getcfg.c
903 *
904 * BEWARE:: many UN*X kernels and debuggers become severely confused when
905 *          debugging programs which use signals.  The problem is *much*
906 *          worse when using multiple signals, since ptrace(2) tends to
907 *          drop all signals except 1 in the case of multiples.
908 *          On hpux9, this problem was so bad, we couldn't use interrupts
909 *          with the shared memory driver if we ever hoped to debug
910 *          RTEMS programs.
911 *          Maybe systems that use /proc don't have this problem...
912 */
913
914
915int _CPU_SHM_Get_vector( void )
916{
917#ifdef CPU_USE_SHM_INTERRUPTS
918  return SIGUSR1;
919#else
920  return 0;
921#endif
922}
923
924void _CPU_SHM_Send_interrupt(
925  int pid,
926  int vector
927)
928{
929  kill((pid_t) pid, vector);
930}
931
932void _CPU_SHM_Lock(
933  int semaphore
934)
935{
936  struct sembuf      sb;
937  int                status;
938
939  sb.sem_num = semaphore;
940  sb.sem_op  = -1;
941  sb.sem_flg = 0;
942
943  while (1) {
944    status = semop(_CPU_SHM_Semid, &sb, 1);
945    if ( status >= 0 )
946      break;
947    if ( status == -1 ) {
948       fix_syscall_errno();    /* in case of newlib */
949        if (errno == EINTR)
950            continue;
951        perror("shm lock");
952        _CPU_Fatal_halt( 0xdead0005 );
953    }
954  }
955
956}
957
958void _CPU_SHM_Unlock(
959  int semaphore
960)
961{
962  struct sembuf  sb;
963  int            status;
964
965  sb.sem_num = semaphore;
966  sb.sem_op  = 1;
967  sb.sem_flg = 0;
968
969  while (1) {
970    status = semop(_CPU_SHM_Semid, &sb, 1);
971    if ( status >= 0 )
972      break;
973
974    if ( status == -1 ) {
975      fix_syscall_errno();    /* in case of newlib */
976      if (errno == EINTR)
977          continue;
978      perror("shm unlock");
979      _CPU_Fatal_halt( 0xdead0006 );
980    }
981  }
982
983}
Note: See TracBrowser for help on using the repository browser.