1 | /* |
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2 | * UNIX Simulator Dependent Source |
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3 | * |
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4 | * |
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5 | * To anyone who acknowledges that this file is provided "AS IS" |
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6 | * without any express or implied warranty: |
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7 | * permission to use, copy, modify, and distribute this file |
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8 | * for any purpose is hereby granted without fee, provided that |
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9 | * the above copyright notice and this notice appears in all |
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10 | * copies, and that the name of Division Incorporated not be |
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11 | * used in advertising or publicity pertaining to distribution |
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12 | * of the software without specific, written prior permission. |
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13 | * Division Incorporated makes no representations about the |
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14 | * suitability of this software for any purpose. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #include <rtems/system.h> |
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20 | #include <rtems/score/isr.h> |
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21 | #include <rtems/score/interr.h> |
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22 | |
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23 | #if defined(solaris2) |
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24 | /* |
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25 | #undef _POSIX_C_SOURCE |
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26 | #define _POSIX_C_SOURCE 3 |
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27 | #undef __STRICT_ANSI__ |
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28 | #define __STRICT_ANSI__ |
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29 | */ |
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30 | #define __EXTENSIONS__ |
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31 | #endif |
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32 | |
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33 | #if defined(linux) |
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34 | #define MALLOC_0_RETURNS_NULL |
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35 | #endif |
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36 | |
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37 | #include <sys/types.h> |
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38 | #include <sys/times.h> |
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39 | #include <stdio.h> |
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40 | #include <stdlib.h> |
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41 | #include <setjmp.h> |
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42 | #include <signal.h> |
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43 | #include <time.h> |
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44 | #include <sys/time.h> |
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45 | #include <errno.h> |
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46 | #include <unistd.h> |
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47 | #include <sys/ipc.h> |
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48 | #include <sys/shm.h> |
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49 | #include <sys/sem.h> |
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50 | #include <string.h> /* memset */ |
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51 | |
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52 | #ifndef SA_RESTART |
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53 | #define SA_RESTART 0 |
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54 | #endif |
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55 | |
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56 | typedef struct { |
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57 | jmp_buf regs; |
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58 | unsigned32 isr_level; |
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59 | } Context_Control_overlay; |
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60 | |
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61 | void _CPU_Signal_initialize(void); |
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62 | void _CPU_Stray_signal(int); |
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63 | void _CPU_ISR_Handler(int); |
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64 | |
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65 | static sigset_t _CPU_Signal_mask; |
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66 | static Context_Control_overlay _CPU_Context_Default_with_ISRs_enabled; |
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67 | static Context_Control_overlay _CPU_Context_Default_with_ISRs_disabled; |
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68 | |
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69 | /* |
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70 | * Which cpu are we? Used by libcpu and libbsp. |
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71 | */ |
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72 | |
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73 | int cpu_number; |
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74 | |
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75 | /*PAGE |
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76 | * |
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77 | * _CPU_ISR_From_CPU_Init |
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78 | */ |
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79 | |
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80 | sigset_t posix_empty_mask; |
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81 | |
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82 | void _CPU_ISR_From_CPU_Init() |
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83 | { |
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84 | unsigned32 i; |
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85 | proc_ptr old_handler; |
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86 | |
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87 | /* |
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88 | * Generate an empty mask to be used by disable_support |
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89 | */ |
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90 | |
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91 | sigemptyset(&posix_empty_mask); |
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92 | |
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93 | /* |
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94 | * Block all the signals except SIGTRAP for the debugger |
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95 | * and fatal error signals. |
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96 | */ |
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97 | |
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98 | (void) sigfillset(&_CPU_Signal_mask); |
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99 | (void) sigdelset(&_CPU_Signal_mask, SIGTRAP); |
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100 | (void) sigdelset(&_CPU_Signal_mask, SIGABRT); |
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101 | (void) sigdelset(&_CPU_Signal_mask, SIGIOT); |
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102 | (void) sigdelset(&_CPU_Signal_mask, SIGCONT); |
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103 | (void) sigdelset(&_CPU_Signal_mask, SIGSEGV); |
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104 | (void) sigdelset(&_CPU_Signal_mask, SIGBUS); |
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105 | (void) sigdelset(&_CPU_Signal_mask, SIGFPE); |
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106 | |
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107 | _CPU_ISR_Enable(1); |
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108 | |
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109 | /* |
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110 | * Set the handler for all signals to be signal_handler |
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111 | * which will then vector out to the correct handler |
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112 | * for whichever signal actually happened. Initially |
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113 | * set the vectors to the stray signal handler. |
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114 | */ |
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115 | |
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116 | for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) |
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117 | (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler); |
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118 | |
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119 | _CPU_Signal_initialize(); |
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120 | } |
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121 | |
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122 | void _CPU_Signal_initialize( void ) |
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123 | { |
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124 | struct sigaction act; |
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125 | sigset_t mask; |
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126 | |
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127 | /* mark them all active except for TraceTrap and Abort */ |
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128 | |
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129 | mask = _CPU_Signal_mask; |
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130 | sigprocmask(SIG_UNBLOCK, &mask, 0); |
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131 | |
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132 | act.sa_handler = _CPU_ISR_Handler; |
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133 | act.sa_mask = mask; |
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134 | act.sa_flags = SA_RESTART; |
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135 | |
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136 | sigaction(SIGHUP, &act, 0); |
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137 | sigaction(SIGINT, &act, 0); |
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138 | sigaction(SIGQUIT, &act, 0); |
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139 | sigaction(SIGILL, &act, 0); |
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140 | #ifdef SIGEMT |
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141 | sigaction(SIGEMT, &act, 0); |
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142 | #endif |
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143 | sigaction(SIGFPE, &act, 0); |
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144 | sigaction(SIGKILL, &act, 0); |
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145 | sigaction(SIGBUS, &act, 0); |
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146 | sigaction(SIGSEGV, &act, 0); |
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147 | #ifdef SIGSYS |
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148 | sigaction(SIGSYS, &act, 0); |
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149 | #endif |
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150 | sigaction(SIGPIPE, &act, 0); |
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151 | sigaction(SIGALRM, &act, 0); |
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152 | sigaction(SIGTERM, &act, 0); |
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153 | sigaction(SIGUSR1, &act, 0); |
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154 | sigaction(SIGUSR2, &act, 0); |
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155 | sigaction(SIGCHLD, &act, 0); |
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156 | sigaction(SIGCLD, &act, 0); |
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157 | sigaction(SIGPWR, &act, 0); |
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158 | sigaction(SIGVTALRM, &act, 0); |
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159 | sigaction(SIGPROF, &act, 0); |
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160 | sigaction(SIGIO, &act, 0); |
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161 | sigaction(SIGWINCH, &act, 0); |
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162 | sigaction(SIGSTOP, &act, 0); |
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163 | sigaction(SIGTTIN, &act, 0); |
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164 | sigaction(SIGTTOU, &act, 0); |
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165 | sigaction(SIGURG, &act, 0); |
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166 | #ifdef SIGLOST |
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167 | sigaction(SIGLOST, &act, 0); |
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168 | #endif |
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169 | } |
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170 | |
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171 | /*PAGE |
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172 | * |
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173 | * _CPU_Context_From_CPU_Init |
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174 | */ |
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175 | |
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176 | void _CPU_Context_From_CPU_Init() |
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177 | { |
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178 | |
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179 | #if defined(hppa1_1) && defined(RTEMS_UNIXLIB_SETJMP) |
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180 | /* |
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181 | * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp |
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182 | * will handle the full 32 floating point registers. |
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183 | */ |
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184 | |
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185 | { |
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186 | extern unsigned32 _SYSTEM_ID; |
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187 | |
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188 | _SYSTEM_ID = 0x20c; |
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189 | } |
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190 | #endif |
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191 | |
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192 | /* |
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193 | * get default values to use in _CPU_Context_Initialize() |
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194 | */ |
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195 | |
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196 | |
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197 | (void) memset( |
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198 | &_CPU_Context_Default_with_ISRs_enabled, |
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199 | 0, |
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200 | sizeof(Context_Control) |
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201 | ); |
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202 | (void) memset( |
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203 | &_CPU_Context_Default_with_ISRs_disabled, |
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204 | 0, |
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205 | sizeof(Context_Control) |
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206 | ); |
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207 | |
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208 | _CPU_ISR_Set_level( 0 ); |
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209 | _CPU_Context_switch( |
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210 | (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled, |
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211 | (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled |
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212 | ); |
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213 | |
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214 | _CPU_ISR_Set_level( 1 ); |
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215 | _CPU_Context_switch( |
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216 | (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled, |
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217 | (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled |
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218 | ); |
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219 | } |
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220 | |
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221 | /*PAGE |
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222 | * |
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223 | * _CPU_ISR_Get_level |
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224 | */ |
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225 | |
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226 | unsigned32 _CPU_ISR_Get_level( void ) |
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227 | { |
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228 | sigset_t old_mask; |
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229 | |
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230 | sigprocmask(SIG_BLOCK, 0, &old_mask); |
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231 | |
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232 | if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t))) |
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233 | return 1; |
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234 | |
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235 | return 0; |
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236 | } |
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237 | |
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238 | /* _CPU_Initialize |
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239 | * |
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240 | * This routine performs processor dependent initialization. |
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241 | * |
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242 | * INPUT PARAMETERS: |
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243 | * cpu_table - CPU table to initialize |
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244 | * thread_dispatch - address of disptaching routine |
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245 | */ |
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246 | |
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247 | |
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248 | void _CPU_Initialize( |
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249 | rtems_cpu_table *cpu_table, |
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250 | void (*thread_dispatch) /* ignored on this CPU */ |
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251 | ) |
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252 | { |
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253 | /* |
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254 | * The thread_dispatch argument is the address of the entry point |
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255 | * for the routine called at the end of an ISR once it has been |
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256 | * decided a context switch is necessary. On some compilation |
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257 | * systems it is difficult to call a high-level language routine |
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258 | * from assembly. This allows us to trick these systems. |
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259 | * |
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260 | * If you encounter this problem save the entry point in a CPU |
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261 | * dependent variable. |
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262 | */ |
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263 | |
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264 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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265 | |
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266 | /* |
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267 | * XXX; If there is not an easy way to initialize the FP context |
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268 | * during Context_Initialize, then it is usually easier to |
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269 | * save an "uninitialized" FP context here and copy it to |
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270 | * the task's during Context_Initialize. |
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271 | */ |
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272 | |
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273 | /* XXX: FP context initialization support */ |
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274 | |
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275 | _CPU_Table = *cpu_table; |
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276 | |
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277 | _CPU_ISR_From_CPU_Init(); |
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278 | |
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279 | _CPU_Context_From_CPU_Init(); |
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280 | |
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281 | } |
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282 | |
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283 | /*PAGE |
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284 | * |
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285 | * _CPU_ISR_install_raw_handler |
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286 | */ |
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287 | |
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288 | void _CPU_ISR_install_raw_handler( |
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289 | unsigned32 vector, |
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290 | proc_ptr new_handler, |
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291 | proc_ptr *old_handler |
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292 | ) |
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293 | { |
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294 | _CPU_Fatal_halt( 0xdeaddead ); |
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295 | } |
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296 | |
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297 | /*PAGE |
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298 | * |
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299 | * _CPU_ISR_install_vector |
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300 | * |
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301 | * This kernel routine installs the RTEMS handler for the |
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302 | * specified vector. |
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303 | * |
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304 | * Input parameters: |
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305 | * vector - interrupt vector number |
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306 | * old_handler - former ISR for this vector number |
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307 | * new_handler - replacement ISR for this vector number |
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308 | * |
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309 | * Output parameters: NONE |
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310 | * |
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311 | */ |
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312 | |
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313 | |
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314 | void _CPU_ISR_install_vector( |
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315 | unsigned32 vector, |
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316 | proc_ptr new_handler, |
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317 | proc_ptr *old_handler |
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318 | ) |
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319 | { |
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320 | *old_handler = _ISR_Vector_table[ vector ]; |
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321 | |
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322 | /* |
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323 | * If the interrupt vector table is a table of pointer to isr entry |
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324 | * points, then we need to install the appropriate RTEMS interrupt |
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325 | * handler for this vector number. |
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326 | */ |
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327 | |
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328 | /* |
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329 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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330 | * be used by the _CPU_ISR_Handler so the user gets control. |
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331 | */ |
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332 | |
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333 | _ISR_Vector_table[ vector ] = new_handler; |
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334 | } |
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335 | |
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336 | /*PAGE |
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337 | * |
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338 | * _CPU_Install_interrupt_stack |
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339 | */ |
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340 | |
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341 | void _CPU_Install_interrupt_stack( void ) |
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342 | { |
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343 | } |
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344 | |
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345 | /*PAGE |
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346 | * |
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347 | * _CPU_Thread_Idle_body |
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348 | * |
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349 | * Stop until we get a signal which is the logically the same thing |
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350 | * entering low-power or sleep mode on a real processor and waiting for |
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351 | * an interrupt. This significantly reduces the consumption of host |
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352 | * CPU cycles which is again similar to low power mode. |
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353 | */ |
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354 | |
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355 | void _CPU_Thread_Idle_body( void ) |
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356 | { |
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357 | while (1) { |
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358 | #ifdef RTEMS_DEBUG |
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359 | /* interrupts had better be enabled at this point! */ |
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360 | if (_CPU_ISR_Get_level() != 0) |
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361 | abort(); |
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362 | #endif |
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363 | pause(); |
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364 | } |
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365 | |
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366 | } |
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367 | |
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368 | /*PAGE |
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369 | * |
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370 | * _CPU_Context_Initialize |
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371 | */ |
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372 | |
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373 | void _CPU_Context_Initialize( |
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374 | Context_Control *_the_context, |
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375 | unsigned32 *_stack_base, |
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376 | unsigned32 _size, |
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377 | unsigned32 _new_level, |
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378 | void *_entry_point, |
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379 | boolean _is_fp |
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380 | ) |
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381 | { |
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382 | unsigned32 *addr; |
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383 | unsigned32 jmp_addr; |
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384 | unsigned32 _stack_low; /* lowest "stack aligned" address */ |
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385 | unsigned32 _stack_high; /* highest "stack aligned" address */ |
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386 | unsigned32 _the_size; |
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387 | |
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388 | jmp_addr = (unsigned32) _entry_point; |
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389 | |
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390 | /* |
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391 | * On CPUs with stacks which grow down, we build the stack |
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392 | * based on the _stack_high address. On CPUs with stacks which |
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393 | * grow up, we build the stack based on the _stack_low address. |
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394 | */ |
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395 | |
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396 | _stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1; |
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397 | _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); |
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398 | |
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399 | _stack_high = (unsigned32)(_stack_base) + _size; |
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400 | _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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401 | |
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402 | if (_stack_high > _stack_low) |
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403 | _the_size = _stack_high - _stack_low; |
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404 | else |
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405 | _the_size = _stack_low - _stack_high; |
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406 | |
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407 | /* |
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408 | * Slam our jmp_buf template into the context we are creating |
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409 | */ |
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410 | |
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411 | if ( _new_level == 0 ) |
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412 | *_the_context = *(Context_Control *) |
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413 | &_CPU_Context_Default_with_ISRs_enabled; |
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414 | else |
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415 | *_the_context = *(Context_Control *) |
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416 | &_CPU_Context_Default_with_ISRs_disabled; |
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417 | |
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418 | addr = (unsigned32 *)_the_context; |
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419 | |
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420 | #if defined(hppa1_1) |
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421 | *(addr + RP_OFF) = jmp_addr; |
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422 | *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE); |
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423 | |
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424 | /* |
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425 | * See if we are using shared libraries by checking |
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426 | * bit 30 in 24 off of newp. If bit 30 is set then |
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427 | * we are using shared libraries and the jump address |
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428 | * points to the pointer, so we put that into rp instead. |
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429 | */ |
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430 | |
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431 | if (jmp_addr & 0x40000000) { |
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432 | jmp_addr &= 0xfffffffc; |
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433 | *(addr + RP_OFF) = *(unsigned32 *)jmp_addr; |
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434 | } |
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435 | #elif defined(sparc) |
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436 | |
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437 | /* |
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438 | * See /usr/include/sys/stack.h in Solaris 2.3 for a nice |
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439 | * diagram of the stack. |
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440 | */ |
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441 | |
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442 | asm ("ta 0x03"); /* flush registers */ |
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443 | |
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444 | *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; |
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445 | *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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446 | *(addr + FP_OFF) = (unsigned32)(_stack_high); |
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447 | |
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448 | #elif defined(i386) |
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449 | |
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450 | /* |
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451 | * This information was gathered by disassembling setjmp(). |
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452 | */ |
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453 | |
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454 | { |
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455 | unsigned32 stack_ptr; |
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456 | |
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457 | stack_ptr = _stack_high - CPU_FRAME_SIZE; |
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458 | |
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459 | *(addr + EBX_OFF) = 0xFEEDFEED; |
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460 | *(addr + ESI_OFF) = 0xDEADDEAD; |
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461 | *(addr + EDI_OFF) = 0xDEAFDEAF; |
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462 | *(addr + EBP_OFF) = stack_ptr; |
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463 | *(addr + ESP_OFF) = stack_ptr; |
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464 | *(addr + RET_OFF) = jmp_addr; |
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465 | |
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466 | addr = (unsigned32 *) stack_ptr; |
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467 | |
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468 | addr[ 0 ] = jmp_addr; |
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469 | addr[ 1 ] = (unsigned32) stack_ptr; |
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470 | addr[ 2 ] = (unsigned32) stack_ptr; |
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471 | } |
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472 | |
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473 | #else |
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474 | #error "UNKNOWN CPU!!!" |
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475 | #endif |
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476 | |
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477 | } |
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478 | |
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479 | /*PAGE |
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480 | * |
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481 | * _CPU_Context_restore |
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482 | */ |
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483 | |
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484 | void _CPU_Context_restore( |
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485 | Context_Control *next |
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486 | ) |
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487 | { |
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488 | Context_Control_overlay *nextp = (Context_Control_overlay *)next; |
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489 | |
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490 | _CPU_ISR_Enable(nextp->isr_level); |
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491 | longjmp( nextp->regs, 0 ); |
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492 | } |
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493 | |
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494 | /*PAGE |
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495 | * |
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496 | * _CPU_Context_switch |
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497 | */ |
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498 | |
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499 | static void do_jump( |
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500 | Context_Control_overlay *currentp, |
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501 | Context_Control_overlay *nextp |
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502 | ); |
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503 | |
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504 | void _CPU_Context_switch( |
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505 | Context_Control *current, |
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506 | Context_Control *next |
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507 | ) |
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508 | { |
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509 | Context_Control_overlay *currentp = (Context_Control_overlay *)current; |
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510 | Context_Control_overlay *nextp = (Context_Control_overlay *)next; |
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511 | #if 0 |
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512 | int status; |
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513 | #endif |
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514 | |
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515 | currentp->isr_level = _CPU_ISR_Disable_support(); |
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516 | |
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517 | do_jump( currentp, nextp ); |
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518 | |
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519 | #if 0 |
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520 | if (sigsetjmp(currentp->regs, 1) == 0) { /* Save the current context */ |
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521 | siglongjmp(nextp->regs, 0); /* Switch to the new context */ |
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522 | _Internal_error_Occurred( |
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523 | INTERNAL_ERROR_CORE, |
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524 | TRUE, |
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525 | status |
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526 | ); |
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527 | } |
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528 | #endif |
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529 | |
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530 | #ifdef RTEMS_DEBUG |
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531 | if (_CPU_ISR_Get_level() == 0) |
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532 | abort(); |
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533 | #endif |
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534 | |
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535 | _CPU_ISR_Enable(currentp->isr_level); |
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536 | } |
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537 | |
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538 | static void do_jump( |
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539 | Context_Control_overlay *currentp, |
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540 | Context_Control_overlay *nextp |
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541 | ) |
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542 | { |
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543 | int status; |
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544 | |
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545 | if (setjmp(currentp->regs) == 0) { /* Save the current context */ |
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546 | longjmp(nextp->regs, 0); /* Switch to the new context */ |
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547 | _Internal_error_Occurred( |
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548 | INTERNAL_ERROR_CORE, |
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549 | TRUE, |
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550 | status |
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551 | ); |
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552 | } |
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553 | } |
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554 | |
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555 | /*PAGE |
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556 | * |
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557 | * _CPU_Save_float_context |
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558 | */ |
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559 | |
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560 | void _CPU_Save_float_context( |
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561 | Context_Control_fp *fp_context |
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562 | ) |
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563 | { |
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564 | } |
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565 | |
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566 | /*PAGE |
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567 | * |
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568 | * _CPU_Restore_float_context |
---|
569 | */ |
---|
570 | |
---|
571 | void _CPU_Restore_float_context( |
---|
572 | Context_Control_fp *fp_context |
---|
573 | ) |
---|
574 | { |
---|
575 | } |
---|
576 | |
---|
577 | /*PAGE |
---|
578 | * |
---|
579 | * _CPU_ISR_Disable_support |
---|
580 | */ |
---|
581 | |
---|
582 | unsigned32 _CPU_ISR_Disable_support(void) |
---|
583 | { |
---|
584 | int status; |
---|
585 | sigset_t old_mask; |
---|
586 | |
---|
587 | status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask); |
---|
588 | if ( status ) |
---|
589 | _Internal_error_Occurred( |
---|
590 | INTERNAL_ERROR_CORE, |
---|
591 | TRUE, |
---|
592 | status |
---|
593 | ); |
---|
594 | |
---|
595 | if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t))) |
---|
596 | return 1; |
---|
597 | |
---|
598 | return 0; |
---|
599 | } |
---|
600 | |
---|
601 | /*PAGE |
---|
602 | * |
---|
603 | * _CPU_ISR_Enable |
---|
604 | */ |
---|
605 | |
---|
606 | void _CPU_ISR_Enable( |
---|
607 | unsigned32 level |
---|
608 | ) |
---|
609 | { |
---|
610 | int status; |
---|
611 | |
---|
612 | if (level == 0) |
---|
613 | status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0); |
---|
614 | else |
---|
615 | status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
---|
616 | |
---|
617 | if ( status ) |
---|
618 | _Internal_error_Occurred( |
---|
619 | INTERNAL_ERROR_CORE, |
---|
620 | TRUE, |
---|
621 | status |
---|
622 | ); |
---|
623 | } |
---|
624 | |
---|
625 | /*PAGE |
---|
626 | * |
---|
627 | * _CPU_ISR_Handler |
---|
628 | * |
---|
629 | * External interrupt handler. |
---|
630 | * This is installed as a UNIX signal handler. |
---|
631 | * It vectors out to specific user interrupt handlers. |
---|
632 | */ |
---|
633 | |
---|
634 | void _CPU_ISR_Handler(int vector) |
---|
635 | { |
---|
636 | extern void _Thread_Dispatch(void); |
---|
637 | extern unsigned32 _Thread_Dispatch_disable_level; |
---|
638 | extern boolean _Context_Switch_necessary; |
---|
639 | |
---|
640 | if (_ISR_Nest_level++ == 0) { |
---|
641 | /* switch to interrupt stack */ |
---|
642 | } |
---|
643 | |
---|
644 | _Thread_Dispatch_disable_level++; |
---|
645 | |
---|
646 | if (_ISR_Vector_table[vector]) { |
---|
647 | _ISR_Vector_table[vector](vector); |
---|
648 | } else { |
---|
649 | _CPU_Stray_signal(vector); |
---|
650 | } |
---|
651 | |
---|
652 | if (_ISR_Nest_level-- == 0) { |
---|
653 | /* switch back to original stack */ |
---|
654 | } |
---|
655 | |
---|
656 | _Thread_Dispatch_disable_level--; |
---|
657 | |
---|
658 | if (_Thread_Dispatch_disable_level == 0 && |
---|
659 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { |
---|
660 | _ISR_Signals_to_thread_executing = FALSE; |
---|
661 | _CPU_ISR_Enable(0); |
---|
662 | _Thread_Dispatch(); |
---|
663 | } |
---|
664 | } |
---|
665 | |
---|
666 | /*PAGE |
---|
667 | * |
---|
668 | * _CPU_Stray_signal |
---|
669 | */ |
---|
670 | |
---|
671 | void _CPU_Stray_signal(int sig_num) |
---|
672 | { |
---|
673 | char buffer[ 4 ]; |
---|
674 | |
---|
675 | /* |
---|
676 | * print "stray" msg about ones which that might mean something |
---|
677 | * Avoid using the stdio section of the library. |
---|
678 | * The following is generally safe. |
---|
679 | */ |
---|
680 | |
---|
681 | switch (sig_num) |
---|
682 | { |
---|
683 | case SIGCLD: |
---|
684 | break; |
---|
685 | |
---|
686 | default: |
---|
687 | { |
---|
688 | /* |
---|
689 | * We avoid using the stdio section of the library. |
---|
690 | * The following is generally safe |
---|
691 | */ |
---|
692 | |
---|
693 | int digit; |
---|
694 | int number = sig_num; |
---|
695 | int len = 0; |
---|
696 | |
---|
697 | digit = number / 100; |
---|
698 | number %= 100; |
---|
699 | if (digit) buffer[len++] = '0' + digit; |
---|
700 | |
---|
701 | digit = number / 10; |
---|
702 | number %= 10; |
---|
703 | if (digit || len) buffer[len++] = '0' + digit; |
---|
704 | |
---|
705 | digit = number; |
---|
706 | buffer[len++] = '0' + digit; |
---|
707 | |
---|
708 | buffer[ len++ ] = '\n'; |
---|
709 | |
---|
710 | write( 2, "Stray signal ", 13 ); |
---|
711 | write( 2, buffer, len ); |
---|
712 | |
---|
713 | } |
---|
714 | } |
---|
715 | |
---|
716 | /* |
---|
717 | * If it was a "fatal" signal, then exit here |
---|
718 | * If app code has installed a hander for one of these, then |
---|
719 | * we won't call _CPU_Stray_signal, so this is ok. |
---|
720 | */ |
---|
721 | |
---|
722 | switch (sig_num) { |
---|
723 | case SIGINT: |
---|
724 | case SIGHUP: |
---|
725 | case SIGQUIT: |
---|
726 | case SIGILL: |
---|
727 | #ifdef SIGEMT |
---|
728 | case SIGEMT: |
---|
729 | #endif |
---|
730 | case SIGKILL: |
---|
731 | case SIGBUS: |
---|
732 | case SIGSEGV: |
---|
733 | case SIGTERM: |
---|
734 | case SIGIOT: |
---|
735 | _CPU_Fatal_error(0x100 + sig_num); |
---|
736 | } |
---|
737 | } |
---|
738 | |
---|
739 | /*PAGE |
---|
740 | * |
---|
741 | * _CPU_Fatal_error |
---|
742 | */ |
---|
743 | |
---|
744 | void _CPU_Fatal_error(unsigned32 error) |
---|
745 | { |
---|
746 | setitimer(ITIMER_REAL, 0, 0); |
---|
747 | |
---|
748 | if ( error ) { |
---|
749 | #ifdef RTEMS_DEBUG |
---|
750 | abort(); |
---|
751 | #endif |
---|
752 | if (getenv("RTEMS_DEBUG")) |
---|
753 | abort(); |
---|
754 | } |
---|
755 | |
---|
756 | _exit(error); |
---|
757 | } |
---|
758 | |
---|
759 | /* |
---|
760 | * Special Purpose Routines to hide the use of UNIX system calls. |
---|
761 | */ |
---|
762 | |
---|
763 | int _CPU_Get_clock_vector( void ) |
---|
764 | { |
---|
765 | return SIGALRM; |
---|
766 | } |
---|
767 | |
---|
768 | void _CPU_Start_clock( |
---|
769 | int microseconds |
---|
770 | ) |
---|
771 | { |
---|
772 | struct itimerval new; |
---|
773 | |
---|
774 | new.it_value.tv_sec = 0; |
---|
775 | new.it_value.tv_usec = microseconds; |
---|
776 | new.it_interval.tv_sec = 0; |
---|
777 | new.it_interval.tv_usec = microseconds; |
---|
778 | |
---|
779 | setitimer(ITIMER_REAL, &new, 0); |
---|
780 | } |
---|
781 | |
---|
782 | void _CPU_Stop_clock( void ) |
---|
783 | { |
---|
784 | struct itimerval new; |
---|
785 | struct sigaction act; |
---|
786 | |
---|
787 | /* |
---|
788 | * Set the SIGALRM signal to ignore any last |
---|
789 | * signals that might come in while we are |
---|
790 | * disarming the timer and removing the interrupt |
---|
791 | * vector. |
---|
792 | */ |
---|
793 | |
---|
794 | (void) memset(&act, 0, sizeof(act)); |
---|
795 | act.sa_handler = SIG_IGN; |
---|
796 | |
---|
797 | sigaction(SIGALRM, &act, 0); |
---|
798 | |
---|
799 | (void) memset(&new, 0, sizeof(new)); |
---|
800 | setitimer(ITIMER_REAL, &new, 0); |
---|
801 | } |
---|
802 | |
---|
803 | int _CPU_SHM_Semid; |
---|
804 | extern void fix_syscall_errno( void ); |
---|
805 | |
---|
806 | void _CPU_SHM_Init( |
---|
807 | unsigned32 maximum_nodes, |
---|
808 | boolean is_master_node, |
---|
809 | void **shm_address, |
---|
810 | unsigned32 *shm_length |
---|
811 | ) |
---|
812 | { |
---|
813 | int i; |
---|
814 | int shmid; |
---|
815 | char *shm_addr; |
---|
816 | key_t shm_key; |
---|
817 | key_t sem_key; |
---|
818 | int status; |
---|
819 | int shm_size; |
---|
820 | |
---|
821 | if (getenv("RTEMS_SHM_KEY")) |
---|
822 | shm_key = strtol(getenv("RTEMS_SHM_KEY"), 0, 0); |
---|
823 | else |
---|
824 | #ifdef RTEMS_SHM_KEY |
---|
825 | shm_key = RTEMS_SHM_KEY; |
---|
826 | #else |
---|
827 | shm_key = 0xa000; |
---|
828 | #endif |
---|
829 | |
---|
830 | if (getenv("RTEMS_SHM_SIZE")) |
---|
831 | shm_size = strtol(getenv("RTEMS_SHM_SIZE"), 0, 0); |
---|
832 | else |
---|
833 | #ifdef RTEMS_SHM_SIZE |
---|
834 | shm_size = RTEMS_SHM_SIZE; |
---|
835 | #else |
---|
836 | shm_size = 64 * 1024; |
---|
837 | #endif |
---|
838 | |
---|
839 | if (getenv("RTEMS_SHM_SEMAPHORE_KEY")) |
---|
840 | sem_key = strtol(getenv("RTEMS_SHM_SEMAPHORE_KEY"), 0, 0); |
---|
841 | else |
---|
842 | #ifdef RTEMS_SHM_SEMAPHORE_KEY |
---|
843 | sem_key = RTEMS_SHM_SEMAPHORE_KEY; |
---|
844 | #else |
---|
845 | sem_key = 0xa001; |
---|
846 | #endif |
---|
847 | |
---|
848 | shmid = shmget(shm_key, shm_size, IPC_CREAT | 0660); |
---|
849 | if ( shmid == -1 ) { |
---|
850 | fix_syscall_errno(); /* in case of newlib */ |
---|
851 | perror( "shmget" ); |
---|
852 | _CPU_Fatal_halt( 0xdead0001 ); |
---|
853 | } |
---|
854 | |
---|
855 | shm_addr = shmat(shmid, (char *)0, SHM_RND); |
---|
856 | if ( shm_addr == (void *)-1 ) { |
---|
857 | fix_syscall_errno(); /* in case of newlib */ |
---|
858 | perror( "shmat" ); |
---|
859 | _CPU_Fatal_halt( 0xdead0002 ); |
---|
860 | } |
---|
861 | |
---|
862 | _CPU_SHM_Semid = semget(sem_key, maximum_nodes + 1, IPC_CREAT | 0660); |
---|
863 | if ( _CPU_SHM_Semid == -1 ) { |
---|
864 | fix_syscall_errno(); /* in case of newlib */ |
---|
865 | perror( "semget" ); |
---|
866 | _CPU_Fatal_halt( 0xdead0003 ); |
---|
867 | } |
---|
868 | |
---|
869 | if ( is_master_node ) { |
---|
870 | for ( i=0 ; i <= maximum_nodes ; i++ ) { |
---|
871 | #if defined(solaris2) |
---|
872 | union semun { |
---|
873 | int val; |
---|
874 | struct semid_ds *buf; |
---|
875 | ushort *array; |
---|
876 | } help; |
---|
877 | |
---|
878 | help.val = 1; |
---|
879 | status = semctl( _CPU_SHM_Semid, i, SETVAL, help ); |
---|
880 | #endif |
---|
881 | #if defined(hpux) |
---|
882 | status = semctl( _CPU_SHM_Semid, i, SETVAL, 1 ); |
---|
883 | #endif |
---|
884 | |
---|
885 | fix_syscall_errno(); /* in case of newlib */ |
---|
886 | if ( status == -1 ) { |
---|
887 | _CPU_Fatal_halt( 0xdead0004 ); |
---|
888 | } |
---|
889 | } |
---|
890 | } |
---|
891 | |
---|
892 | *shm_address = shm_addr; |
---|
893 | *shm_length = shm_size; |
---|
894 | |
---|
895 | } |
---|
896 | |
---|
897 | int _CPU_Get_pid( void ) |
---|
898 | { |
---|
899 | return getpid(); |
---|
900 | } |
---|
901 | |
---|
902 | /* |
---|
903 | * Define this to use signals for MPCI shared memory driver. |
---|
904 | * If undefined, the shared memory driver will poll from the |
---|
905 | * clock interrupt. |
---|
906 | * Ref: ../shmsupp/getcfg.c |
---|
907 | * |
---|
908 | * BEWARE:: many UN*X kernels and debuggers become severely confused when |
---|
909 | * debugging programs which use signals. The problem is *much* |
---|
910 | * worse when using multiple signals, since ptrace(2) tends to |
---|
911 | * drop all signals except 1 in the case of multiples. |
---|
912 | * On hpux9, this problem was so bad, we couldn't use interrupts |
---|
913 | * with the shared memory driver if we ever hoped to debug |
---|
914 | * RTEMS programs. |
---|
915 | * Maybe systems that use /proc don't have this problem... |
---|
916 | */ |
---|
917 | |
---|
918 | |
---|
919 | int _CPU_SHM_Get_vector( void ) |
---|
920 | { |
---|
921 | #ifdef CPU_USE_SHM_INTERRUPTS |
---|
922 | return SIGUSR1; |
---|
923 | #else |
---|
924 | return 0; |
---|
925 | #endif |
---|
926 | } |
---|
927 | |
---|
928 | void _CPU_SHM_Send_interrupt( |
---|
929 | int pid, |
---|
930 | int vector |
---|
931 | ) |
---|
932 | { |
---|
933 | kill((pid_t) pid, vector); |
---|
934 | } |
---|
935 | |
---|
936 | void _CPU_SHM_Lock( |
---|
937 | int semaphore |
---|
938 | ) |
---|
939 | { |
---|
940 | struct sembuf sb; |
---|
941 | int status; |
---|
942 | |
---|
943 | sb.sem_num = semaphore; |
---|
944 | sb.sem_op = -1; |
---|
945 | sb.sem_flg = 0; |
---|
946 | |
---|
947 | while (1) { |
---|
948 | status = semop(_CPU_SHM_Semid, &sb, 1); |
---|
949 | if ( status >= 0 ) |
---|
950 | break; |
---|
951 | if ( status == -1 ) { |
---|
952 | fix_syscall_errno(); /* in case of newlib */ |
---|
953 | if (errno == EINTR) |
---|
954 | continue; |
---|
955 | perror("shm lock"); |
---|
956 | _CPU_Fatal_halt( 0xdead0005 ); |
---|
957 | } |
---|
958 | } |
---|
959 | |
---|
960 | } |
---|
961 | |
---|
962 | void _CPU_SHM_Unlock( |
---|
963 | int semaphore |
---|
964 | ) |
---|
965 | { |
---|
966 | struct sembuf sb; |
---|
967 | int status; |
---|
968 | |
---|
969 | sb.sem_num = semaphore; |
---|
970 | sb.sem_op = 1; |
---|
971 | sb.sem_flg = 0; |
---|
972 | |
---|
973 | while (1) { |
---|
974 | status = semop(_CPU_SHM_Semid, &sb, 1); |
---|
975 | if ( status >= 0 ) |
---|
976 | break; |
---|
977 | |
---|
978 | if ( status == -1 ) { |
---|
979 | fix_syscall_errno(); /* in case of newlib */ |
---|
980 | if (errno == EINTR) |
---|
981 | continue; |
---|
982 | perror("shm unlock"); |
---|
983 | _CPU_Fatal_halt( 0xdead0006 ); |
---|
984 | } |
---|
985 | } |
---|
986 | |
---|
987 | } |
---|