source: rtems/cpukit/score/cpu/unix/cpu.c @ c64e4ed4

4.104.114.84.95
Last change on this file since c64e4ed4 was c64e4ed4, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 15, 1996 at 9:50:28 PM

updates from Tony Bennett for PA and UNIX ports

  • Property mode set to 100644
File size: 19.5 KB
Line 
1/*
2 *  UNIX Simulator Dependent Source
3 *
4 *
5 *  To anyone who acknowledges that this file is provided "AS IS"
6 *  without any express or implied warranty:
7 *      permission to use, copy, modify, and distribute this file
8 *      for any purpose is hereby granted without fee, provided that
9 *      the above copyright notice and this notice appears in all
10 *      copies, and that the name of Division Incorporated not be
11 *      used in advertising or publicity pertaining to distribution
12 *      of the software without specific, written prior permission.
13 *      Division Incorporated makes no representations about the
14 *      suitability of this software for any purpose.
15 *
16 *  $Id$
17 */
18
19#include <rtems/system.h>
20#include <rtems/score/isr.h>
21#include <rtems/score/interr.h>
22
23#if defined(solaris2)
24/*
25#undef  _POSIX_C_SOURCE
26#define _POSIX_C_SOURCE 3
27#undef  __STRICT_ANSI__
28#define __STRICT_ANSI__
29*/
30#define __EXTENSIONS__
31#endif
32 
33#if defined(linux)
34#define MALLOC_0_RETURNS_NULL
35#endif
36 
37#include <stdio.h>
38#include <stdlib.h>
39#include <setjmp.h>
40#include <signal.h>
41#include <time.h>
42#include <sys/time.h>
43#include <sys/types.h>
44#include <errno.h>
45#include <unistd.h>
46#include <sys/ipc.h>
47#include <sys/shm.h>
48#include <sys/sem.h>
49
50#ifndef SA_RESTART
51#define SA_RESTART 0
52#endif
53
54typedef struct {
55  jmp_buf   regs;
56  sigset_t  isr_level;
57} Context_Control_overlay;
58
59void  _CPU_Signal_initialize(void);
60void  _CPU_Stray_signal(int);
61void  _CPU_ISR_Handler(int);
62
63sigset_t         _CPU_Signal_mask;
64Context_Control  _CPU_Context_Default_with_ISRs_enabled;
65Context_Control  _CPU_Context_Default_with_ISRs_disabled;
66
67/*
68 * Which cpu are we? Used by libcpu and libbsp.
69 */
70
71int cpu_number;
72
73/*PAGE
74 *
75 *  _CPU_ISR_From_CPU_Init
76 */
77
78sigset_t  posix_empty_mask;
79
80void _CPU_ISR_From_CPU_Init()
81{
82  unsigned32        i;
83  proc_ptr          old_handler;
84
85  /*
86   * Generate an empty mask to be used by disable_support
87   */
88
89  sigemptyset(&posix_empty_mask);
90
91  /*
92   * Block all the signals except SIGTRAP for the debugger
93   * and SIGABRT for fatal errors.
94   */
95
96  (void) sigfillset(&_CPU_Signal_mask);
97  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
98  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
99  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
100  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
101
102  _CPU_ISR_Enable(1);
103
104  /*
105   * Set the handler for all signals to be signal_handler
106   * which will then vector out to the correct handler
107   * for whichever signal actually happened. Initially
108   * set the vectors to the stray signal handler.
109   */
110
111  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
112      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
113
114  _CPU_Signal_initialize();
115}
116
117void _CPU_Signal_initialize( void )
118{
119  struct sigaction  act;
120  sigset_t          mask;
121
122  /* mark them all active except for TraceTrap  and Abort */
123
124  sigfillset(&mask);
125  sigdelset(&mask, SIGTRAP);
126  sigdelset(&mask, SIGABRT);
127  sigdelset(&mask, SIGIOT);
128  sigdelset(&mask, SIGCONT);
129  sigprocmask(SIG_UNBLOCK, &mask, 0);
130
131  act.sa_handler = _CPU_ISR_Handler;
132  act.sa_mask = mask;
133  act.sa_flags = SA_RESTART;
134
135  sigaction(SIGHUP, &act, 0);
136  sigaction(SIGINT, &act, 0);
137  sigaction(SIGQUIT, &act, 0);
138  sigaction(SIGILL, &act, 0);
139#ifdef SIGEMT
140  sigaction(SIGEMT, &act, 0);
141#endif
142  sigaction(SIGFPE, &act, 0);
143  sigaction(SIGKILL, &act, 0);
144  sigaction(SIGBUS, &act, 0);
145  sigaction(SIGSEGV, &act, 0);
146#ifdef SIGSYS
147  sigaction(SIGSYS, &act, 0);
148#endif
149  sigaction(SIGPIPE, &act, 0);
150  sigaction(SIGALRM, &act, 0);
151  sigaction(SIGTERM, &act, 0);
152  sigaction(SIGUSR1, &act, 0);
153  sigaction(SIGUSR2, &act, 0);
154  sigaction(SIGCHLD, &act, 0);
155  sigaction(SIGCLD, &act, 0);
156  sigaction(SIGPWR, &act, 0);
157  sigaction(SIGVTALRM, &act, 0);
158  sigaction(SIGPROF, &act, 0);
159  sigaction(SIGIO, &act, 0);
160  sigaction(SIGWINCH, &act, 0);
161  sigaction(SIGSTOP, &act, 0);
162  sigaction(SIGTTIN, &act, 0);
163  sigaction(SIGTTOU, &act, 0);
164  sigaction(SIGURG, &act, 0);
165#ifdef SIGLOST
166    sigaction(SIGLOST, &act, 0);
167#endif
168
169}
170
171/*PAGE
172 *
173 *  _CPU_Context_From_CPU_Init
174 */
175
176void _CPU_Context_From_CPU_Init()
177{
178
179#if defined(hppa1_1) && defined(RTEMS_UNIXLIB_SETJMP)
180    /*
181     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
182     * will handle the full 32 floating point registers.
183     *
184     *  NOTE:  Is this a bug in HPUX9?
185     */
186
187    {
188      extern unsigned32 _SYSTEM_ID;
189
190      _SYSTEM_ID = 0x20c;
191    }
192#endif
193
194  /*
195   *  get default values to use in _CPU_Context_Initialize()
196   */
197
198  _CPU_ISR_Set_level( 0 );
199  _CPU_Context_switch(
200    &_CPU_Context_Default_with_ISRs_enabled,
201    &_CPU_Context_Default_with_ISRs_enabled
202  );
203
204  _CPU_ISR_Set_level( 1 );
205  _CPU_Context_switch(
206    &_CPU_Context_Default_with_ISRs_disabled,
207    &_CPU_Context_Default_with_ISRs_disabled
208  );
209}
210
211/*PAGE
212 *
213 *  _CPU_ISR_Get_level
214 */
215
216sigset_t GET_old_mask;
217
218unsigned32 _CPU_ISR_Get_level( void )
219{
220/*  sigset_t  old_mask; */
221   unsigned32 old_level;
222 
223  sigprocmask(0, 0, &GET_old_mask);
224 
225  if (memcmp((void *)&posix_empty_mask, (void *)&GET_old_mask, sizeof(sigset_t)))
226    old_level = 1;
227  else 
228    old_level = 0;
229
230  return old_level;
231}
232
233/*  _CPU_Initialize
234 *
235 *  This routine performs processor dependent initialization.
236 *
237 *  INPUT PARAMETERS:
238 *    cpu_table       - CPU table to initialize
239 *    thread_dispatch - address of disptaching routine
240 */
241
242
243void _CPU_Initialize(
244  rtems_cpu_table  *cpu_table,
245  void            (*thread_dispatch)      /* ignored on this CPU */
246)
247{
248  /*
249   *  The thread_dispatch argument is the address of the entry point
250   *  for the routine called at the end of an ISR once it has been
251   *  decided a context switch is necessary.  On some compilation
252   *  systems it is difficult to call a high-level language routine
253   *  from assembly.  This allows us to trick these systems.
254   *
255   *  If you encounter this problem save the entry point in a CPU
256   *  dependent variable.
257   */
258
259  _CPU_Thread_dispatch_pointer = thread_dispatch;
260
261  /*
262   * XXX; If there is not an easy way to initialize the FP context
263   *      during Context_Initialize, then it is usually easier to
264   *      save an "uninitialized" FP context here and copy it to
265   *      the task's during Context_Initialize.
266   */
267
268  /* XXX: FP context initialization support */
269
270  _CPU_Table = *cpu_table;
271
272  _CPU_ISR_From_CPU_Init();
273
274  _CPU_Context_From_CPU_Init();
275
276}
277
278/*PAGE
279 *
280 *  _CPU_ISR_install_raw_handler
281 */
282
283void _CPU_ISR_install_raw_handler(
284  unsigned32  vector,
285  proc_ptr    new_handler,
286  proc_ptr   *old_handler
287)
288{
289  _CPU_Fatal_halt( 0xdeaddead );
290}
291
292/*PAGE
293 *
294 *  _CPU_ISR_install_vector
295 *
296 *  This kernel routine installs the RTEMS handler for the
297 *  specified vector.
298 *
299 *  Input parameters:
300 *    vector      - interrupt vector number
301 *    old_handler - former ISR for this vector number
302 *    new_handler - replacement ISR for this vector number
303 *
304 *  Output parameters:  NONE
305 *
306 */
307
308
309void _CPU_ISR_install_vector(
310  unsigned32  vector,
311  proc_ptr    new_handler,
312  proc_ptr   *old_handler
313)
314{
315   *old_handler = _ISR_Vector_table[ vector ];
316
317   /*
318    *  If the interrupt vector table is a table of pointer to isr entry
319    *  points, then we need to install the appropriate RTEMS interrupt
320    *  handler for this vector number.
321    */
322
323   /*
324    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
325    *  be used by the _CPU_ISR_Handler so the user gets control.
326    */
327
328    _ISR_Vector_table[ vector ] = new_handler;
329}
330
331/*PAGE
332 *
333 *  _CPU_Install_interrupt_stack
334 */
335
336void _CPU_Install_interrupt_stack( void )
337{
338}
339
340/*PAGE
341 *
342 *  _CPU_Internal_threads_Idle_thread_body
343 *
344 *  Stop until we get a signal which is the logically the same thing
345 *  entering low-power or sleep mode on a real processor and waiting for
346 *  an interrupt.  This significantly reduces the consumption of host
347 *  CPU cycles which is again similar to low power mode.
348 */
349
350void _CPU_Internal_threads_Idle_thread_body( void )
351{
352  while (1)
353    pause();
354}
355
356/*PAGE
357 *
358 *  _CPU_Context_Initialize
359 */
360
361void _CPU_Context_Initialize(
362  Context_Control  *_the_context,
363  unsigned32       *_stack_base,
364  unsigned32        _size,
365  unsigned32        _new_level,
366  void             *_entry_point,
367  boolean           _is_fp
368)
369{
370  void        *source;
371  unsigned32  *addr;
372  unsigned32   jmp_addr;
373  unsigned32   _stack_low;   /* lowest "stack aligned" address */
374  unsigned32   _stack_high;  /* highest "stack aligned" address */
375  unsigned32   _the_size;
376
377  jmp_addr = (unsigned32) _entry_point;
378
379  /*
380   *  On CPUs with stacks which grow down, we build the stack
381   *  based on the _stack_high address.  On CPUs with stacks which
382   *  grow up, we build the stack based on the _stack_low address. 
383   */
384
385  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
386  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
387
388  _stack_high = ((unsigned32)(_stack_base) + _size);
389  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
390
391  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
392
393  /*
394   * Slam our jmp_buf template into the context we are creating
395   */
396
397  if ( _new_level == 0 )
398    source = &_CPU_Context_Default_with_ISRs_enabled;
399  else
400    source = &_CPU_Context_Default_with_ISRs_disabled;
401     
402  memcpy(_the_context, source, sizeof(Context_Control) ); /* sizeof(jmp_buf)); */
403
404  addr = (unsigned32 *)_the_context;
405
406#if defined(hppa1_1)
407  *(addr + RP_OFF) = jmp_addr;
408  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
409
410  /*
411   * See if we are using shared libraries by checking
412   * bit 30 in 24 off of newp. If bit 30 is set then
413   * we are using shared libraries and the jump address
414   * is at what 24 off of newp points to so shove that
415   * into 24 off of newp instead.
416   */
417
418  if (jmp_addr & 0x40000000) {
419    jmp_addr &= 0xfffffffc;
420     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
421  }
422#elif defined(sparc)
423
424  /*
425   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
426   *  diagram of the stack.
427   */
428
429  asm ("ta  0x03");            /* flush registers */
430
431  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
432  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
433  *(addr + FP_OFF) = (unsigned32)(_stack_high);
434
435#elif defined(i386)
436 
437    /*
438     *  This information was gathered by disassembling setjmp().
439     */
440
441    {
442      unsigned32 stack_ptr;
443
444      stack_ptr = _stack_high - CPU_FRAME_SIZE;
445
446      *(addr + EBX_OFF) = 0xFEEDFEED;
447      *(addr + ESI_OFF) = 0xDEADDEAD;
448      *(addr + EDI_OFF) = 0xDEAFDEAF;
449      *(addr + EBP_OFF) = stack_ptr;
450      *(addr + ESP_OFF) = stack_ptr;
451      *(addr + RET_OFF) = jmp_addr;
452 
453      addr = (unsigned32 *) stack_ptr;
454 
455      addr[ 0 ] = jmp_addr;
456      addr[ 1 ] = (unsigned32) stack_ptr;
457      addr[ 2 ] = (unsigned32) stack_ptr;
458    }
459
460#else
461#error "UNKNOWN CPU!!!"
462#endif
463
464}
465
466/*PAGE
467 *
468 *  _CPU_Context_restore
469 */
470
471void _CPU_Context_restore(
472  Context_Control  *next
473)
474{
475  Context_Control_overlay *nextp = (Context_Control_overlay *)next;
476
477  sigprocmask( SIG_SETMASK, &nextp->isr_level, 0 );
478  longjmp( nextp->regs, 0 );
479}
480
481/*PAGE
482 *
483 *  _CPU_Context_switch
484 */
485
486void _CPU_Context_switch(
487  Context_Control  *current,
488  Context_Control  *next
489)
490{
491  Context_Control_overlay *currentp = (Context_Control_overlay *)current;
492  Context_Control_overlay *nextp = (Context_Control_overlay *)next;
493
494  int status;
495
496  /*
497   *  Switch levels in one operation
498   */
499
500  status = sigprocmask( SIG_SETMASK, &nextp->isr_level, &currentp->isr_level );
501  if ( status )
502    _Internal_error_Occurred(
503      INTERNAL_ERROR_CORE,
504      TRUE,
505      status
506    );
507
508  if (setjmp(currentp->regs) == 0) {    /* Save the current context */
509     longjmp(nextp->regs, 0);           /* Switch to the new context */
510     if ( status )
511       _Internal_error_Occurred(
512         INTERNAL_ERROR_CORE,
513         TRUE,
514         status
515       );
516  }
517
518}
519 
520/*PAGE
521 *
522 *  _CPU_Save_float_context
523 */
524
525void _CPU_Save_float_context(
526  Context_Control_fp *fp_context
527)
528{
529}
530
531/*PAGE
532 *
533 *  _CPU_Restore_float_context
534 */
535
536void _CPU_Restore_float_context(
537  Context_Control_fp *fp_context
538)
539{
540}
541
542/*PAGE
543 *
544 *  _CPU_ISR_Disable_support
545 */
546
547unsigned32 _CPU_ISR_Disable_support(void)
548{
549  int status;
550  sigset_t  old_mask;
551
552  status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
553  if ( status )
554    _Internal_error_Occurred(
555      INTERNAL_ERROR_CORE,
556      TRUE,
557      status
558    );
559
560  if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)))
561    return 1;
562
563  return 0;
564}
565
566/*PAGE
567 *
568 *  _CPU_ISR_Enable
569 */
570
571void _CPU_ISR_Enable(
572  unsigned32 level
573)
574{
575  int status;
576
577  if (level == 0)
578    status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
579  else
580    status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
581
582  if ( status )
583    _Internal_error_Occurred(
584      INTERNAL_ERROR_CORE,
585      TRUE,
586      status
587    );
588}
589
590/*PAGE
591 *
592 *  _CPU_ISR_Handler
593 *
594 *  External interrupt handler.
595 *  This is installed as a UNIX signal handler.
596 *  It vectors out to specific user interrupt handlers.
597 */
598
599void _CPU_ISR_Handler(int vector)
600{
601  extern void        _Thread_Dispatch(void);
602  extern unsigned32  _Thread_Dispatch_disable_level;
603  extern boolean     _Context_Switch_necessary;
604
605  if (_ISR_Nest_level++ == 0) {
606      /* switch to interrupt stack */
607  }
608
609  _Thread_Dispatch_disable_level++;
610
611  if (_ISR_Vector_table[vector]) {
612     _ISR_Vector_table[vector](vector);
613  } else {
614     _CPU_Stray_signal(vector);
615  }
616
617  if (_ISR_Nest_level-- == 0) {
618      /* switch back to original stack */
619  }
620
621  _Thread_Dispatch_disable_level--;
622
623  if (_Thread_Dispatch_disable_level == 0 &&
624      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
625      _CPU_ISR_Enable(0);
626      _Thread_Dispatch();
627  }
628}
629
630/*PAGE
631 *
632 *  _CPU_Stray_signal
633 */
634
635void _CPU_Stray_signal(int sig_num)
636{
637  char buffer[ 4 ];
638 
639  /*
640   * print "stray" msg about ones which that might mean something
641   * Avoid using the stdio section of the library.
642   * The following is generally safe.
643   */
644 
645  switch (sig_num)
646  {
647      case SIGCLD:
648          break;
649 
650      default:
651      {
652          /*
653           *  We avoid using the stdio section of the library.
654           *  The following is generally safe.
655           */
656 
657          buffer[ 0 ] = (sig_num >> 4) + 0x30;
658          buffer[ 1 ] = (sig_num & 0xf) + 0x30;
659          buffer[ 2 ] = '\n';
660 
661          write( 2, "Stray signal 0x", 12 );
662          write( 2, buffer, 3 );
663      }
664  }
665 
666  /*
667   * If it was a "fatal" signal, then exit here
668   * If app code has installed a hander for one of these, then
669   * we won't call _CPU_Stray_signal, so this is ok.
670   */
671 
672  switch (sig_num) {
673      case SIGINT:
674      case SIGHUP:
675      case SIGQUIT:
676      case SIGILL:
677#ifdef SIGEMT
678      case SIGEMT:
679#endif
680      case SIGKILL:
681      case SIGBUS:
682      case SIGSEGV:
683      case SIGTERM:
684          _CPU_Fatal_error(0x100 + sig_num);
685  }
686}
687
688/*PAGE
689 *
690 *  _CPU_Fatal_error
691 */
692
693void _CPU_Fatal_error(unsigned32 error)
694{
695  setitimer(ITIMER_REAL, 0, 0);
696
697  if ( error ) {
698#ifdef RTEMS_DEBUG
699    abort();
700#endif
701    if (getenv("RTEMS_DEBUG"))
702      abort();
703  }
704
705  _exit(error);
706}
707
708/*
709 *  Special Purpose Routines to hide the use of UNIX system calls.
710 */
711
712int _CPU_Get_clock_vector( void )
713{
714  return SIGALRM;
715}
716
717void _CPU_Start_clock( 
718  int microseconds
719)
720{
721  struct itimerval  new;
722
723  new.it_value.tv_sec = 0;
724  new.it_value.tv_usec = microseconds;
725  new.it_interval.tv_sec = 0;
726  new.it_interval.tv_usec = microseconds;
727
728  setitimer(ITIMER_REAL, &new, 0);
729}
730
731void _CPU_Stop_clock( void )
732{
733  struct itimerval  new;
734  struct sigaction  act;
735 
736  /*
737   * Set the SIGALRM signal to ignore any last
738   * signals that might come in while we are
739   * disarming the timer and removing the interrupt
740   * vector.
741   */
742 
743  act.sa_handler = SIG_IGN;
744
745  sigaction(SIGALRM, &act, 0);
746 
747  new.it_value.tv_sec = 0;
748  new.it_value.tv_usec = 0;
749 
750  setitimer(ITIMER_REAL, &new, 0);
751}
752
753int  _CPU_SHM_Semid;
754extern       void fix_syscall_errno( void );
755
756void _CPU_SHM_Init( 
757  unsigned32   maximum_nodes,
758  boolean      is_master_node,
759  void       **shm_address,
760  unsigned32  *shm_length
761)
762{
763  int          i;
764  int          shmid;
765  char        *shm_addr;
766  key_t        shm_key;
767  key_t        sem_key;
768  int          status;
769  int          shm_size;
770 
771  if (getenv("RTEMS_SHM_KEY"))
772    shm_key = strtol(getenv("RTEMS_SHM_KEY"), 0, 0);
773  else
774#ifdef RTEMS_SHM_KEY
775    shm_key = RTEMS_SHM_KEY;
776#else
777    shm_key = 0xa000;
778#endif
779 
780    if (getenv("RTEMS_SHM_SIZE"))
781      shm_size = strtol(getenv("RTEMS_SHM_SIZE"), 0, 0);
782    else
783#ifdef RTEMS_SHM_SIZE
784      shm_size = RTEMS_SHM_SIZE;
785#else
786      shm_size = 64 * 1024;
787#endif
788 
789    if (getenv("RTEMS_SHM_SEMAPHORE_KEY"))
790      sem_key = strtol(getenv("RTEMS_SHM_SEMAPHORE_KEY"), 0, 0);
791    else
792#ifdef RTEMS_SHM_SEMAPHORE_KEY
793      sem_key = RTEMS_SHM_SEMAPHORE_KEY;
794#else
795      sem_key = 0xa001;
796#endif
797 
798    shmid = shmget(shm_key, shm_size, IPC_CREAT | 0660);
799    if ( shmid == -1 ) {
800      fix_syscall_errno(); /* in case of newlib */
801      perror( "shmget" );
802      _CPU_Fatal_halt( 0xdead0001 );
803    }
804 
805    shm_addr = shmat(shmid, (char *)0, SHM_RND);
806    if ( shm_addr == (void *)-1 ) {
807      fix_syscall_errno(); /* in case of newlib */
808      perror( "shmat" );
809      _CPU_Fatal_halt( 0xdead0002 );
810    }
811 
812    _CPU_SHM_Semid = semget(sem_key, maximum_nodes + 1, IPC_CREAT | 0660);
813    if ( _CPU_SHM_Semid == -1 ) {
814      fix_syscall_errno(); /* in case of newlib */
815      perror( "semget" );
816      _CPU_Fatal_halt( 0xdead0003 );
817    }
818 
819    if ( is_master_node ) {
820      for ( i=0 ; i <= maximum_nodes ; i++ ) {
821#if defined(solaris2)
822        union semun {
823          int val;
824          struct semid_ds *buf;
825          ushort *array;
826        } help;
827 
828        help.val = 1;
829        status = semctl( _CPU_SHM_Semid, i, SETVAL, help );
830#endif
831#if defined(hpux)
832        status = semctl( _CPU_SHM_Semid, i, SETVAL, 1 );
833#endif
834 
835        fix_syscall_errno(); /* in case of newlib */
836        if ( status == -1 ) {
837          _CPU_Fatal_halt( 0xdead0004 );
838        }
839      }
840    }
841 
842  *shm_address = shm_addr;
843  *shm_length = shm_size;
844
845}
846
847int _CPU_Get_pid( void )
848{
849  return getpid();
850}
851
852/*
853 * Define this to use signals for MPCI shared memory driver.
854 * If undefined, the shared memory driver will poll from the
855 * clock interrupt.
856 * Ref: ../shmsupp/getcfg.c
857 *
858 * BEWARE:: many UN*X kernels and debuggers become severely confused when
859 *          debugging programs which use signals.  The problem is *much*
860 *          worse when using multiple signals, since ptrace(2) tends to
861 *          drop all signals except 1 in the case of multiples.
862 *          On hpux9, this problem was so bad, we couldn't use interrupts
863 *          with the shared memory driver if we ever hoped to debug
864 *          RTEMS programs.
865 *          Maybe systems that use /proc don't have this problem...
866 */
867 
868 
869int _CPU_SHM_Get_vector( void )
870{
871#ifdef CPU_USE_SHM_INTERRUPTS
872  return SIGUSR1;
873#else
874  return 0;
875#endif
876}
877
878void _CPU_SHM_Send_interrupt(
879  int pid,
880  int vector
881)
882{
883  kill((pid_t) pid, vector);
884}
885
886void _CPU_SHM_Lock( 
887  int semaphore
888)
889{
890  struct sembuf      sb;
891  int                status;
892 
893  sb.sem_num = semaphore;
894  sb.sem_op  = -1;
895  sb.sem_flg = 0;
896 
897  while (1) {
898    status = semop(_CPU_SHM_Semid, &sb, 1);
899    if ( status >= 0 )
900      break;
901    if ( status == -1 ) {
902       fix_syscall_errno();    /* in case of newlib */
903        if (errno == EINTR)
904            continue;
905        perror("shm lock");
906        _CPU_Fatal_halt( 0xdead0005 );
907    }
908  }
909
910}
911
912void _CPU_SHM_Unlock(
913  int semaphore
914)
915{
916  struct sembuf  sb;
917  int            status;
918 
919  sb.sem_num = semaphore;
920  sb.sem_op  = 1;
921  sb.sem_flg = 0;
922 
923  while (1) {
924    status = semop(_CPU_SHM_Semid, &sb, 1);
925    if ( status >= 0 )
926      break;
927 
928    if ( status == -1 ) {
929      fix_syscall_errno();    /* in case of newlib */
930      if (errno == EINTR)
931          continue;
932      perror("shm unlock");
933      _CPU_Fatal_halt( 0xdead0006 );
934    }
935  }
936
937}
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