source: rtems/cpukit/score/cpu/unix/cpu.c @ 637df35

4.104.114.84.95
Last change on this file since 637df35 was 637df35, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 12, 1995 at 7:47:25 PM

Ada95, gnat, go32

  • Property mode set to 100644
File size: 12.6 KB
Line 
1/*
2 *  HP PA-RISC CPU Dependent Source
3 *
4 *
5 *  To anyone who acknowledges that this file is provided "AS IS"
6 *  without any express or implied warranty:
7 *      permission to use, copy, modify, and distribute this file
8 *      for any purpose is hereby granted without fee, provided that
9 *      the above copyright notice and this notice appears in all
10 *      copies, and that the name of Division Incorporated not be
11 *      used in advertising or publicity pertaining to distribution
12 *      of the software without specific, written prior permission.
13 *      Division Incorporated makes no representations about the
14 *      suitability of this software for any purpose.
15 *
16 *  $Id$
17 */
18
19#include <rtems/system.h>
20#include <rtems/isr.h>
21
22#include <stdio.h>
23#include <stdlib.h>
24#include <unistd.h>
25#include <signal.h>
26#include <time.h>
27
28#ifndef SA_RESTART
29#define SA_RESTART 0
30#endif
31
32void  _CPU_Signal_initialize(void);
33void  _CPU_Stray_signal(int);
34void  _CPU_ISR_Handler(int);
35
36sigset_t         _CPU_Signal_mask;
37Context_Control  _CPU_Context_Default_with_ISRs_enabled;
38Context_Control  _CPU_Context_Default_with_ISRs_disabled;
39
40/*
41 * Which cpu are we? Used by libcpu and libbsp.
42 */
43
44int cpu_number;
45
46/*PAGE
47 *
48 *  _CPU_ISR_From_CPU_Init
49 */
50
51void _CPU_ISR_From_CPU_Init()
52{
53  unsigned32        i;
54  proc_ptr          old_handler;
55
56
57  /*
58   * Block all the signals except SIGTRAP for the debugger
59   * and SIGABRT for fatal errors.
60   */
61
62  _CPU_ISR_Enable(1);
63
64  (void) sigfillset(&_CPU_Signal_mask);
65  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
66  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
67  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
68  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
69
70  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
71
72  /*
73   * Set the handler for all signals to be signal_handler
74   * which will then vector out to the correct handler
75   * for whichever signal actually happened. Initially
76   * set the vectors to the stray signal handler.
77   */
78
79  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
80      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
81
82  _CPU_Signal_initialize();
83}
84
85void _CPU_Signal_initialize( void )
86{
87  struct sigaction  act;
88  sigset_t          mask;
89
90  /* mark them all active except for TraceTrap  and Abort */
91
92  sigfillset(&mask);
93  sigdelset(&mask, SIGTRAP);
94  sigdelset(&mask, SIGABRT);
95  sigdelset(&mask, SIGIOT);
96  sigdelset(&mask, SIGCONT);
97  sigprocmask(SIG_UNBLOCK, &mask, 0);
98
99  act.sa_handler = _CPU_ISR_Handler;
100  act.sa_mask = mask;
101  act.sa_flags = SA_RESTART;
102
103  sigaction(SIGHUP, &act, 0);
104  sigaction(SIGINT, &act, 0);
105  sigaction(SIGQUIT, &act, 0);
106  sigaction(SIGILL, &act, 0);
107  sigaction(SIGEMT, &act, 0);
108  sigaction(SIGFPE, &act, 0);
109  sigaction(SIGKILL, &act, 0);
110  sigaction(SIGBUS, &act, 0);
111  sigaction(SIGSEGV, &act, 0);
112  sigaction(SIGSYS, &act, 0);
113  sigaction(SIGPIPE, &act, 0);
114  sigaction(SIGALRM, &act, 0);
115  sigaction(SIGTERM, &act, 0);
116  sigaction(SIGUSR1, &act, 0);
117  sigaction(SIGUSR2, &act, 0);
118  sigaction(SIGCHLD, &act, 0);
119  sigaction(SIGCLD, &act, 0);
120  sigaction(SIGPWR, &act, 0);
121  sigaction(SIGVTALRM, &act, 0);
122  sigaction(SIGPROF, &act, 0);
123  sigaction(SIGIO, &act, 0);
124  sigaction(SIGWINCH, &act, 0);
125  sigaction(SIGSTOP, &act, 0);
126  sigaction(SIGTTIN, &act, 0);
127  sigaction(SIGTTOU, &act, 0);
128  sigaction(SIGURG, &act, 0);
129/*
130 *  XXX: Really should be on HPUX.
131 */
132
133#if defined(hppa1_1)
134    sigaction(SIGLOST, &act, 0);
135#endif
136
137}
138
139/*PAGE
140 *
141 *  _CPU_Context_From_CPU_Init
142 */
143
144void _CPU_Context_From_CPU_Init()
145{
146
147#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
148    /*
149     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
150     * will handle the full 32 floating point registers.
151     *
152     *  NOTE:  Is this a bug in HPUX9?
153     */
154
155    {
156      extern unsigned32 _SYSTEM_ID;
157
158      _SYSTEM_ID = 0x20c;
159    }
160#endif
161
162  /*
163   *  get default values to use in _CPU_Context_Initialize()
164   */
165
166  _CPU_ISR_Set_level( 0 );
167  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
168  sigprocmask(
169    SIG_SETMASK,    /* ignored when second arg is NULL */
170    0,
171    &_CPU_Context_Default_with_ISRs_enabled.isr_level
172  );
173
174  _CPU_ISR_Set_level( 1 );
175  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
176  sigprocmask(
177    SIG_SETMASK,    /* ignored when second arg is NULL */
178    0,
179    &_CPU_Context_Default_with_ISRs_disabled.isr_level
180  );
181
182}
183
184/*  _CPU_Initialize
185 *
186 *  This routine performs processor dependent initialization.
187 *
188 *  INPUT PARAMETERS:
189 *    cpu_table       - CPU table to initialize
190 *    thread_dispatch - address of disptaching routine
191 */
192
193
194void _CPU_Initialize(
195  rtems_cpu_table  *cpu_table,
196  void      (*thread_dispatch)      /* ignored on this CPU */
197)
198{
199  if ( cpu_table == NULL )
200    _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED );
201
202  /*
203   *  The thread_dispatch argument is the address of the entry point
204   *  for the routine called at the end of an ISR once it has been
205   *  decided a context switch is necessary.  On some compilation
206   *  systems it is difficult to call a high-level language routine
207   *  from assembly.  This allows us to trick these systems.
208   *
209   *  If you encounter this problem save the entry point in a CPU
210   *  dependent variable.
211   */
212
213  _CPU_Thread_dispatch_pointer = thread_dispatch;
214
215  /*
216   * XXX; If there is not an easy way to initialize the FP context
217   *      during Context_Initialize, then it is usually easier to
218   *      save an "uninitialized" FP context here and copy it to
219   *      the task's during Context_Initialize.
220   */
221
222  /* XXX: FP context initialization support */
223
224  _CPU_Table = *cpu_table;
225
226  _CPU_ISR_From_CPU_Init();
227
228  _CPU_Context_From_CPU_Init();
229
230}
231
232/*PAGE
233 *
234 *  _CPU_ISR_install_raw_handler
235 */
236
237void _CPU_ISR_install_raw_handler(
238  unsigned32  vector,
239  proc_ptr    new_handler,
240  proc_ptr   *old_handler
241)
242{
243  _CPU_Fatal_halt( 0xdeaddead );
244}
245
246/*PAGE
247 *
248 *  _CPU_ISR_install_vector
249 *
250 *  This kernel routine installs the RTEMS handler for the
251 *  specified vector.
252 *
253 *  Input parameters:
254 *    vector      - interrupt vector number
255 *    old_handler - former ISR for this vector number
256 *    new_handler - replacement ISR for this vector number
257 *
258 *  Output parameters:  NONE
259 *
260 */
261
262
263void _CPU_ISR_install_vector(
264  unsigned32  vector,
265  proc_ptr    new_handler,
266  proc_ptr   *old_handler
267)
268{
269   *old_handler = _ISR_Vector_table[ vector ];
270
271   /*
272    *  If the interrupt vector table is a table of pointer to isr entry
273    *  points, then we need to install the appropriate RTEMS interrupt
274    *  handler for this vector number.
275    */
276
277   /*
278    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
279    *  be used by the _CPU_ISR_Handler so the user gets control.
280    */
281
282    _ISR_Vector_table[ vector ] = new_handler;
283}
284
285/*PAGE
286 *
287 *  _CPU_Install_interrupt_stack
288 */
289
290void _CPU_Install_interrupt_stack( void )
291{
292}
293
294/*PAGE
295 *
296 *  _CPU_Internal_threads_Idle_thread_body
297 *
298 *  NOTES:
299 *
300 *  1. This is the same as the regular CPU independent algorithm.
301 *
302 *  2. If you implement this using a "halt", "idle", or "shutdown"
303 *     instruction, then don't forget to put it in an infinite loop.
304 *
305 *  3. Be warned. Some processors with onboard DMA have been known
306 *     to stop the DMA if the CPU were put in IDLE mode.  This might
307 *     also be a problem with other on-chip peripherals.  So use this
308 *     hook with caution.
309 */
310
311void _CPU_Internal_threads_Idle_thread_body( void )
312{
313  while (1)
314    pause();
315}
316
317/*PAGE
318 *
319 *  _CPU_Context_Initialize
320 */
321
322void _CPU_Context_Initialize(
323  Context_Control  *_the_context,
324  unsigned32       *_stack_base,
325  unsigned32        _size,
326  unsigned32        _new_level,
327  void             *_entry_point
328)
329{
330  void        *source;
331  unsigned32  *addr;
332  unsigned32   jmp_addr;
333  unsigned32   _stack_low;   /* lowest "stack aligned" address */
334  unsigned32   _stack_high;  /* highest "stack aligned" address */
335  unsigned32   _the_size;
336
337  jmp_addr = (unsigned32) _entry_point;
338
339  /*
340   *  On CPUs with stacks which grow down, we build the stack
341   *  based on the _stack_high address.  On CPUs with stacks which
342   *  grow up, we build the stack based on the _stack_low address. 
343   */
344
345  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
346  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
347
348  _stack_high = ((unsigned32)(_stack_base) + _size);
349  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
350
351  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
352
353  /*
354   * Slam our jmp_buf template into the context we are creating
355   */
356
357  if ( _new_level == 0 )
358    source = _CPU_Context_Default_with_ISRs_enabled.regs;
359  else
360    source = _CPU_Context_Default_with_ISRs_disabled.regs;
361     
362  memcpy(_the_context, source, sizeof(jmp_buf));
363
364  addr = (unsigned32 *)_the_context;
365
366#if defined(hppa1_1)
367  *(addr + RP_OFF) = jmp_addr;
368  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
369
370  /*
371   * See if we are using shared libraries by checking
372   * bit 30 in 24 off of newp. If bit 30 is set then
373   * we are using shared libraries and the jump address
374   * is at what 24 off of newp points to so shove that
375   * into 24 off of newp instead.
376   */
377
378  if (jmp_addr & 0x40000000) {
379    jmp_addr &= 0xfffffffc;
380     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
381  }
382#elif defined(sparc)
383
384  /*
385   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
386   *  diagram of the stack.
387   */
388
389  asm ("ta  0x03");            /* flush registers */
390
391  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
392  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
393  *(addr + FP_OFF) = (unsigned32)(_stack_high);
394#else
395#error "UNKNOWN CPU!!!"
396#endif
397
398}
399
400/*PAGE
401 *
402 *  _CPU_Context_restore
403 */
404
405void _CPU_Context_restore(
406  Context_Control  *next
407)
408{
409  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
410  longjmp( next->regs, 0 );
411}
412
413/*PAGE
414 *
415 *  _CPU_Context_switch
416 */
417
418void _CPU_Context_switch(
419  Context_Control  *current,
420  Context_Control  *next
421)
422{
423  /*
424   *  Switch levels in one operation
425   */
426
427  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
428
429  if (setjmp(current->regs) == 0) {    /* Save the current context */
430     longjmp(next->regs, 0);           /* Switch to the new context */
431  }
432}
433 
434/*PAGE
435 *
436 *  _CPU_Save_float_context
437 */
438
439void _CPU_Save_float_context(
440  Context_Control_fp *fp_context
441)
442{
443}
444
445/*PAGE
446 *
447 *  _CPU_Restore_float_context
448 */
449
450void _CPU_Restore_float_context(
451  Context_Control_fp *fp_context
452)
453{
454}
455
456/*PAGE
457 *
458 *  _CPU_ISR_Disable_support
459 */
460
461unsigned32 _CPU_ISR_Disable_support(void)
462{
463  sigset_t  old_mask;
464  sigset_t  empty_mask;
465
466  sigemptyset(&empty_mask);
467  sigemptyset(&old_mask);
468  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
469
470  if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
471    return 1;
472
473  return 0;
474}
475
476/*PAGE
477 *
478 *  _CPU_ISR_Enable
479 */
480
481void _CPU_ISR_Enable(
482  unsigned32 level
483)
484{
485  if (level == 0)
486    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
487  else
488    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
489}
490
491/*PAGE
492 *
493 *  _CPU_ISR_Handler
494 *
495 *  External interrupt handler.
496 *  This is installed as a UNIX signal handler.
497 *  It vectors out to specific user interrupt handlers.
498 */
499
500void _CPU_ISR_Handler(int vector)
501{
502  extern void        _Thread_Dispatch(void);
503  extern unsigned32  _Thread_Dispatch_disable_level;
504  extern boolean     _Context_Switch_necessary;
505
506
507  if (_ISR_Nest_level++ == 0) {
508      /* switch to interrupt stack */
509  }
510
511  _Thread_Dispatch_disable_level++;
512
513  if (_ISR_Vector_table[vector]) {
514     _ISR_Vector_table[vector](vector);
515  } else {
516     _CPU_Stray_signal(vector);
517  }
518
519  if (_ISR_Nest_level-- == 0) {
520      /* switch back to original stack */
521  }
522
523  _Thread_Dispatch_disable_level--;
524
525  if (_Thread_Dispatch_disable_level == 0 &&
526      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
527      _CPU_ISR_Enable(0);
528      _Thread_Dispatch();
529  }
530}
531
532/*PAGE
533 *
534 *  _CPU_Stray_signal
535 */
536
537void _CPU_Stray_signal(int sig_num)
538{
539  char buffer[ 80 ];   
540
541  /*
542   *  We avoid using the stdio section of the library.
543   *  The following is generally safe.
544   */
545
546  write( 
547    2,
548    buffer, 
549    sprintf( buffer, "Stray signal %d\n", sig_num )
550  );
551 
552  /*
553   * If it was a "fatal" signal, then exit here
554   * If app code has installed a hander for one of these, then
555   * we won't call _CPU_Stray_signal, so this is ok.
556   */
557 
558  switch (sig_num) {
559      case SIGINT:
560      case SIGHUP:
561      case SIGQUIT:
562      case SIGILL:
563      case SIGEMT:
564      case SIGKILL:
565      case SIGBUS:
566      case SIGSEGV:
567      case SIGTERM:
568          _CPU_Fatal_error(0x100 + sig_num);
569  }
570}
571
572/*PAGE
573 *
574 *  _CPU_Fatal_error
575 */
576
577void _CPU_Fatal_error(unsigned32 error)
578{
579  setitimer(ITIMER_REAL, 0, 0);
580
581  _exit(error);
582}
583
584/*PAGE
585 *
586 *  _CPU_ffs
587 */
588
589int _CPU_ffs(unsigned32 value)
590{
591  int output;
592  extern int ffs( int );
593
594  output = ffs(value);
595  output = output - 1;
596
597  return output;
598}
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