source: rtems/cpukit/score/cpu/unix/cpu.c @ 3a4ae6c

4.104.114.84.95
Last change on this file since 3a4ae6c was 3a4ae6c, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 11, 1995 at 7:35:39 PM

The word "RTEMS" almost completely removed from the core.

Configuration Table Template file added and all tests
modified to use this. All gvar.h and conftbl.h files
removed from test directories.

Configuration parameter maximum_devices added.

Core semaphore and mutex handlers added and RTEMS API Semaphore
Manager updated to reflect this.

Initialization sequence changed to invoke API specific initialization
routines. Initialization tasks table now owned by RTEMS Tasks Manager.

Added user extension for post-switch.

Utilized user extensions to implement API specific functionality
like signal dispatching.

Added extensions to the System Initialization Thread so that an
API can register a function to be invoked while the system
is being initialized. These are largely equivalent to the
pre-driver and post-driver hooks.

Added the Modules file oar-go32_p5, modified oar-go32, and modified
the file make/custom/go32.cfg to look at an environment varable which
determines what CPU model is being used.

All BSPs updated to reflect named devices and clock driver's IOCTL
used by the Shared Memory Driver. Also merged clock isr into
main file and removed ckisr.c where possible.

Updated spsize to reflect new and moved variables.

Makefiles for the executive source and include files updated to show
break down of files into Core, RTEMS API, and Neither.

Header and inline files installed into subdirectory based on whether
logically in the Core or a part of the RTEMS API.

  • Property mode set to 100644
File size: 13.6 KB
Line 
1/*
2 *  HP PA-RISC CPU Dependent Source
3 *
4 *
5 *  To anyone who acknowledges that this file is provided "AS IS"
6 *  without any express or implied warranty:
7 *      permission to use, copy, modify, and distribute this file
8 *      for any purpose is hereby granted without fee, provided that
9 *      the above copyright notice and this notice appears in all
10 *      copies, and that the name of Division Incorporated not be
11 *      used in advertising or publicity pertaining to distribution
12 *      of the software without specific, written prior permission.
13 *      Division Incorporated makes no representations about the
14 *      suitability of this software for any purpose.
15 *
16 *  $Id$
17 */
18
19#include <rtems/system.h>
20#include <rtems/core/isr.h>
21
22#include <stdio.h>
23#include <stdlib.h>
24#include <signal.h>
25#include <time.h>
26#include <sys/time.h>
27
28#ifndef SA_RESTART
29#define SA_RESTART 0
30#endif
31
32void  _CPU_Signal_initialize(void);
33void  _CPU_Stray_signal(int);
34void  _CPU_ISR_Handler(int);
35
36sigset_t         _CPU_Signal_mask;
37Context_Control  _CPU_Context_Default_with_ISRs_enabled;
38Context_Control  _CPU_Context_Default_with_ISRs_disabled;
39
40/*
41 * Which cpu are we? Used by libcpu and libbsp.
42 */
43
44int cpu_number;
45
46/*PAGE
47 *
48 *  _CPU_ISR_From_CPU_Init
49 */
50
51sigset_t  posix_empty_mask;
52
53void _CPU_ISR_From_CPU_Init()
54{
55  unsigned32        i;
56  proc_ptr          old_handler;
57
58  /*
59   * Generate an empty mask to be used by disable_support
60   */
61
62  sigemptyset(&posix_empty_mask);
63 
64  /*
65   * Block all the signals except SIGTRAP for the debugger
66   * and SIGABRT for fatal errors.
67   */
68
69  (void) sigfillset(&_CPU_Signal_mask);
70  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
71  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
72  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
73  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
74
75  _CPU_ISR_Enable(1);
76
77  /*
78   * Set the handler for all signals to be signal_handler
79   * which will then vector out to the correct handler
80   * for whichever signal actually happened. Initially
81   * set the vectors to the stray signal handler.
82   */
83
84  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
85      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
86
87  _CPU_Signal_initialize();
88}
89
90void _CPU_Signal_initialize( void )
91{
92  struct sigaction  act;
93  sigset_t          mask;
94
95  /* mark them all active except for TraceTrap  and Abort */
96
97  sigfillset(&mask);
98  sigdelset(&mask, SIGTRAP);
99  sigdelset(&mask, SIGABRT);
100  sigdelset(&mask, SIGIOT);
101  sigdelset(&mask, SIGCONT);
102  sigprocmask(SIG_UNBLOCK, &mask, 0);
103
104  act.sa_handler = _CPU_ISR_Handler;
105  act.sa_mask = mask;
106  act.sa_flags = SA_RESTART;
107
108  sigaction(SIGHUP, &act, 0);
109  sigaction(SIGINT, &act, 0);
110  sigaction(SIGQUIT, &act, 0);
111  sigaction(SIGILL, &act, 0);
112#ifdef SIGEMT
113  sigaction(SIGEMT, &act, 0);
114#endif
115  sigaction(SIGFPE, &act, 0);
116  sigaction(SIGKILL, &act, 0);
117  sigaction(SIGBUS, &act, 0);
118  sigaction(SIGSEGV, &act, 0);
119#ifdef SIGSYS
120  sigaction(SIGSYS, &act, 0);
121#endif
122  sigaction(SIGPIPE, &act, 0);
123  sigaction(SIGALRM, &act, 0);
124  sigaction(SIGTERM, &act, 0);
125  sigaction(SIGUSR1, &act, 0);
126  sigaction(SIGUSR2, &act, 0);
127  sigaction(SIGCHLD, &act, 0);
128  sigaction(SIGCLD, &act, 0);
129  sigaction(SIGPWR, &act, 0);
130  sigaction(SIGVTALRM, &act, 0);
131  sigaction(SIGPROF, &act, 0);
132  sigaction(SIGIO, &act, 0);
133  sigaction(SIGWINCH, &act, 0);
134  sigaction(SIGSTOP, &act, 0);
135  sigaction(SIGTTIN, &act, 0);
136  sigaction(SIGTTOU, &act, 0);
137  sigaction(SIGURG, &act, 0);
138#ifdef SIGLOST
139    sigaction(SIGLOST, &act, 0);
140#endif
141
142}
143
144/*PAGE
145 *
146 *  _CPU_Context_From_CPU_Init
147 */
148
149void _CPU_Context_From_CPU_Init()
150{
151
152#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
153    /*
154     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
155     * will handle the full 32 floating point registers.
156     *
157     *  NOTE:  Is this a bug in HPUX9?
158     */
159
160    {
161      extern unsigned32 _SYSTEM_ID;
162
163      _SYSTEM_ID = 0x20c;
164    }
165#endif
166
167  /*
168   *  get default values to use in _CPU_Context_Initialize()
169   */
170
171  _CPU_ISR_Set_level( 0 );
172  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
173  sigprocmask(
174    SIG_SETMASK,    /* ignored when second arg is NULL */
175    0,
176    &_CPU_Context_Default_with_ISRs_enabled.isr_level
177  );
178
179  _CPU_ISR_Set_level( 1 );
180  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
181  sigprocmask(
182    SIG_SETMASK,    /* ignored when second arg is NULL */
183    0,
184    &_CPU_Context_Default_with_ISRs_disabled.isr_level
185  );
186
187}
188
189/*PAGE
190 *
191 *  _CPU_ISR_Get_level
192 */
193
194unsigned32 _CPU_ISR_Get_level( void )
195{
196  sigset_t sigset;
197 
198  sigprocmask( 0, 0, &sigset ); 
199
200  /*
201   *  This is an educated guess based on ONLY ONE of the signals we
202   *  disable/enable to mask ISRs.
203   */
204
205  if ( sigismember( &sigset, SIGUSR1 ) )
206    return 1;
207  else
208    return 0;
209}
210
211/*  _CPU_Initialize
212 *
213 *  This routine performs processor dependent initialization.
214 *
215 *  INPUT PARAMETERS:
216 *    cpu_table       - CPU table to initialize
217 *    thread_dispatch - address of disptaching routine
218 */
219
220
221void _CPU_Initialize(
222  rtems_cpu_table  *cpu_table,
223  void            (*thread_dispatch)      /* ignored on this CPU */
224)
225{
226  /*
227   *  The thread_dispatch argument is the address of the entry point
228   *  for the routine called at the end of an ISR once it has been
229   *  decided a context switch is necessary.  On some compilation
230   *  systems it is difficult to call a high-level language routine
231   *  from assembly.  This allows us to trick these systems.
232   *
233   *  If you encounter this problem save the entry point in a CPU
234   *  dependent variable.
235   */
236
237  _CPU_Thread_dispatch_pointer = thread_dispatch;
238
239  /*
240   * XXX; If there is not an easy way to initialize the FP context
241   *      during Context_Initialize, then it is usually easier to
242   *      save an "uninitialized" FP context here and copy it to
243   *      the task's during Context_Initialize.
244   */
245
246  /* XXX: FP context initialization support */
247
248  _CPU_Table = *cpu_table;
249
250  _CPU_ISR_From_CPU_Init();
251
252  _CPU_Context_From_CPU_Init();
253
254}
255
256/*PAGE
257 *
258 *  _CPU_ISR_install_raw_handler
259 */
260
261void _CPU_ISR_install_raw_handler(
262  unsigned32  vector,
263  proc_ptr    new_handler,
264  proc_ptr   *old_handler
265)
266{
267  _CPU_Fatal_halt( 0xdeaddead );
268}
269
270/*PAGE
271 *
272 *  _CPU_ISR_install_vector
273 *
274 *  This kernel routine installs the RTEMS handler for the
275 *  specified vector.
276 *
277 *  Input parameters:
278 *    vector      - interrupt vector number
279 *    old_handler - former ISR for this vector number
280 *    new_handler - replacement ISR for this vector number
281 *
282 *  Output parameters:  NONE
283 *
284 */
285
286
287void _CPU_ISR_install_vector(
288  unsigned32  vector,
289  proc_ptr    new_handler,
290  proc_ptr   *old_handler
291)
292{
293   *old_handler = _ISR_Vector_table[ vector ];
294
295   /*
296    *  If the interrupt vector table is a table of pointer to isr entry
297    *  points, then we need to install the appropriate RTEMS interrupt
298    *  handler for this vector number.
299    */
300
301   /*
302    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
303    *  be used by the _CPU_ISR_Handler so the user gets control.
304    */
305
306    _ISR_Vector_table[ vector ] = new_handler;
307}
308
309/*PAGE
310 *
311 *  _CPU_Install_interrupt_stack
312 */
313
314void _CPU_Install_interrupt_stack( void )
315{
316}
317
318/*PAGE
319 *
320 *  _CPU_Internal_threads_Idle_thread_body
321 *
322 *  NOTES:
323 *
324 *  1. This is the same as the regular CPU independent algorithm.
325 *
326 *  2. If you implement this using a "halt", "idle", or "shutdown"
327 *     instruction, then don't forget to put it in an infinite loop.
328 *
329 *  3. Be warned. Some processors with onboard DMA have been known
330 *     to stop the DMA if the CPU were put in IDLE mode.  This might
331 *     also be a problem with other on-chip peripherals.  So use this
332 *     hook with caution.
333 */
334
335void _CPU_Internal_threads_Idle_thread_body( void )
336{
337  while (1)
338    pause();
339}
340
341/*PAGE
342 *
343 *  _CPU_Context_Initialize
344 */
345
346void _CPU_Context_Initialize(
347  Context_Control  *_the_context,
348  unsigned32       *_stack_base,
349  unsigned32        _size,
350  unsigned32        _new_level,
351  void             *_entry_point
352)
353{
354  void        *source;
355  unsigned32  *addr;
356  unsigned32   jmp_addr;
357  unsigned32   _stack_low;   /* lowest "stack aligned" address */
358  unsigned32   _stack_high;  /* highest "stack aligned" address */
359  unsigned32   _the_size;
360
361  jmp_addr = (unsigned32) _entry_point;
362
363  /*
364   *  On CPUs with stacks which grow down, we build the stack
365   *  based on the _stack_high address.  On CPUs with stacks which
366   *  grow up, we build the stack based on the _stack_low address. 
367   */
368
369  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
370  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
371
372  _stack_high = ((unsigned32)(_stack_base) + _size);
373  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
374
375  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
376
377  /*
378   * Slam our jmp_buf template into the context we are creating
379   */
380
381  if ( _new_level == 0 )
382    source = _CPU_Context_Default_with_ISRs_enabled.regs;
383  else
384    source = _CPU_Context_Default_with_ISRs_disabled.regs;
385     
386  memcpy(_the_context, source, sizeof(jmp_buf));
387
388  addr = (unsigned32 *)_the_context;
389
390#if defined(hppa1_1)
391  *(addr + RP_OFF) = jmp_addr;
392  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
393
394  /*
395   * See if we are using shared libraries by checking
396   * bit 30 in 24 off of newp. If bit 30 is set then
397   * we are using shared libraries and the jump address
398   * is at what 24 off of newp points to so shove that
399   * into 24 off of newp instead.
400   */
401
402  if (jmp_addr & 0x40000000) {
403    jmp_addr &= 0xfffffffc;
404     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
405  }
406#elif defined(sparc)
407
408  /*
409   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
410   *  diagram of the stack.
411   */
412
413  asm ("ta  0x03");            /* flush registers */
414
415  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
416  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
417  *(addr + FP_OFF) = (unsigned32)(_stack_high);
418
419#elif defined(i386)
420 
421    /*
422     *  This information was gathered by disassembling setjmp().
423     */
424
425    {
426      unsigned32 stack_ptr;
427
428      stack_ptr = _stack_high - CPU_FRAME_SIZE;
429
430      *(addr + EBX_OFF) = 0xFEEDFEED;
431      *(addr + ESI_OFF) = 0xDEADDEAD;
432      *(addr + EDI_OFF) = 0xDEAFDEAF;
433      *(addr + EBP_OFF) = stack_ptr;
434      *(addr + ESP_OFF) = stack_ptr;
435      *(addr + RET_OFF) = jmp_addr;
436 
437      addr = (unsigned32 *) stack_ptr;
438 
439      addr[ 0 ] = jmp_addr;
440      addr[ 1 ] = (unsigned32) stack_ptr;
441      addr[ 2 ] = (unsigned32) stack_ptr;
442    }
443
444#else
445#error "UNKNOWN CPU!!!"
446#endif
447
448}
449
450/*PAGE
451 *
452 *  _CPU_Context_restore
453 */
454
455void _CPU_Context_restore(
456  Context_Control  *next
457)
458{
459  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
460  longjmp( next->regs, 0 );
461}
462
463/*PAGE
464 *
465 *  _CPU_Context_switch
466 */
467
468void _CPU_Context_switch(
469  Context_Control  *current,
470  Context_Control  *next
471)
472{
473  /*
474   *  Switch levels in one operation
475   */
476
477  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
478
479  if (setjmp(current->regs) == 0) {    /* Save the current context */
480     longjmp(next->regs, 0);           /* Switch to the new context */
481  }
482}
483 
484/*PAGE
485 *
486 *  _CPU_Save_float_context
487 */
488
489void _CPU_Save_float_context(
490  Context_Control_fp *fp_context
491)
492{
493}
494
495/*PAGE
496 *
497 *  _CPU_Restore_float_context
498 */
499
500void _CPU_Restore_float_context(
501  Context_Control_fp *fp_context
502)
503{
504}
505
506/*PAGE
507 *
508 *  _CPU_ISR_Disable_support
509 */
510
511unsigned32 _CPU_ISR_Disable_support(void)
512{
513  sigset_t  old_mask;
514
515  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
516
517  if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)) != 0)
518    return 1;
519
520  return 0;
521}
522
523/*PAGE
524 *
525 *  _CPU_ISR_Enable
526 */
527
528void _CPU_ISR_Enable(
529  unsigned32 level
530)
531{
532  if (level == 0)
533    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
534  else
535    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
536}
537
538/*PAGE
539 *
540 *  _CPU_ISR_Handler
541 *
542 *  External interrupt handler.
543 *  This is installed as a UNIX signal handler.
544 *  It vectors out to specific user interrupt handlers.
545 */
546
547void _CPU_ISR_Handler(int vector)
548{
549  extern void        _Thread_Dispatch(void);
550  extern unsigned32  _Thread_Dispatch_disable_level;
551  extern boolean     _Context_Switch_necessary;
552
553
554  if (_ISR_Nest_level++ == 0) {
555      /* switch to interrupt stack */
556  }
557
558  _Thread_Dispatch_disable_level++;
559
560  if (_ISR_Vector_table[vector]) {
561     _ISR_Vector_table[vector](vector);
562  } else {
563     _CPU_Stray_signal(vector);
564  }
565
566  if (_ISR_Nest_level-- == 0) {
567      /* switch back to original stack */
568  }
569
570  _Thread_Dispatch_disable_level--;
571
572  if (_Thread_Dispatch_disable_level == 0 &&
573      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
574      _CPU_ISR_Enable(0);
575      _Thread_Dispatch();
576  }
577}
578
579/*PAGE
580 *
581 *  _CPU_Stray_signal
582 */
583
584void _CPU_Stray_signal(int sig_num)
585{
586  char buffer[ 80 ];   
587
588  /*
589   *  We avoid using the stdio section of the library.
590   *  The following is generally safe.
591   */
592
593  write( 
594    2,
595    buffer, 
596    sprintf( buffer, "Stray signal %d\n", sig_num )
597  );
598 
599  /*
600   * If it was a "fatal" signal, then exit here
601   * If app code has installed a hander for one of these, then
602   * we won't call _CPU_Stray_signal, so this is ok.
603   */
604 
605  switch (sig_num) {
606      case SIGINT:
607      case SIGHUP:
608      case SIGQUIT:
609      case SIGILL:
610#ifdef SIGEMT
611      case SIGEMT:
612#endif
613      case SIGKILL:
614      case SIGBUS:
615      case SIGSEGV:
616      case SIGTERM:
617          _CPU_Fatal_error(0x100 + sig_num);
618  }
619}
620
621/*PAGE
622 *
623 *  _CPU_Fatal_error
624 */
625
626void _CPU_Fatal_error(unsigned32 error)
627{
628  setitimer(ITIMER_REAL, 0, 0);
629
630  if ( error ) {
631#ifdef RTEMS_DEBUG
632    abort();
633#endif
634    if (getenv("RTEMS_DEBUG"))
635      abort();
636  }
637
638  _exit(error);
639}
640
641/*PAGE
642 *
643 *  _CPU_ffs
644 */
645
646int _CPU_ffs(unsigned32 value)
647{
648  int output;
649  extern int ffs( int );
650
651  output = ffs(value);
652  output = output - 1;
653
654  return output;
655}
Note: See TracBrowser for help on using the repository browser.