1 | /* |
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2 | * HP PA-RISC CPU Dependent Source |
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3 | * |
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4 | * |
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5 | * To anyone who acknowledges that this file is provided "AS IS" |
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6 | * without any express or implied warranty: |
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7 | * permission to use, copy, modify, and distribute this file |
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8 | * for any purpose is hereby granted without fee, provided that |
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9 | * the above copyright notice and this notice appears in all |
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10 | * copies, and that the name of Division Incorporated not be |
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11 | * used in advertising or publicity pertaining to distribution |
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12 | * of the software without specific, written prior permission. |
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13 | * Division Incorporated makes no representations about the |
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14 | * suitability of this software for any purpose. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #include <rtems/system.h> |
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20 | #include <rtems/isr.h> |
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21 | |
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22 | #include <stdio.h> |
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23 | #include <stdlib.h> |
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24 | #include <signal.h> |
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25 | #include <time.h> |
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26 | #include <sys/time.h> |
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27 | |
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28 | #ifndef SA_RESTART |
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29 | #define SA_RESTART 0 |
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30 | #endif |
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31 | |
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32 | void _CPU_Signal_initialize(void); |
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33 | void _CPU_Stray_signal(int); |
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34 | void _CPU_ISR_Handler(int); |
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35 | |
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36 | sigset_t _CPU_Signal_mask; |
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37 | Context_Control _CPU_Context_Default_with_ISRs_enabled; |
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38 | Context_Control _CPU_Context_Default_with_ISRs_disabled; |
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39 | |
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40 | /* |
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41 | * Which cpu are we? Used by libcpu and libbsp. |
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42 | */ |
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43 | |
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44 | int cpu_number; |
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45 | |
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46 | /*PAGE |
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47 | * |
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48 | * _CPU_ISR_From_CPU_Init |
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49 | */ |
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50 | |
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51 | void _CPU_ISR_From_CPU_Init() |
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52 | { |
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53 | unsigned32 i; |
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54 | proc_ptr old_handler; |
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55 | |
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56 | |
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57 | /* |
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58 | * Block all the signals except SIGTRAP for the debugger |
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59 | * and SIGABRT for fatal errors. |
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60 | */ |
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61 | |
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62 | _CPU_ISR_Enable(1); |
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63 | |
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64 | (void) sigfillset(&_CPU_Signal_mask); |
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65 | (void) sigdelset(&_CPU_Signal_mask, SIGTRAP); |
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66 | (void) sigdelset(&_CPU_Signal_mask, SIGABRT); |
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67 | (void) sigdelset(&_CPU_Signal_mask, SIGIOT); |
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68 | (void) sigdelset(&_CPU_Signal_mask, SIGCONT); |
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69 | |
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70 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
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71 | |
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72 | /* |
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73 | * Set the handler for all signals to be signal_handler |
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74 | * which will then vector out to the correct handler |
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75 | * for whichever signal actually happened. Initially |
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76 | * set the vectors to the stray signal handler. |
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77 | */ |
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78 | |
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79 | for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) |
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80 | (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler); |
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81 | |
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82 | _CPU_Signal_initialize(); |
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83 | } |
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84 | |
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85 | void _CPU_Signal_initialize( void ) |
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86 | { |
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87 | struct sigaction act; |
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88 | sigset_t mask; |
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89 | |
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90 | /* mark them all active except for TraceTrap and Abort */ |
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91 | |
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92 | sigfillset(&mask); |
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93 | sigdelset(&mask, SIGTRAP); |
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94 | sigdelset(&mask, SIGABRT); |
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95 | sigdelset(&mask, SIGIOT); |
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96 | sigdelset(&mask, SIGCONT); |
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97 | sigprocmask(SIG_UNBLOCK, &mask, 0); |
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98 | |
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99 | act.sa_handler = _CPU_ISR_Handler; |
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100 | act.sa_mask = mask; |
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101 | act.sa_flags = SA_RESTART; |
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102 | |
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103 | sigaction(SIGHUP, &act, 0); |
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104 | sigaction(SIGINT, &act, 0); |
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105 | sigaction(SIGQUIT, &act, 0); |
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106 | sigaction(SIGILL, &act, 0); |
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107 | #ifdef SIGEMT |
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108 | sigaction(SIGEMT, &act, 0); |
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109 | #endif |
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110 | sigaction(SIGFPE, &act, 0); |
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111 | sigaction(SIGKILL, &act, 0); |
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112 | sigaction(SIGBUS, &act, 0); |
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113 | sigaction(SIGSEGV, &act, 0); |
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114 | #ifdef SIGSYS |
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115 | sigaction(SIGSYS, &act, 0); |
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116 | #endif |
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117 | sigaction(SIGPIPE, &act, 0); |
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118 | sigaction(SIGALRM, &act, 0); |
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119 | sigaction(SIGTERM, &act, 0); |
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120 | sigaction(SIGUSR1, &act, 0); |
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121 | sigaction(SIGUSR2, &act, 0); |
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122 | sigaction(SIGCHLD, &act, 0); |
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123 | sigaction(SIGCLD, &act, 0); |
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124 | sigaction(SIGPWR, &act, 0); |
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125 | sigaction(SIGVTALRM, &act, 0); |
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126 | sigaction(SIGPROF, &act, 0); |
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127 | sigaction(SIGIO, &act, 0); |
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128 | sigaction(SIGWINCH, &act, 0); |
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129 | sigaction(SIGSTOP, &act, 0); |
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130 | sigaction(SIGTTIN, &act, 0); |
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131 | sigaction(SIGTTOU, &act, 0); |
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132 | sigaction(SIGURG, &act, 0); |
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133 | /* |
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134 | * XXX: Really should be on HPUX. |
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135 | */ |
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136 | |
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137 | #if defined(hppa1_1) |
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138 | sigaction(SIGLOST, &act, 0); |
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139 | #endif |
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140 | |
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141 | } |
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142 | |
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143 | /*PAGE |
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144 | * |
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145 | * _CPU_Context_From_CPU_Init |
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146 | */ |
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147 | |
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148 | void _CPU_Context_From_CPU_Init() |
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149 | { |
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150 | |
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151 | #if defined(hppa1_1) && defined(RTEMS_UNIXLIB) |
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152 | /* |
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153 | * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp |
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154 | * will handle the full 32 floating point registers. |
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155 | * |
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156 | * NOTE: Is this a bug in HPUX9? |
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157 | */ |
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158 | |
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159 | { |
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160 | extern unsigned32 _SYSTEM_ID; |
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161 | |
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162 | _SYSTEM_ID = 0x20c; |
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163 | } |
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164 | #endif |
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165 | |
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166 | /* |
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167 | * get default values to use in _CPU_Context_Initialize() |
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168 | */ |
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169 | |
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170 | _CPU_ISR_Set_level( 0 ); |
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171 | setjmp( _CPU_Context_Default_with_ISRs_enabled.regs ); |
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172 | sigprocmask( |
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173 | SIG_SETMASK, /* ignored when second arg is NULL */ |
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174 | 0, |
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175 | &_CPU_Context_Default_with_ISRs_enabled.isr_level |
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176 | ); |
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177 | |
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178 | _CPU_ISR_Set_level( 1 ); |
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179 | setjmp( _CPU_Context_Default_with_ISRs_disabled.regs ); |
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180 | sigprocmask( |
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181 | SIG_SETMASK, /* ignored when second arg is NULL */ |
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182 | 0, |
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183 | &_CPU_Context_Default_with_ISRs_disabled.isr_level |
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184 | ); |
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185 | |
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186 | } |
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187 | |
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188 | /* _CPU_Initialize |
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189 | * |
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190 | * This routine performs processor dependent initialization. |
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191 | * |
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192 | * INPUT PARAMETERS: |
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193 | * cpu_table - CPU table to initialize |
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194 | * thread_dispatch - address of disptaching routine |
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195 | */ |
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196 | |
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197 | |
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198 | void _CPU_Initialize( |
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199 | rtems_cpu_table *cpu_table, |
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200 | void (*thread_dispatch) /* ignored on this CPU */ |
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201 | ) |
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202 | { |
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203 | if ( cpu_table == NULL ) |
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204 | _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED ); |
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205 | |
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206 | /* |
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207 | * The thread_dispatch argument is the address of the entry point |
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208 | * for the routine called at the end of an ISR once it has been |
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209 | * decided a context switch is necessary. On some compilation |
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210 | * systems it is difficult to call a high-level language routine |
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211 | * from assembly. This allows us to trick these systems. |
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212 | * |
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213 | * If you encounter this problem save the entry point in a CPU |
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214 | * dependent variable. |
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215 | */ |
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216 | |
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217 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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218 | |
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219 | /* |
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220 | * XXX; If there is not an easy way to initialize the FP context |
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221 | * during Context_Initialize, then it is usually easier to |
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222 | * save an "uninitialized" FP context here and copy it to |
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223 | * the task's during Context_Initialize. |
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224 | */ |
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225 | |
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226 | /* XXX: FP context initialization support */ |
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227 | |
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228 | _CPU_Table = *cpu_table; |
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229 | |
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230 | _CPU_ISR_From_CPU_Init(); |
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231 | |
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232 | _CPU_Context_From_CPU_Init(); |
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233 | |
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234 | } |
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235 | |
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236 | /*PAGE |
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237 | * |
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238 | * _CPU_ISR_install_raw_handler |
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239 | */ |
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240 | |
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241 | void _CPU_ISR_install_raw_handler( |
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242 | unsigned32 vector, |
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243 | proc_ptr new_handler, |
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244 | proc_ptr *old_handler |
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245 | ) |
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246 | { |
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247 | _CPU_Fatal_halt( 0xdeaddead ); |
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248 | } |
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249 | |
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250 | /*PAGE |
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251 | * |
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252 | * _CPU_ISR_install_vector |
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253 | * |
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254 | * This kernel routine installs the RTEMS handler for the |
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255 | * specified vector. |
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256 | * |
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257 | * Input parameters: |
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258 | * vector - interrupt vector number |
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259 | * old_handler - former ISR for this vector number |
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260 | * new_handler - replacement ISR for this vector number |
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261 | * |
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262 | * Output parameters: NONE |
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263 | * |
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264 | */ |
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265 | |
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266 | |
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267 | void _CPU_ISR_install_vector( |
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268 | unsigned32 vector, |
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269 | proc_ptr new_handler, |
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270 | proc_ptr *old_handler |
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271 | ) |
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272 | { |
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273 | *old_handler = _ISR_Vector_table[ vector ]; |
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274 | |
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275 | /* |
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276 | * If the interrupt vector table is a table of pointer to isr entry |
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277 | * points, then we need to install the appropriate RTEMS interrupt |
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278 | * handler for this vector number. |
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279 | */ |
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280 | |
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281 | /* |
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282 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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283 | * be used by the _CPU_ISR_Handler so the user gets control. |
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284 | */ |
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285 | |
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286 | _ISR_Vector_table[ vector ] = new_handler; |
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287 | } |
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288 | |
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289 | /*PAGE |
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290 | * |
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291 | * _CPU_Install_interrupt_stack |
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292 | */ |
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293 | |
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294 | void _CPU_Install_interrupt_stack( void ) |
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295 | { |
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296 | } |
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297 | |
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298 | /*PAGE |
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299 | * |
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300 | * _CPU_Internal_threads_Idle_thread_body |
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301 | * |
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302 | * NOTES: |
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303 | * |
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304 | * 1. This is the same as the regular CPU independent algorithm. |
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305 | * |
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306 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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307 | * instruction, then don't forget to put it in an infinite loop. |
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308 | * |
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309 | * 3. Be warned. Some processors with onboard DMA have been known |
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310 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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311 | * also be a problem with other on-chip peripherals. So use this |
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312 | * hook with caution. |
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313 | */ |
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314 | |
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315 | void _CPU_Internal_threads_Idle_thread_body( void ) |
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316 | { |
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317 | while (1) |
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318 | pause(); |
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319 | } |
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320 | |
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321 | /*PAGE |
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322 | * |
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323 | * _CPU_Context_Initialize |
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324 | */ |
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325 | |
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326 | void _CPU_Context_Initialize( |
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327 | Context_Control *_the_context, |
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328 | unsigned32 *_stack_base, |
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329 | unsigned32 _size, |
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330 | unsigned32 _new_level, |
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331 | void *_entry_point |
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332 | ) |
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333 | { |
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334 | void *source; |
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335 | unsigned32 *addr; |
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336 | unsigned32 jmp_addr; |
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337 | unsigned32 _stack_low; /* lowest "stack aligned" address */ |
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338 | unsigned32 _stack_high; /* highest "stack aligned" address */ |
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339 | unsigned32 _the_size; |
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340 | |
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341 | jmp_addr = (unsigned32) _entry_point; |
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342 | |
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343 | /* |
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344 | * On CPUs with stacks which grow down, we build the stack |
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345 | * based on the _stack_high address. On CPUs with stacks which |
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346 | * grow up, we build the stack based on the _stack_low address. |
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347 | */ |
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348 | |
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349 | _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT); |
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350 | _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); |
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351 | |
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352 | _stack_high = ((unsigned32)(_stack_base) + _size); |
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353 | _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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354 | |
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355 | _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1); |
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356 | |
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357 | /* |
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358 | * Slam our jmp_buf template into the context we are creating |
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359 | */ |
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360 | |
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361 | if ( _new_level == 0 ) |
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362 | source = _CPU_Context_Default_with_ISRs_enabled.regs; |
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363 | else |
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364 | source = _CPU_Context_Default_with_ISRs_disabled.regs; |
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365 | |
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366 | memcpy(_the_context, source, sizeof(jmp_buf)); |
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367 | |
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368 | addr = (unsigned32 *)_the_context; |
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369 | |
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370 | #if defined(hppa1_1) |
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371 | *(addr + RP_OFF) = jmp_addr; |
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372 | *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE); |
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373 | |
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374 | /* |
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375 | * See if we are using shared libraries by checking |
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376 | * bit 30 in 24 off of newp. If bit 30 is set then |
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377 | * we are using shared libraries and the jump address |
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378 | * is at what 24 off of newp points to so shove that |
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379 | * into 24 off of newp instead. |
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380 | */ |
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381 | |
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382 | if (jmp_addr & 0x40000000) { |
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383 | jmp_addr &= 0xfffffffc; |
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384 | *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr; |
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385 | } |
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386 | #elif defined(sparc) |
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387 | |
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388 | /* |
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389 | * See /usr/include/sys/stack.h in Solaris 2.3 for a nice |
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390 | * diagram of the stack. |
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391 | */ |
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392 | |
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393 | asm ("ta 0x03"); /* flush registers */ |
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394 | |
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395 | *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; |
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396 | *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE); |
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397 | *(addr + FP_OFF) = (unsigned32)(_stack_high); |
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398 | |
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399 | #elif defined(i386) |
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400 | |
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401 | /* |
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402 | * This information was gathered by disassembling setjmp(). |
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403 | */ |
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404 | |
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405 | { |
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406 | unsigned32 stack_ptr; |
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407 | |
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408 | stack_ptr = _stack_high - CPU_FRAME_SIZE; |
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409 | |
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410 | *(addr + EBX_OFF) = 0xFEEDFEED; |
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411 | *(addr + ESI_OFF) = 0xDEADDEAD; |
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412 | *(addr + EDI_OFF) = 0xDEAFDEAF; |
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413 | *(addr + EBP_OFF) = stack_ptr; |
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414 | *(addr + ESP_OFF) = stack_ptr; |
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415 | *(addr + RET_OFF) = jmp_addr; |
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416 | |
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417 | addr = (unsigned32 *) stack_ptr; |
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418 | |
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419 | addr[ 0 ] = jmp_addr; |
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420 | addr[ 1 ] = (unsigned32) stack_ptr; |
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421 | addr[ 2 ] = (unsigned32) stack_ptr; |
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422 | } |
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423 | |
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424 | #else |
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425 | #error "UNKNOWN CPU!!!" |
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426 | #endif |
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427 | |
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428 | } |
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429 | |
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430 | /*PAGE |
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431 | * |
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432 | * _CPU_Context_restore |
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433 | */ |
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434 | |
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435 | void _CPU_Context_restore( |
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436 | Context_Control *next |
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437 | ) |
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438 | { |
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439 | sigprocmask( SIG_SETMASK, &next->isr_level, 0 ); |
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440 | longjmp( next->regs, 0 ); |
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441 | } |
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442 | |
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443 | /*PAGE |
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444 | * |
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445 | * _CPU_Context_switch |
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446 | */ |
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447 | |
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448 | void _CPU_Context_switch( |
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449 | Context_Control *current, |
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450 | Context_Control *next |
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451 | ) |
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452 | { |
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453 | /* |
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454 | * Switch levels in one operation |
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455 | */ |
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456 | |
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457 | sigprocmask( SIG_SETMASK, &next->isr_level, ¤t->isr_level ); |
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458 | |
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459 | if (setjmp(current->regs) == 0) { /* Save the current context */ |
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460 | longjmp(next->regs, 0); /* Switch to the new context */ |
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461 | } |
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462 | } |
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463 | |
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464 | /*PAGE |
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465 | * |
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466 | * _CPU_Save_float_context |
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467 | */ |
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468 | |
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469 | void _CPU_Save_float_context( |
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470 | Context_Control_fp *fp_context |
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471 | ) |
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472 | { |
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473 | } |
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474 | |
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475 | /*PAGE |
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476 | * |
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477 | * _CPU_Restore_float_context |
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478 | */ |
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479 | |
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480 | void _CPU_Restore_float_context( |
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481 | Context_Control_fp *fp_context |
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482 | ) |
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483 | { |
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484 | } |
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485 | |
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486 | /*PAGE |
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487 | * |
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488 | * _CPU_ISR_Disable_support |
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489 | */ |
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490 | |
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491 | unsigned32 _CPU_ISR_Disable_support(void) |
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492 | { |
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493 | sigset_t old_mask; |
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494 | sigset_t empty_mask; |
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495 | |
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496 | sigemptyset(&empty_mask); |
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497 | sigemptyset(&old_mask); |
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498 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask); |
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499 | |
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500 | if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0) |
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501 | return 1; |
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502 | |
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503 | return 0; |
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504 | } |
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505 | |
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506 | /*PAGE |
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507 | * |
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508 | * _CPU_ISR_Enable |
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509 | */ |
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510 | |
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511 | void _CPU_ISR_Enable( |
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512 | unsigned32 level |
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513 | ) |
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514 | { |
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515 | if (level == 0) |
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516 | sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0); |
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517 | else |
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518 | sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); |
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519 | } |
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520 | |
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521 | /*PAGE |
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522 | * |
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523 | * _CPU_ISR_Handler |
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524 | * |
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525 | * External interrupt handler. |
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526 | * This is installed as a UNIX signal handler. |
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527 | * It vectors out to specific user interrupt handlers. |
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528 | */ |
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529 | |
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530 | void _CPU_ISR_Handler(int vector) |
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531 | { |
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532 | extern void _Thread_Dispatch(void); |
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533 | extern unsigned32 _Thread_Dispatch_disable_level; |
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534 | extern boolean _Context_Switch_necessary; |
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535 | |
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536 | |
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537 | if (_ISR_Nest_level++ == 0) { |
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538 | /* switch to interrupt stack */ |
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539 | } |
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540 | |
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541 | _Thread_Dispatch_disable_level++; |
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542 | |
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543 | if (_ISR_Vector_table[vector]) { |
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544 | _ISR_Vector_table[vector](vector); |
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545 | } else { |
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546 | _CPU_Stray_signal(vector); |
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547 | } |
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548 | |
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549 | if (_ISR_Nest_level-- == 0) { |
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550 | /* switch back to original stack */ |
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551 | } |
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552 | |
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553 | _Thread_Dispatch_disable_level--; |
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554 | |
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555 | if (_Thread_Dispatch_disable_level == 0 && |
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556 | (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { |
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557 | _CPU_ISR_Enable(0); |
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558 | _Thread_Dispatch(); |
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559 | } |
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560 | } |
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561 | |
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562 | /*PAGE |
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563 | * |
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564 | * _CPU_Stray_signal |
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565 | */ |
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566 | |
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567 | void _CPU_Stray_signal(int sig_num) |
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568 | { |
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569 | char buffer[ 80 ]; |
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570 | |
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571 | /* |
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572 | * We avoid using the stdio section of the library. |
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573 | * The following is generally safe. |
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574 | */ |
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575 | |
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576 | write( |
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577 | 2, |
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578 | buffer, |
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579 | sprintf( buffer, "Stray signal %d\n", sig_num ) |
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580 | ); |
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581 | |
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582 | /* |
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583 | * If it was a "fatal" signal, then exit here |
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584 | * If app code has installed a hander for one of these, then |
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585 | * we won't call _CPU_Stray_signal, so this is ok. |
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586 | */ |
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587 | |
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588 | switch (sig_num) { |
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589 | case SIGINT: |
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590 | case SIGHUP: |
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591 | case SIGQUIT: |
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592 | case SIGILL: |
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593 | #ifdef SIGEMT |
---|
594 | case SIGEMT: |
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595 | #endif |
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596 | case SIGKILL: |
---|
597 | case SIGBUS: |
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598 | case SIGSEGV: |
---|
599 | case SIGTERM: |
---|
600 | _CPU_Fatal_error(0x100 + sig_num); |
---|
601 | } |
---|
602 | } |
---|
603 | |
---|
604 | /*PAGE |
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605 | * |
---|
606 | * _CPU_Fatal_error |
---|
607 | */ |
---|
608 | |
---|
609 | void _CPU_Fatal_error(unsigned32 error) |
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610 | { |
---|
611 | setitimer(ITIMER_REAL, 0, 0); |
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612 | |
---|
613 | _exit(error); |
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614 | } |
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615 | |
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616 | /*PAGE |
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617 | * |
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618 | * _CPU_ffs |
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619 | */ |
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620 | |
---|
621 | int _CPU_ffs(unsigned32 value) |
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622 | { |
---|
623 | int output; |
---|
624 | extern int ffs( int ); |
---|
625 | |
---|
626 | output = ffs(value); |
---|
627 | output = output - 1; |
---|
628 | |
---|
629 | return output; |
---|
630 | } |
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