source: rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h @ c86da31c

4.115
Last change on this file since c86da31c was c86da31c, checked in by Joel Sherrill <joel.sherrill@…>, on 06/15/10 at 22:43:56

2010-06-15 Joel Sherrill <joel.sherrill@…>

PR 1561/cpukit

  • .cvsignore, ChangeLog?, Makefile.am, Makefile.in, README, context.S, cpu.c, preinstall.am, rtems/asm.h, rtems/score/cpu.h, rtems/score/sparc64.h, rtems/score/types.h: New files.
  • Property mode set to 100644
File size: 31.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the port of
7 *  the executive to the SPARC64 processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  This file is based on the SPARC cpu.h file. Modifications are made
13 *  to support the SPARC64 processor.
14 *    COPYRIGHT (c) 2010. Gedare Bloom.
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *  http://www.rtems.com/license/LICENSE.
19 *
20 *  $Id$
21 */
22
23#ifndef _RTEMS_SCORE_CPU_H
24#define _RTEMS_SCORE_CPU_H
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems/score/sparc64.h>               /* pick up machine definitions */
31#ifndef ASM
32#include <rtems/score/types.h>
33#endif
34
35/* conditional compilation parameters */
36
37/*
38 *  Should the calls to _Thread_Enable_dispatch be inlined?
39 *
40 *  If TRUE, then they are inlined.
41 *  If FALSE, then a subroutine call is made.
42 */
43
44#define CPU_INLINE_ENABLE_DISPATCH       TRUE
45
46/*
47 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
48 *  be unrolled one time?  In unrolled each iteration of the loop examines
49 *  two "nodes" on the chain being searched.  Otherwise, only one node
50 *  is examined per iteration.
51 *
52 *  If TRUE, then the loops are unrolled.
53 *  If FALSE, then the loops are not unrolled.
54 *
55 *  This parameter could go either way on the SPARC.  The interrupt flash
56 *  code is relatively lengthy given the requirements for nops following
57 *  writes to the psr.  But if the clock speed were high enough, this would
58 *  not represent a great deal of time.
59 */
60
61#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
62
63/*
64 *  Does the executive manage a dedicated interrupt stack in software?
65 *
66 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
67 *  If FALSE, nothing is done.
68 *
69 *  The SPARC does not have a dedicated HW interrupt stack and one has
70 *  been implemented in SW.
71 */
72
73#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
74
75/*
76 *  Does the CPU follow the simple vectored interrupt model?
77 *
78 *  If TRUE, then RTEMS allocates the vector table it internally manages.
79 *  If FALSE, then the BSP is assumed to allocate and manage the vector
80 *  table
81 *
82 *  SPARC Specific Information:
83 *
84 *  XXX document implementation including references if appropriate
85 */
86#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
87
88/*
89 *  Does this CPU have hardware support for a dedicated interrupt stack?
90 *
91 *  If TRUE, then it must be installed during initialization.
92 *  If FALSE, then no installation is performed.
93 *
94 *  The SPARC does not have a dedicated HW interrupt stack.
95 */
96
97#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
98
99/*
100 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
101 *
102 *  If TRUE, then the memory is allocated during initialization.
103 *  If FALSE, then the memory is allocated during initialization.
104 */
105
106#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
107
108/*
109 *  Does the RTEMS invoke the user's ISR with the vector number and
110 *  a pointer to the saved interrupt frame (1) or just the vector
111 *  number (0)?
112 */
113
114#define CPU_ISR_PASSES_FRAME_POINTER 0
115
116/*
117 *  Does the CPU have hardware floating point?
118 *
119 *  If TRUE, then the FLOATING_POINT task attribute is supported.
120 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
121 */
122
123#if ( SPARC_HAS_FPU == 1 )
124#define CPU_HARDWARE_FP     TRUE
125#else
126#define CPU_HARDWARE_FP     FALSE
127#endif
128#define CPU_SOFTWARE_FP     FALSE
129
130/*
131 *  Are all tasks FLOATING_POINT tasks implicitly?
132 *
133 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
134 *  If FALSE, then the FLOATING_POINT task attribute is followed.
135 */
136
137#define CPU_ALL_TASKS_ARE_FP     FALSE
138
139/*
140 *  Should the IDLE task have a floating point context?
141 *
142 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
143 *  and it has a floating point context which is switched in and out.
144 *  If FALSE, then the IDLE task does not have a floating point context.
145 */
146
147#define CPU_IDLE_TASK_IS_FP      FALSE
148
149/*
150 *  Should the saving of the floating point registers be deferred
151 *  until a context switch is made to another different floating point
152 *  task?
153 *
154 *  If TRUE, then the floating point context will not be stored until
155 *  necessary.  It will remain in the floating point registers and not
156 *  disturned until another floating point task is switched to.
157 *
158 *  If FALSE, then the floating point context is saved when a floating
159 *  point task is switched out and restored when the next floating point
160 *  task is restored.  The state of the floating point registers between
161 *  those two operations is not specified.
162 */
163
164#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
165
166/*
167 *  Does this port provide a CPU dependent IDLE task implementation?
168 *
169 *  If TRUE, then the routine _CPU_Thread_Idle_body
170 *  must be provided and is the default IDLE thread body instead of
171 *  _CPU_Thread_Idle_body.
172 *
173 *  If FALSE, then use the generic IDLE thread body if the BSP does
174 *  not provide one.
175 */
176
177#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
178
179/*
180 *  Does the stack grow up (toward higher addresses) or down
181 *  (toward lower addresses)?
182 *
183 *  If TRUE, then the grows upward.
184 *  If FALSE, then the grows toward smaller addresses.
185 *
186 *  The stack grows to lower addresses on the SPARC.
187 */
188
189#define CPU_STACK_GROWS_UP               FALSE
190
191/*
192 *  The following is the variable attribute used to force alignment
193 *  of critical data structures.  On some processors it may make
194 *  sense to have these aligned on tighter boundaries than
195 *  the minimum requirements of the compiler in order to have as
196 *  much of the critical data area as possible in a cache line.
197 *
198 *  The SPARC does not appear to have particularly strict alignment
199 *  requirements.  This value (16) was chosen to take advantages of caches.
200 *
201 *  SPARC 64 requirements on floating point alignment is at least 8,
202 *  and is 16 if quad-word fp instructions are available (e.g. LDQF).
203 */
204
205#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
206
207/*
208 *  Define what is required to specify how the network to host conversion
209 *  routines are handled.
210 */
211
212#define CPU_BIG_ENDIAN                           TRUE
213#define CPU_LITTLE_ENDIAN                        FALSE
214
215/*
216 *  The following defines the number of bits actually used in the
217 *  interrupt field of the task mode.  How those bits map to the
218 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
219 *
220 *  The SPARC v9 has 16 interrupt levels in the PIL field of the PSR.
221 */
222
223#define CPU_MODES_INTERRUPT_MASK   0x0000000F
224
225/*
226 *  This structure represents the organization of the minimum stack frame
227 *  for the SPARC.  More framing information is required in certain situaions
228 *  such as when there are a large number of out parameters or when the callee
229 *  must save floating point registers.
230 */
231
232#ifndef ASM
233
234typedef struct {
235  uint64_t    l0;
236  uint64_t    l1;
237  uint64_t    l2;
238  uint64_t    l3;
239  uint64_t    l4;
240  uint64_t    l5;
241  uint64_t    l6;
242  uint64_t    l7;
243  uint64_t    i0;
244  uint64_t    i1;
245  uint64_t    i2;
246  uint64_t    i3;
247  uint64_t    i4;
248  uint64_t    i5;
249  uint64_t    i6_fp;
250  uint64_t    i7;
251  void       *structure_return_address;
252  /*
253   *  The following are for the callee to save the register arguments in
254   *  should this be necessary.
255   */
256  uint64_t    saved_arg0;
257  uint64_t    saved_arg1;
258  uint64_t    saved_arg2;
259  uint64_t    saved_arg3;
260  uint64_t    saved_arg4;
261  uint64_t    saved_arg5;
262  uint64_t    pad0;
263}  CPU_Minimum_stack_frame;
264
265#endif /* !ASM */
266
267#define CPU_STACK_FRAME_L0_OFFSET             0x00
268#define CPU_STACK_FRAME_L1_OFFSET             0x08
269#define CPU_STACK_FRAME_L2_OFFSET             0x10
270#define CPU_STACK_FRAME_L3_OFFSET             0x18
271#define CPU_STACK_FRAME_L4_OFFSET             0x20
272#define CPU_STACK_FRAME_L5_OFFSET             0x28
273#define CPU_STACK_FRAME_L6_OFFSET             0x30
274#define CPU_STACK_FRAME_L7_OFFSET             0x38
275#define CPU_STACK_FRAME_I0_OFFSET             0x40
276#define CPU_STACK_FRAME_I1_OFFSET             0x48
277#define CPU_STACK_FRAME_I2_OFFSET             0x50
278#define CPU_STACK_FRAME_I3_OFFSET             0x58
279#define CPU_STACK_FRAME_I4_OFFSET             0x60
280#define CPU_STACK_FRAME_I5_OFFSET             0x68
281#define CPU_STACK_FRAME_I6_FP_OFFSET          0x70
282#define CPU_STACK_FRAME_I7_OFFSET             0x78
283#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x80
284#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x88
285#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x90
286#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x98
287#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0xA0
288#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0xA8
289#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0xB0
290#define CPU_STACK_FRAME_PAD0_OFFSET           0xB8
291
292#define CPU_MINIMUM_STACK_FRAME_SIZE          0xC0
293
294/*
295 * Contexts
296 *
297 *  Generally there are 2 types of context to save.
298 *     1. Interrupt registers to save
299 *     2. Task level registers to save
300 *
301 *  This means we have the following 3 context items:
302 *     1. task level context stuff::  Context_Control
303 *     2. floating point task stuff:: Context_Control_fp
304 *     3. special interrupt level context :: Context_Control_interrupt
305 *
306 *  On the SPARC, we are relatively conservative in that we save most
307 *  of the CPU state in the context area.  The ET (enable trap) bit and
308 *  the CWP (current window pointer) fields of the PSR are considered
309 *  system wide resources and are not maintained on a per-thread basis.
310 */
311
312#ifndef ASM
313
314typedef struct {
315    uint64_t   g1;
316    uint64_t   g2;
317    uint64_t   g3;
318    uint64_t   g4;
319    uint64_t   g5;
320    uint64_t   g6;
321    uint64_t   g7;
322
323    uint64_t   l0;
324    uint64_t   l1;
325    uint64_t   l2;
326    uint64_t   l3;
327    uint64_t   l4;
328    uint64_t   l5;
329    uint64_t   l6;
330    uint64_t   l7;
331
332    uint64_t   i0;
333    uint64_t   i1;
334    uint64_t   i2;
335    uint64_t   i3;
336    uint64_t   i4;
337    uint64_t   i5;
338    uint64_t   i6_fp;
339    uint64_t   i7;
340
341    uint64_t   o0;
342    uint64_t   o1;
343    uint64_t   o2;
344    uint64_t   o3;
345    uint64_t   o4;
346    uint64_t   o5;
347    uint64_t   o6_sp;
348    uint64_t   o7;
349
350    uint32_t   isr_dispatch_disable;
351    uint32_t   pad;
352} Context_Control;
353
354#define _CPU_Context_Get_SP( _context ) \
355  (_context)->o6_sp
356
357#endif /* ASM */
358
359/*
360 *  Offsets of fields with Context_Control for assembly routines.
361 */
362
363#define G1_OFFSET    0x00
364#define G2_OFFSET    0x08
365#define G3_OFFSET    0x10
366#define G4_OFFSET    0x18
367#define G5_OFFSET    0x20
368#define G6_OFFSET    0x28
369#define G7_OFFSET    0x30
370
371#define L0_OFFSET    0x38
372#define L1_OFFSET    0x40
373#define L2_OFFSET    0x48
374#define L3_OFFSET    0x50
375#define L4_OFFSET    0x58
376#define L5_OFFSET    0x60
377#define L6_OFFSET    0x68
378#define L7_OFFSET    0x70
379
380#define I0_OFFSET    0x78
381#define I1_OFFSET    0x80
382#define I2_OFFSET    0x88
383#define I3_OFFSET    0x90
384#define I4_OFFSET    0x98
385#define I5_OFFSET    0xA0
386#define I6_FP_OFFSET    0xA8
387#define I7_OFFSET 0xB0
388
389#define O0_OFFSET    0xB8
390#define O1_OFFSET    0xC0
391#define O2_OFFSET    0xC8
392#define O3_OFFSET    0xD0
393#define O4_OFFSET    0xD8
394#define O5_OFFSET    0xE0
395#define O6_SP_OFFSET    0xE8
396#define O7_OFFSET 0xF0
397
398#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8
399#define ISR_PAD_OFFSET 0xFC
400
401#define CONTEXT_CONTROL_SIZE 0x100
402
403/*
404 *  The floating point context area.
405 */
406
407#ifndef ASM
408
409typedef struct {
410    double      f0;     /* f0-f1 */
411    double      f2;     /* f2-f3 */
412    double      f4;     /* f4-f5 */
413    double      f6;     /* f6-f7 */
414    double      f8;     /* f8-f9 */
415    double      f10;    /* f10-f11 */
416    double      f12;    /* f12-f13 */
417    double      f14;    /* f14-f15 */
418    double      f16;    /* f16-f17 */
419    double      f18;    /* f18-f19 */
420    double      f20;    /* f20-f21 */
421    double      f22;    /* f22-f23 */
422    double      f24;    /* f24-f25 */
423    double      f26;    /* f26-f27 */
424    double      f28;    /* f28-f29 */
425    double      f30;    /* f30-f31 */
426    double      f32;
427    double      f34;
428    double      f36;
429    double      f38;
430    double      f40;
431    double      f42;
432    double      f44;
433    double      f46;
434    double      f48;
435    double      f50;
436    double      f52;
437    double      f54;
438    double      f56;
439    double      f58;
440    double      f60;
441    double      f62;
442    uint64_t    fsr;
443} Context_Control_fp;
444
445#endif /* !ASM */
446
447/*
448 *  Offsets of fields with Context_Control_fp for assembly routines.
449 */
450
451#define FO_OFFSET    0x00
452#define F2_OFFSET    0x08
453#define F4_OFFSET    0x10
454#define F6_OFFSET    0x18
455#define F8_OFFSET    0x20
456#define F1O_OFFSET   0x28
457#define F12_OFFSET   0x30
458#define F14_OFFSET   0x38
459#define F16_OFFSET   0x40
460#define F18_OFFSET   0x48
461#define F2O_OFFSET   0x50
462#define F22_OFFSET   0x58
463#define F24_OFFSET   0x60
464#define F26_OFFSET   0x68
465#define F28_OFFSET   0x70
466#define F3O_OFFSET   0x78
467#define F32_OFFSET   0x80
468#define F34_OFFSET   0x88
469#define F36_OFFSET   0x90
470#define F38_OFFSET   0x98
471#define F4O_OFFSET   0xA0
472#define F42_OFFSET   0xA8
473#define F44_OFFSET   0xB0
474#define F46_OFFSET   0xB8
475#define F48_OFFSET   0xC0
476#define F5O_OFFSET   0xC8
477#define F52_OFFSET   0xD0
478#define F54_OFFSET   0xD8
479#define F56_OFFSET   0xE0
480#define F58_OFFSET   0xE8
481#define F6O_OFFSET   0xF0
482#define F62_OFFSET   0xF8
483#define FSR_OFFSET   0x100
484
485#define CONTEXT_CONTROL_FP_SIZE 0x108
486
487#ifndef ASM
488
489/*
490 *  Context saved on stack for an interrupt.
491 *
492 *  NOTE:  The tstate, tpc, and tnpc are saved in this structure
493 *         to allow resetting the TL while still being able to return
494 *         from a trap later.  The PIL is saved because
495 *         if this is an external interrupt, we will mask lower
496 *         priority interrupts until finishing. Even though the y register
497 *         is deprecated, gcc still uses it.
498 */
499
500typedef struct {
501  CPU_Minimum_stack_frame  Stack_frame;
502  uint64_t                 tstate;
503  uint64_t                 tpc;
504  uint64_t                 tnpc;
505  uint64_t                 pil;
506  uint64_t                 y;
507  uint64_t                 g1;
508  uint64_t                 g2;
509  uint64_t                 g3;
510  uint64_t                 g4;
511  uint64_t                 g5;
512  uint64_t                 g6;
513  uint64_t                 g7;
514  uint64_t                 o0;
515  uint64_t                 o1;
516  uint64_t                 o2;
517  uint64_t                 o3;
518  uint64_t                 o4;
519  uint64_t                 o5;
520  uint64_t                 o6_sp;
521  uint64_t                 o7;
522} CPU_Interrupt_frame;
523
524#endif /* ASM */
525
526/*
527 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
528 */
529
530#define ISF_STACK_FRAME_OFFSET 0x00
531#define ISF_TSTATE_OFFSET      CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
532#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
533#define ISF_TNPC_OFFSET        CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
534#define ISF_PIL_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
535#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
536#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
537#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
538#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
539#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
540#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
541#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
542#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x58
543#define ISF_O0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x60
544#define ISF_O1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x68
545#define ISF_O2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x70
546#define ISF_O3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x78
547#define ISF_O4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x80
548#define ISF_O5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x88
549#define ISF_O6_SP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x90
550#define ISF_O7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x98
551#define ISF_TVEC_NUM            CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0
552
553#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8
554#ifndef ASM
555/*
556 *  This variable is contains the initialize context for the FP unit.
557 *  It is filled in by _CPU_Initialize and copied into the task's FP
558 *  context area during _CPU_Context_Initialize.
559 */
560
561SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
562
563/*
564 *  This stack is allocated by the Interrupt Manager and the switch
565 *  is performed in _ISR_Handler.  These variables contain pointers
566 *  to the lowest and highest addresses in the chunk of memory allocated
567 *  for the interrupt stack.  Since it is unknown whether the stack
568 *  grows up or down (in general), this give the CPU dependent
569 *  code the option of picking the version it wants to use.  Thus
570 *  both must be present if either is.
571 *
572 *  The SPARC supports a software based interrupt stack and these
573 *  are required.
574 */
575
576SCORE_EXTERN void *_CPU_Interrupt_stack_low;
577SCORE_EXTERN void *_CPU_Interrupt_stack_high;
578
579/*
580 *  This flag is context switched with each thread.  It indicates
581 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
582 *  By using this flag, we can avoid nesting more interrupt dispatching
583 *  attempts on a previously interrupted thread's stack.
584 */
585
586SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
587
588/*
589 *  The following type defines an entry in the SPARC's trap table.
590 *
591 *  NOTE: The instructions chosen are RTEMS dependent although one is
592 *        obligated to use two of the four instructions to perform a
593 *        long jump.  The other instructions load one register with the
594 *        trap type (a.k.a. vector) and another with the psr.
595 */
596/* For SPARC V9, we must use 6 of these instructions to perform a long
597 * jump, because the _handler value is now 64-bits. We also need to store
598 * temporary values in the global register set at this trap level. Because
599 * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3
600 * to pass parameters to ISR_Handler.
601 *
602 * The instruction sequence is now more like:
603 *      rdpr %tstate, %g4
604 *      setx _handler, %g2, %g3
605 *      jmp %g3+0
606 *      mov _vector, %g2
607 */
608typedef struct {
609  uint32_t     rdpr_tstate_g4;                  /* rdpr  %tstate, %g4        */
610  uint32_t     sethi_of_hh_handler_to_g2;       /* sethi %hh(_handler), %g2  */
611  uint32_t     or_g2_hm_handler_to_g2;          /* or %l3, %hm(_handler), %g2 */
612  uint32_t     sllx_g2_by_32_to_g2;             /* sllx   %g2, 32, %g2 */
613  uint32_t     sethi_of_handler_to_g3;          /* sethi %hi(_handler), %g3  */
614  uint32_t     or_g3_g2_to_g3;                  /* or     %g3, %g2, %g3 */
615  uint32_t     jmp_to_low_of_handler_plus_g3;   /* jmp   %g3 + %lo(_handler) */
616  uint32_t     mov_vector_g2;                   /* mov   _vector, %g2        */
617} CPU_Trap_table_entry;
618 
619/*
620 *  This is the set of opcodes for the instructions loaded into a trap
621 *  table entry.  The routine which installs a handler is responsible
622 *  for filling in the fields for the _handler address and the _vector
623 *  trap type.
624 *
625 *  The constants following this structure are masks for the fields which
626 *  must be filled in when the handler is installed.
627 */
628 
629extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
630
631/*
632 *  The size of the floating point context area. 
633 */
634
635#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
636
637#endif
638
639/*
640 *  Amount of extra stack (above minimum stack size) required by
641 *  MPCI receive server thread.  Remember that in a multiprocessor
642 *  system this thread must exist and be able to process all directives.
643 */
644
645#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
646
647/*
648 *  This defines the number of entries in the ISR_Vector_table managed
649 *  by the executive.
650 *
651 *  On the SPARC, there are really only 256 vectors.  However, the executive
652 *  has no easy, fast, reliable way to determine which traps are synchronous
653 *  and which are asynchronous.  By default, synchronous traps return to the
654 *  instruction which caused the interrupt.  So if you install a software
655 *  trap handler as an executive interrupt handler (which is desirable since
656 *  RTEMS takes care of window and register issues), then the executive needs
657 *  to know that the return address is to the trap rather than the instruction
658 *  following the trap.
659 *
660 *  So vectors 0 through 255 are treated as regular asynchronous traps which
661 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
662 *  by the executive to be synchronous and to require that the return address
663 *  be fudged.
664 *
665 *  If you use this mechanism to install a trap handler which must reexecute
666 *  the instruction which caused the trap, then it should be installed as
667 *  an asynchronous trap.  This will avoid the executive changing the return
668 *  address.
669 */
670/* On SPARC v9, there are 512 vectors. The same philosophy applies to
671 * vector installation and use, we just provide a larger table.
672 */
673#define CPU_INTERRUPT_NUMBER_OF_VECTORS     512
674#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023
675
676#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x200
677#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
678#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 512 )
679
680#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 512)
681
682/*
683 *  This is defined if the port has a special way to report the ISR nesting
684 *  level.  Most ports maintain the variable _ISR_Nest_level.
685 */
686
687#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
688
689/*
690 *  Should be large enough to run all tests.  This ensures
691 *  that a "reasonable" small application should not have any problems.
692 *
693 *  This appears to be a fairly generous number for the SPARC since
694 *  represents a call depth of about 20 routines based on the minimum
695 *  stack frame.
696 */
697
698#define CPU_STACK_MINIMUM_SIZE  (1024*8)
699
700/*
701 *  CPU's worst alignment requirement for data types on a byte boundary.  This
702 *  alignment does not take into account the requirements for the stack.
703 *
704 *  On the SPARC, this is required for double word loads and stores.
705 *
706 *  Note: quad-word loads/stores need alignment of 16, but currently supported
707 *  architectures do not provide HW implemented quad-word operations.
708 */
709
710#define CPU_ALIGNMENT      8
711
712/*
713 *  This number corresponds to the byte alignment requirement for the
714 *  heap handler.  This alignment requirement may be stricter than that
715 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
716 *  common for the heap to follow the same alignment requirement as
717 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
718 *  then this should be set to CPU_ALIGNMENT.
719 *
720 *  NOTE:  This does not have to be a power of 2.  It does have to
721 *         be greater or equal to than CPU_ALIGNMENT.
722 */
723
724#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
725
726/*
727 *  This number corresponds to the byte alignment requirement for memory
728 *  buffers allocated by the partition manager.  This alignment requirement
729 *  may be stricter than that for the data types alignment specified by
730 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
731 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
732 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
733 *
734 *  NOTE:  This does not have to be a power of 2.  It does have to
735 *         be greater or equal to than CPU_ALIGNMENT.
736 */
737
738#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
739
740/*
741 *  This number corresponds to the byte alignment requirement for the
742 *  stack.  This alignment requirement may be stricter than that for the
743 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
744 *  is strict enough for the stack, then this should be set to 0.
745 *
746 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
747 *
748 *  The alignment restrictions for the SPARC are not that strict but this
749 *  should unsure that the stack is always sufficiently alignment that the
750 *  window overflow, underflow, and flush routines can use double word loads
751 *  and stores.
752 */
753
754#define CPU_STACK_ALIGNMENT        16
755
756#ifndef ASM
757
758/*
759 *  ISR handler macros
760 */
761
762/*
763 *  Support routine to initialize the RTEMS vector table after it is allocated.
764 */
765
766#define _CPU_Initialize_vectors()
767
768/*
769 *  Disable all interrupts for a critical section.  The previous
770 *  level is returned in _level.
771 */
772
773 #define _CPU_ISR_Disable( _level ) \
774  (_level) = sparc_disable_interrupts()
775
776/*
777 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
778 *  This indicates the end of a critical section.  The parameter
779 *  _level is not modified.
780 */
781
782#define _CPU_ISR_Enable( _level ) \
783  sparc_enable_interrupts( _level )
784
785/*
786 *  This temporarily restores the interrupt to _level before immediately
787 *  disabling them again.  This is used to divide long critical
788 *  sections into two or more parts.  The parameter _level is not
789 *  modified.
790 */
791
792#define _CPU_ISR_Flash( _level ) \
793   sparc_flash_interrupts( _level )
794
795/*
796 *  Map interrupt level in task mode onto the hardware that the CPU
797 *  actually provides.  Currently, interrupt levels which do not
798 *  map onto the CPU in a straight fashion are undefined. 
799 */
800
801#define _CPU_ISR_Set_level( _newlevel ) \
802   sparc_enable_interrupts( _newlevel)
803
804uint32_t   _CPU_ISR_Get_level( void );
805 
806/* end of ISR handler macros */
807
808/* Context handler macros */
809
810/*
811 *  Initialize the context to a state suitable for starting a
812 *  task after a context restore operation.  Generally, this
813 *  involves:
814 *
815 *     - setting a starting address
816 *     - preparing the stack
817 *     - preparing the stack and frame pointers
818 *     - setting the proper interrupt level in the context
819 *     - initializing the floating point context
820 *
821 *  NOTE:  Implemented as a subroutine for the SPARC port.
822 */
823
824void _CPU_Context_Initialize(
825  Context_Control  *the_context,
826  void         *stack_base,
827  uint32_t          size,
828  uint32_t          new_level,
829  void             *entry_point,
830  bool              is_fp
831);
832
833/*
834 *  This macro is invoked from _Thread_Handler to do whatever CPU
835 *  specific magic is required that must be done in the context of
836 *  the thread when it starts.
837 *
838 *  On the SPARC, this is setting the frame pointer so GDB is happy.
839 *  Make GDB stop unwinding at _Thread_Handler, previous register window
840 *  Frame pointer is 0 and calling address must be a function with starting
841 *  with a SAVE instruction. If return address is leaf-function (no SAVE)
842 *  GDB will not look at prev reg window fp.
843 *
844 *  _Thread_Handler is known to start with SAVE.
845 */
846
847#define _CPU_Context_Initialization_at_thread_begin() \
848  do { \
849    asm volatile ("set _Thread_Handler,%%i7\n"::); \
850  } while (0)
851
852/*
853 *  This routine is responsible for somehow restarting the currently
854 *  executing task. 
855 *
856 *  On the SPARC, this is is relatively painless but requires a small
857 *  amount of wrapper code before using the regular restore code in
858 *  of the context switch.
859 */
860
861#define _CPU_Context_Restart_self( _the_context ) \
862   _CPU_Context_restore( (_the_context) );
863
864/*
865 *  The FP context area for the SPARC is a simple structure and nothing
866 *  special is required to find the "starting load point"
867 */
868
869#define _CPU_Context_Fp_start( _base, _offset ) \
870   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
871
872/*
873 *  This routine initializes the FP context area passed to it to.
874 *
875 *  The SPARC allows us to use the simple initialization model
876 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
877 *  at CPU initialization and it is simply copied into the destination
878 *  context.
879 */
880
881#define _CPU_Context_Initialize_fp( _destination ) \
882  do { \
883   *(*(_destination)) = _CPU_Null_fp_context; \
884  } while (0)
885
886/* end of Context handler macros */
887
888/* Fatal Error manager macros */
889
890/*
891 *  This routine copies _error into a known place -- typically a stack
892 *  location or a register, optionally disables interrupts, and
893 *  halts/stops the CPU.
894 */
895
896#define _CPU_Fatal_halt( _error ) \
897  do { \
898    uint32_t   level; \
899    \
900    level = sparc_disable_interrupts(); \
901    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
902    while (1); /* loop forever */ \
903  } while (0)
904
905/* end of Fatal Error manager macros */
906
907/* Bitfield handler macros */
908
909/*
910 *  The SPARC port uses the generic C algorithm for bitfield scan if the
911 *  CPU model does not have a scan instruction.
912 */
913
914#if ( SPARC_HAS_BITSCAN == 0 )
915#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
916#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
917#else
918#error "scan instruction not currently supported by RTEMS!!"
919#endif
920
921/* end of Bitfield handler macros */
922
923/* Priority handler handler macros */
924
925/*
926 *  The SPARC port uses the generic C algorithm for bitfield scan if the
927 *  CPU model does not have a scan instruction.
928 */
929
930#if ( SPARC_HAS_BITSCAN == 1 )
931#error "scan instruction not currently supported by RTEMS!!"
932#endif
933
934/* end of Priority handler macros */
935
936/* functions */
937
938/*
939 *  _CPU_Initialize
940 *
941 *  This routine performs CPU dependent initialization.
942 */
943
944void _CPU_Initialize(void);
945
946/*
947 *  _CPU_ISR_install_raw_handler
948 *
949 *  This routine installs new_handler to be directly called from the trap
950 *  table.
951 */
952 
953void _CPU_ISR_install_raw_handler(
954  uint32_t    vector,
955  proc_ptr    new_handler,
956  proc_ptr   *old_handler
957);
958
959/*
960 *  _CPU_ISR_install_vector
961 *
962 *  This routine installs an interrupt vector.
963 */
964
965void _CPU_ISR_install_vector(
966  uint64_t    vector,
967  proc_ptr    new_handler,
968  proc_ptr   *old_handler
969);
970
971#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
972 
973/*
974 *  _CPU_Thread_Idle_body
975 *
976 *  Some SPARC implementations have low power, sleep, or idle modes.  This
977 *  tries to take advantage of those models.
978 */
979 
980void *_CPU_Thread_Idle_body( uintptr_t ignored );
981
982#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
983
984/*
985 *  _CPU_Context_switch
986 *
987 *  This routine switches from the run context to the heir context.
988 */
989
990void _CPU_Context_switch(
991  Context_Control  *run,
992  Context_Control  *heir
993);
994
995/*
996 *  _CPU_Context_restore
997 *
998 *  This routine is generally used only to restart self in an
999 *  efficient manner.
1000 */
1001
1002void _CPU_Context_restore(
1003  Context_Control *new_context
1004);
1005
1006/*
1007 *  _CPU_Context_save_fp
1008 *
1009 *  This routine saves the floating point context passed to it.
1010 */
1011
1012void _CPU_Context_save_fp(
1013  Context_Control_fp **fp_context_ptr
1014);
1015
1016/*
1017 *  _CPU_Context_restore_fp
1018 *
1019 *  This routine restores the floating point context passed to it.
1020 */
1021
1022void _CPU_Context_restore_fp(
1023  Context_Control_fp **fp_context_ptr
1024);
1025
1026/*
1027 *  CPU_swap_u32
1028 *
1029 *  The following routine swaps the endian format of an unsigned int.
1030 *  It must be static because it is referenced indirectly.
1031 *
1032 *  This version will work on any processor, but if you come across a better
1033 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
1034 *  entity as shown below is not any more efficient on the SPARC.
1035 *
1036 *     swap least significant two bytes with 16-bit rotate
1037 *     swap upper and lower 16-bits
1038 *     swap most significant two bytes with 16-bit rotate
1039 *
1040 *  It is not obvious how the SPARC can do significantly better than the
1041 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
1042 *  following code at optimization level four (i.e. -O4).
1043 */
1044 
1045static inline uint32_t CPU_swap_u32(
1046  uint32_t value
1047)
1048{
1049  uint32_t   byte1, byte2, byte3, byte4, swapped;
1050 
1051  byte4 = (value >> 24) & 0xff;
1052  byte3 = (value >> 16) & 0xff;
1053  byte2 = (value >> 8)  & 0xff;
1054  byte1 =  value        & 0xff;
1055 
1056  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1057  return( swapped );
1058}
1059
1060#define CPU_swap_u16( value ) \
1061  (((value&0xff) << 8) | ((value >> 8)&0xff))
1062
1063#endif /* ASM */
1064
1065#ifdef __cplusplus
1066}
1067#endif
1068
1069#endif
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