source: rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h @ a0c79c1f

5
Last change on this file since a0c79c1f was a0c79c1f, checked in by Sebastian Huber <sebastian.huber@…>, on 01/25/16 at 08:36:50

sparc64: No explicit align of _CPU_Null_fp_context

This structure is not performance critical.

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1/**
2 * @file
3 *
4 * @brief SPARC64 CPU Department Source
5 *
6 * This include file contains information pertaining to the port of
7 * the executive to the SPARC64 processor.
8 */
9
10/*
11 *
12 *
13 *  COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR).
14 *
15 *  This file is based on the SPARC cpu.h file. Modifications are made
16 *  to support the SPARC64 processor.
17 *  COPYRIGHT (c) 2010. Gedare Bloom.
18 *
19 *  The license and distribution terms for this file may be
20 *  found in the file LICENSE in this distribution or at
21 *  http://www.rtems.org/license/LICENSE.
22 */
23
24#ifndef _RTEMS_SCORE_CPU_H
25#define _RTEMS_SCORE_CPU_H
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31#include <rtems/score/types.h>
32#include <rtems/score/sparc64.h>
33
34/* conditional compilation parameters */
35
36/*
37 *  Should the calls to _Thread_Enable_dispatch be inlined?
38 *
39 *  If TRUE, then they are inlined.
40 *  If FALSE, then a subroutine call is made.
41 */
42
43#define CPU_INLINE_ENABLE_DISPATCH       TRUE
44
45/*
46 *  Does the executive manage a dedicated interrupt stack in software?
47 *
48 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
49 *  If FALSE, nothing is done.
50 *
51 *  The SPARC does not have a dedicated HW interrupt stack and one has
52 *  been implemented in SW.
53 */
54
55#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
56
57/*
58 *  Does the CPU follow the simple vectored interrupt model?
59 *
60 *  If TRUE, then RTEMS allocates the vector table it internally manages.
61 *  If FALSE, then the BSP is assumed to allocate and manage the vector
62 *  table
63 *
64 *  SPARC Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
69
70/*
71 *  Does this CPU have hardware support for a dedicated interrupt stack?
72 *
73 *  If TRUE, then it must be installed during initialization.
74 *  If FALSE, then no installation is performed.
75 *
76 *  The SPARC does not have a dedicated HW interrupt stack.
77 */
78
79#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
80
81/*
82 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
83 *
84 *  If TRUE, then the memory is allocated during initialization.
85 *  If FALSE, then the memory is allocated during initialization.
86 */
87
88#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
89
90/*
91 *  Does the RTEMS invoke the user's ISR with the vector number and
92 *  a pointer to the saved interrupt frame (1) or just the vector
93 *  number (0)?
94 */
95
96#define CPU_ISR_PASSES_FRAME_POINTER 0
97
98/*
99 *  Does the CPU have hardware floating point?
100 *
101 *  If TRUE, then the FLOATING_POINT task attribute is supported.
102 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
103 */
104
105#if ( SPARC_HAS_FPU == 1 )
106#define CPU_HARDWARE_FP     TRUE
107#else
108#define CPU_HARDWARE_FP     FALSE
109#endif
110#define CPU_SOFTWARE_FP     FALSE
111
112/*
113 *  Are all tasks FLOATING_POINT tasks implicitly?
114 *
115 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
116 *  If FALSE, then the FLOATING_POINT task attribute is followed.
117 */
118
119#define CPU_ALL_TASKS_ARE_FP     FALSE
120
121/*
122 *  Should the IDLE task have a floating point context?
123 *
124 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
125 *  and it has a floating point context which is switched in and out.
126 *  If FALSE, then the IDLE task does not have a floating point context.
127 */
128
129#define CPU_IDLE_TASK_IS_FP      FALSE
130
131/*
132 *  Should the saving of the floating point registers be deferred
133 *  until a context switch is made to another different floating point
134 *  task?
135 *
136 *  If TRUE, then the floating point context will not be stored until
137 *  necessary.  It will remain in the floating point registers and not
138 *  disturned until another floating point task is switched to.
139 *
140 *  If FALSE, then the floating point context is saved when a floating
141 *  point task is switched out and restored when the next floating point
142 *  task is restored.  The state of the floating point registers between
143 *  those two operations is not specified.
144 */
145
146#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
147
148/*
149 *  Does this port provide a CPU dependent IDLE task implementation?
150 *
151 *  If TRUE, then the routine _CPU_Thread_Idle_body
152 *  must be provided and is the default IDLE thread body instead of
153 *  _CPU_Thread_Idle_body.
154 *
155 *  If FALSE, then use the generic IDLE thread body if the BSP does
156 *  not provide one.
157 */
158
159#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
160
161/*
162 *  Does the stack grow up (toward higher addresses) or down
163 *  (toward lower addresses)?
164 *
165 *  If TRUE, then the grows upward.
166 *  If FALSE, then the grows toward smaller addresses.
167 *
168 *  The stack grows to lower addresses on the SPARC.
169 */
170
171#define CPU_STACK_GROWS_UP               FALSE
172
173/*
174 *  The following is the variable attribute used to force alignment
175 *  of critical data structures.  On some processors it may make
176 *  sense to have these aligned on tighter boundaries than
177 *  the minimum requirements of the compiler in order to have as
178 *  much of the critical data area as possible in a cache line.
179 *
180 *  The SPARC does not appear to have particularly strict alignment
181 *  requirements.  This value (16) was chosen to take advantages of caches.
182 *
183 *  SPARC 64 requirements on floating point alignment is at least 8,
184 *  and is 16 if quad-word fp instructions are available (e.g. LDQF).
185 */
186
187#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
188
189/*
190 *  Define what is required to specify how the network to host conversion
191 *  routines are handled.
192 */
193
194#define CPU_BIG_ENDIAN                           TRUE
195#define CPU_LITTLE_ENDIAN                        FALSE
196
197/*
198 *  The following defines the number of bits actually used in the
199 *  interrupt field of the task mode.  How those bits map to the
200 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
201 *
202 *  The SPARC v9 has 16 interrupt levels in the PIL field of the PSR.
203 */
204
205#define CPU_MODES_INTERRUPT_MASK   0x0000000F
206
207#define CPU_PER_CPU_CONTROL_SIZE 0
208
209/*
210 *  This structure represents the organization of the minimum stack frame
211 *  for the SPARC.  More framing information is required in certain situaions
212 *  such as when there are a large number of out parameters or when the callee
213 *  must save floating point registers.
214 */
215
216#ifndef ASM
217
218typedef struct {
219  /* There is no CPU specific per-CPU state */
220} CPU_Per_CPU_control;
221
222typedef struct {
223  uint64_t    l0;
224  uint64_t    l1;
225  uint64_t    l2;
226  uint64_t    l3;
227  uint64_t    l4;
228  uint64_t    l5;
229  uint64_t    l6;
230  uint64_t    l7;
231  uint64_t    i0;
232  uint64_t    i1;
233  uint64_t    i2;
234  uint64_t    i3;
235  uint64_t    i4;
236  uint64_t    i5;
237  uint64_t    i6_fp;
238  uint64_t    i7;
239  void       *structure_return_address;
240  /*
241   *  The following are for the callee to save the register arguments in
242   *  should this be necessary.
243   */
244  uint64_t    saved_arg0;
245  uint64_t    saved_arg1;
246  uint64_t    saved_arg2;
247  uint64_t    saved_arg3;
248  uint64_t    saved_arg4;
249  uint64_t    saved_arg5;
250  uint64_t    pad0;
251}  CPU_Minimum_stack_frame;
252
253#endif /* !ASM */
254
255#define CPU_STACK_FRAME_L0_OFFSET             0x00
256#define CPU_STACK_FRAME_L1_OFFSET             0x08
257#define CPU_STACK_FRAME_L2_OFFSET             0x10
258#define CPU_STACK_FRAME_L3_OFFSET             0x18
259#define CPU_STACK_FRAME_L4_OFFSET             0x20
260#define CPU_STACK_FRAME_L5_OFFSET             0x28
261#define CPU_STACK_FRAME_L6_OFFSET             0x30
262#define CPU_STACK_FRAME_L7_OFFSET             0x38
263#define CPU_STACK_FRAME_I0_OFFSET             0x40
264#define CPU_STACK_FRAME_I1_OFFSET             0x48
265#define CPU_STACK_FRAME_I2_OFFSET             0x50
266#define CPU_STACK_FRAME_I3_OFFSET             0x58
267#define CPU_STACK_FRAME_I4_OFFSET             0x60
268#define CPU_STACK_FRAME_I5_OFFSET             0x68
269#define CPU_STACK_FRAME_I6_FP_OFFSET          0x70
270#define CPU_STACK_FRAME_I7_OFFSET             0x78
271#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x80
272#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x88
273#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x90
274#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x98
275#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0xA0
276#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0xA8
277#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0xB0
278#define CPU_STACK_FRAME_PAD0_OFFSET           0xB8
279
280#define CPU_MINIMUM_STACK_FRAME_SIZE          0xC0
281
282/*
283 * Contexts
284 *
285 *  Generally there are 2 types of context to save.
286 *     1. Interrupt registers to save
287 *     2. Task level registers to save
288 *
289 *  This means we have the following 3 context items:
290 *     1. task level context stuff::  Context_Control
291 *     2. floating point task stuff:: Context_Control_fp
292 *     3. special interrupt level context :: Context_Control_interrupt
293 *
294 *  On the SPARC, we are relatively conservative in that we save most
295 *  of the CPU state in the context area.  The ET (enable trap) bit and
296 *  the CWP (current window pointer) fields of the PSR are considered
297 *  system wide resources and are not maintained on a per-thread basis.
298 */
299
300#ifndef ASM
301
302typedef struct {
303    uint64_t   g1;
304    uint64_t   g2;
305    uint64_t   g3;
306    uint64_t   g4;
307    uint64_t   g5;
308    uint64_t   g6;
309    uint64_t   g7;
310
311    uint64_t   l0;
312    uint64_t   l1;
313    uint64_t   l2;
314    uint64_t   l3;
315    uint64_t   l4;
316    uint64_t   l5;
317    uint64_t   l6;
318    uint64_t   l7;
319
320    uint64_t   i0;
321    uint64_t   i1;
322    uint64_t   i2;
323    uint64_t   i3;
324    uint64_t   i4;
325    uint64_t   i5;
326    uint64_t   i6_fp;
327    uint64_t   i7;
328
329    uint64_t   o0;
330    uint64_t   o1;
331    uint64_t   o2;
332    uint64_t   o3;
333    uint64_t   o4;
334    uint64_t   o5;
335    uint64_t   o6_sp;
336    uint64_t   o7;
337
338    uint32_t   isr_dispatch_disable;
339    uint32_t   pad;
340} Context_Control;
341
342#define _CPU_Context_Get_SP( _context ) \
343  (_context)->o6_sp
344
345#endif /* ASM */
346
347/*
348 *  Offsets of fields with Context_Control for assembly routines.
349 */
350
351#define G1_OFFSET    0x00
352#define G2_OFFSET    0x08
353#define G3_OFFSET    0x10
354#define G4_OFFSET    0x18
355#define G5_OFFSET    0x20
356#define G6_OFFSET    0x28
357#define G7_OFFSET    0x30
358
359#define L0_OFFSET    0x38
360#define L1_OFFSET    0x40
361#define L2_OFFSET    0x48
362#define L3_OFFSET    0x50
363#define L4_OFFSET    0x58
364#define L5_OFFSET    0x60
365#define L6_OFFSET    0x68
366#define L7_OFFSET    0x70
367
368#define I0_OFFSET    0x78
369#define I1_OFFSET    0x80
370#define I2_OFFSET    0x88
371#define I3_OFFSET    0x90
372#define I4_OFFSET    0x98
373#define I5_OFFSET    0xA0
374#define I6_FP_OFFSET    0xA8
375#define I7_OFFSET 0xB0
376
377#define O0_OFFSET    0xB8
378#define O1_OFFSET    0xC0
379#define O2_OFFSET    0xC8
380#define O3_OFFSET    0xD0
381#define O4_OFFSET    0xD8
382#define O5_OFFSET    0xE0
383#define O6_SP_OFFSET    0xE8
384#define O7_OFFSET 0xF0
385
386#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8
387#define ISR_PAD_OFFSET 0xFC
388
389/*
390 *  The floating point context area.
391 */
392
393#ifndef ASM
394
395typedef struct {
396    double      f0;     /* f0-f1 */
397    double      f2;     /* f2-f3 */
398    double      f4;     /* f4-f5 */
399    double      f6;     /* f6-f7 */
400    double      f8;     /* f8-f9 */
401    double      f10;    /* f10-f11 */
402    double      f12;    /* f12-f13 */
403    double      f14;    /* f14-f15 */
404    double      f16;    /* f16-f17 */
405    double      f18;    /* f18-f19 */
406    double      f20;    /* f20-f21 */
407    double      f22;    /* f22-f23 */
408    double      f24;    /* f24-f25 */
409    double      f26;    /* f26-f27 */
410    double      f28;    /* f28-f29 */
411    double      f30;    /* f30-f31 */
412    double      f32;
413    double      f34;
414    double      f36;
415    double      f38;
416    double      f40;
417    double      f42;
418    double      f44;
419    double      f46;
420    double      f48;
421    double      f50;
422    double      f52;
423    double      f54;
424    double      f56;
425    double      f58;
426    double      f60;
427    double      f62;
428    uint64_t    fsr;
429} Context_Control_fp;
430
431#endif /* !ASM */
432
433/*
434 *  Offsets of fields with Context_Control_fp for assembly routines.
435 */
436
437#define FO_OFFSET    0x00
438#define F2_OFFSET    0x08
439#define F4_OFFSET    0x10
440#define F6_OFFSET    0x18
441#define F8_OFFSET    0x20
442#define F1O_OFFSET   0x28
443#define F12_OFFSET   0x30
444#define F14_OFFSET   0x38
445#define F16_OFFSET   0x40
446#define F18_OFFSET   0x48
447#define F2O_OFFSET   0x50
448#define F22_OFFSET   0x58
449#define F24_OFFSET   0x60
450#define F26_OFFSET   0x68
451#define F28_OFFSET   0x70
452#define F3O_OFFSET   0x78
453#define F32_OFFSET   0x80
454#define F34_OFFSET   0x88
455#define F36_OFFSET   0x90
456#define F38_OFFSET   0x98
457#define F4O_OFFSET   0xA0
458#define F42_OFFSET   0xA8
459#define F44_OFFSET   0xB0
460#define F46_OFFSET   0xB8
461#define F48_OFFSET   0xC0
462#define F5O_OFFSET   0xC8
463#define F52_OFFSET   0xD0
464#define F54_OFFSET   0xD8
465#define F56_OFFSET   0xE0
466#define F58_OFFSET   0xE8
467#define F6O_OFFSET   0xF0
468#define F62_OFFSET   0xF8
469#define FSR_OFFSET   0x100
470
471#define CONTEXT_CONTROL_FP_SIZE 0x108
472
473#ifndef ASM
474
475/*
476 *  Context saved on stack for an interrupt.
477 *
478 *  NOTE:  The tstate, tpc, and tnpc are saved in this structure
479 *         to allow resetting the TL while still being able to return
480 *         from a trap later.  The PIL is saved because
481 *         if this is an external interrupt, we will mask lower
482 *         priority interrupts until finishing. Even though the y register
483 *         is deprecated, gcc still uses it.
484 */
485
486typedef struct {
487  CPU_Minimum_stack_frame  Stack_frame;
488  uint64_t                 tstate;
489  uint64_t                 tpc;
490  uint64_t                 tnpc;
491  uint64_t                 pil;
492  uint64_t                 y;
493  uint64_t                 g1;
494  uint64_t                 g2;
495  uint64_t                 g3;
496  uint64_t                 g4;
497  uint64_t                 g5;
498  uint64_t                 g6;
499  uint64_t                 g7;
500  uint64_t                 o0;
501  uint64_t                 o1;
502  uint64_t                 o2;
503  uint64_t                 o3;
504  uint64_t                 o4;
505  uint64_t                 o5;
506  uint64_t                 o6_sp;
507  uint64_t                 o7;
508  uint64_t                 tvec;
509} CPU_Interrupt_frame;
510
511#endif /* ASM */
512
513/*
514 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
515 */
516
517#define ISF_TSTATE_OFFSET      CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
518#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
519#define ISF_TNPC_OFFSET        CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
520#define ISF_PIL_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
521#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
522#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
523#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
524#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
525#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
526#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
527#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
528#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x58
529#define ISF_O0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x60
530#define ISF_O1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x68
531#define ISF_O2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x70
532#define ISF_O3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x78
533#define ISF_O4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x80
534#define ISF_O5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x88
535#define ISF_O6_SP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x90
536#define ISF_O7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x98
537#define ISF_TVEC_OFFSET        CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0
538
539#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8
540#ifndef ASM
541/*
542 *  This variable is contains the initialize context for the FP unit.
543 *  It is filled in by _CPU_Initialize and copied into the task's FP
544 *  context area during _CPU_Context_Initialize.
545 */
546
547SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
548
549/*
550 *  This flag is context switched with each thread.  It indicates
551 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
552 *  By using this flag, we can avoid nesting more interrupt dispatching
553 *  attempts on a previously interrupted thread's stack.
554 */
555
556SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
557
558/*
559 *  The following type defines an entry in the SPARC's trap table.
560 *
561 *  NOTE: The instructions chosen are RTEMS dependent although one is
562 *        obligated to use two of the four instructions to perform a
563 *        long jump.  The other instructions load one register with the
564 *        trap type (a.k.a. vector) and another with the psr.
565 */
566/* For SPARC V9, we must use 6 of these instructions to perform a long
567 * jump, because the _handler value is now 64-bits. We also need to store
568 * temporary values in the global register set at this trap level. Because
569 * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3
570 * to pass parameters to ISR_Handler.
571 *
572 * The instruction sequence is now more like:
573 *      rdpr %tstate, %g4
574 *      setx _handler, %g2, %g3
575 *      jmp %g3+0
576 *      mov _vector, %g2
577 */
578typedef struct {
579  uint32_t     rdpr_tstate_g4;                  /* rdpr  %tstate, %g4        */
580  uint32_t     sethi_of_hh_handler_to_g2;       /* sethi %hh(_handler), %g2  */
581  uint32_t     or_g2_hm_handler_to_g2;          /* or %l3, %hm(_handler), %g2 */
582  uint32_t     sllx_g2_by_32_to_g2;             /* sllx   %g2, 32, %g2 */
583  uint32_t     sethi_of_handler_to_g3;          /* sethi %hi(_handler), %g3  */
584  uint32_t     or_g3_g2_to_g3;                  /* or     %g3, %g2, %g3 */
585  uint32_t     jmp_to_low_of_handler_plus_g3;   /* jmp   %g3 + %lo(_handler) */
586  uint32_t     mov_vector_g2;                   /* mov   _vector, %g2        */
587} CPU_Trap_table_entry;
588
589/*
590 *  This is the set of opcodes for the instructions loaded into a trap
591 *  table entry.  The routine which installs a handler is responsible
592 *  for filling in the fields for the _handler address and the _vector
593 *  trap type.
594 *
595 *  The constants following this structure are masks for the fields which
596 *  must be filled in when the handler is installed.
597 */
598
599extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
600
601/*
602 *  The size of the floating point context area.
603 */
604
605#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
606
607#endif
608
609/*
610 *  Amount of extra stack (above minimum stack size) required by
611 *  MPCI receive server thread.  Remember that in a multiprocessor
612 *  system this thread must exist and be able to process all directives.
613 */
614
615#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
616
617/*
618 *  This defines the number of entries in the ISR_Vector_table managed
619 *  by the executive.
620 *
621 *  On the SPARC, there are really only 256 vectors.  However, the executive
622 *  has no easy, fast, reliable way to determine which traps are synchronous
623 *  and which are asynchronous.  By default, synchronous traps return to the
624 *  instruction which caused the interrupt.  So if you install a software
625 *  trap handler as an executive interrupt handler (which is desirable since
626 *  RTEMS takes care of window and register issues), then the executive needs
627 *  to know that the return address is to the trap rather than the instruction
628 *  following the trap.
629 *
630 *  So vectors 0 through 255 are treated as regular asynchronous traps which
631 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
632 *  by the executive to be synchronous and to require that the return address
633 *  be fudged.
634 *
635 *  If you use this mechanism to install a trap handler which must reexecute
636 *  the instruction which caused the trap, then it should be installed as
637 *  an asynchronous trap.  This will avoid the executive changing the return
638 *  address.
639 */
640/* On SPARC v9, there are 512 vectors. The same philosophy applies to
641 * vector installation and use, we just provide a larger table.
642 */
643#define CPU_INTERRUPT_NUMBER_OF_VECTORS     512
644#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023
645
646#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x200
647#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
648#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 512 )
649
650#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 512)
651
652/*
653 *  This is defined if the port has a special way to report the ISR nesting
654 *  level.  Most ports maintain the variable _ISR_Nest_level.
655 */
656
657#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
658
659/*
660 *  Should be large enough to run all tests.  This ensures
661 *  that a "reasonable" small application should not have any problems.
662 *
663 *  This appears to be a fairly generous number for the SPARC since
664 *  represents a call depth of about 20 routines based on the minimum
665 *  stack frame.
666 */
667
668#define CPU_STACK_MINIMUM_SIZE  (1024*8)
669
670#define CPU_SIZEOF_POINTER 8
671
672/*
673 *  CPU's worst alignment requirement for data types on a byte boundary.  This
674 *  alignment does not take into account the requirements for the stack.
675 *
676 *  On the SPARC, this is required for double word loads and stores.
677 *
678 *  Note: quad-word loads/stores need alignment of 16, but currently supported
679 *  architectures do not provide HW implemented quad-word operations.
680 */
681
682#define CPU_ALIGNMENT      8
683
684/*
685 *  This number corresponds to the byte alignment requirement for the
686 *  heap handler.  This alignment requirement may be stricter than that
687 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
688 *  common for the heap to follow the same alignment requirement as
689 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
690 *  then this should be set to CPU_ALIGNMENT.
691 *
692 *  NOTE:  This does not have to be a power of 2.  It does have to
693 *         be greater or equal to than CPU_ALIGNMENT.
694 */
695
696#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
697
698/*
699 *  This number corresponds to the byte alignment requirement for memory
700 *  buffers allocated by the partition manager.  This alignment requirement
701 *  may be stricter than that for the data types alignment specified by
702 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
703 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
704 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
705 *
706 *  NOTE:  This does not have to be a power of 2.  It does have to
707 *         be greater or equal to than CPU_ALIGNMENT.
708 */
709
710#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
711
712/*
713 *  This number corresponds to the byte alignment requirement for the
714 *  stack.  This alignment requirement may be stricter than that for the
715 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
716 *  is strict enough for the stack, then this should be set to 0.
717 *
718 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
719 *
720 *  The alignment restrictions for the SPARC are not that strict but this
721 *  should unsure that the stack is always sufficiently alignment that the
722 *  window overflow, underflow, and flush routines can use double word loads
723 *  and stores.
724 */
725
726#define CPU_STACK_ALIGNMENT        16
727
728#ifndef ASM
729
730/*
731 *  ISR handler macros
732 */
733
734/*
735 *  Support routine to initialize the RTEMS vector table after it is allocated.
736 */
737
738#define _CPU_Initialize_vectors()
739
740/*
741 *  Disable all interrupts for a critical section.  The previous
742 *  level is returned in _level.
743 */
744
745 #define _CPU_ISR_Disable( _level ) \
746  (_level) = sparc_disable_interrupts()
747
748/*
749 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
750 *  This indicates the end of a critical section.  The parameter
751 *  _level is not modified.
752 */
753
754#define _CPU_ISR_Enable( _level ) \
755  sparc_enable_interrupts( _level )
756
757/*
758 *  This temporarily restores the interrupt to _level before immediately
759 *  disabling them again.  This is used to divide long critical
760 *  sections into two or more parts.  The parameter _level is not
761 *  modified.
762 */
763
764#define _CPU_ISR_Flash( _level ) \
765   sparc_flash_interrupts( _level )
766
767/*
768 *  Map interrupt level in task mode onto the hardware that the CPU
769 *  actually provides.  Currently, interrupt levels which do not
770 *  map onto the CPU in a straight fashion are undefined.
771 */
772
773#define _CPU_ISR_Set_level( _newlevel ) \
774   sparc_enable_interrupts( _newlevel)
775
776uint32_t   _CPU_ISR_Get_level( void );
777
778/* end of ISR handler macros */
779
780/* Context handler macros */
781
782/*
783 *  Initialize the context to a state suitable for starting a
784 *  task after a context restore operation.  Generally, this
785 *  involves:
786 *
787 *     - setting a starting address
788 *     - preparing the stack
789 *     - preparing the stack and frame pointers
790 *     - setting the proper interrupt level in the context
791 *     - initializing the floating point context
792 *
793 *  NOTE:  Implemented as a subroutine for the SPARC port.
794 */
795
796void _CPU_Context_Initialize(
797  Context_Control  *the_context,
798  void         *stack_base,
799  uint32_t          size,
800  uint32_t          new_level,
801  void             *entry_point,
802  bool              is_fp,
803  void             *tls_area
804);
805
806/*
807 *  This macro is invoked from _Thread_Handler to do whatever CPU
808 *  specific magic is required that must be done in the context of
809 *  the thread when it starts.
810 *
811 *  On the SPARC, this is setting the frame pointer so GDB is happy.
812 *  Make GDB stop unwinding at _Thread_Handler, previous register window
813 *  Frame pointer is 0 and calling address must be a function with starting
814 *  with a SAVE instruction. If return address is leaf-function (no SAVE)
815 *  GDB will not look at prev reg window fp.
816 *
817 *  _Thread_Handler is known to start with SAVE.
818 */
819
820#define _CPU_Context_Initialization_at_thread_begin() \
821  do { \
822    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
823  } while (0)
824
825/*
826 *  This routine is responsible for somehow restarting the currently
827 *  executing task.
828 *
829 *  On the SPARC, this is is relatively painless but requires a small
830 *  amount of wrapper code before using the regular restore code in
831 *  of the context switch.
832 */
833
834#define _CPU_Context_Restart_self( _the_context ) \
835   _CPU_Context_restore( (_the_context) );
836
837/*
838 *  The FP context area for the SPARC is a simple structure and nothing
839 *  special is required to find the "starting load point"
840 */
841
842#define _CPU_Context_Fp_start( _base, _offset ) \
843   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
844
845/*
846 *  This routine initializes the FP context area passed to it to.
847 *
848 *  The SPARC allows us to use the simple initialization model
849 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
850 *  at CPU initialization and it is simply copied into the destination
851 *  context.
852 */
853
854#define _CPU_Context_Initialize_fp( _destination ) \
855  do { \
856   *(*(_destination)) = _CPU_Null_fp_context; \
857  } while (0)
858
859/* end of Context handler macros */
860
861/* Fatal Error manager macros */
862
863/*
864 *  This routine copies _error into a known place -- typically a stack
865 *  location or a register, optionally disables interrupts, and
866 *  halts/stops the CPU.
867 */
868
869#define _CPU_Fatal_halt( _source, _error ) \
870  do { \
871    uint32_t   level; \
872    \
873    level = sparc_disable_interrupts(); \
874    __asm__ volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
875    while (1); /* loop forever */ \
876  } while (0)
877
878/* end of Fatal Error manager macros */
879
880/* Bitfield handler macros */
881
882/*
883 *  The SPARC port uses the generic C algorithm for bitfield scan if the
884 *  CPU model does not have a scan instruction.
885 */
886
887#if ( SPARC_HAS_BITSCAN == 0 )
888#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
889#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
890#else
891#error "scan instruction not currently supported by RTEMS!!"
892#endif
893
894/* end of Bitfield handler macros */
895
896/* Priority handler handler macros */
897
898/*
899 *  The SPARC port uses the generic C algorithm for bitfield scan if the
900 *  CPU model does not have a scan instruction.
901 */
902
903#if ( SPARC_HAS_BITSCAN == 1 )
904#error "scan instruction not currently supported by RTEMS!!"
905#endif
906
907/* end of Priority handler macros */
908
909/* functions */
910
911/*
912 *  _CPU_Initialize
913 *
914 *  This routine performs CPU dependent initialization.
915 */
916
917void _CPU_Initialize(void);
918
919/*
920 *  _CPU_ISR_install_raw_handler
921 *
922 *  This routine installs new_handler to be directly called from the trap
923 *  table.
924 */
925
926void _CPU_ISR_install_raw_handler(
927  uint32_t    vector,
928  proc_ptr    new_handler,
929  proc_ptr   *old_handler
930);
931
932/*
933 *  _CPU_ISR_install_vector
934 *
935 *  This routine installs an interrupt vector.
936 */
937
938void _CPU_ISR_install_vector(
939  uint64_t    vector,
940  proc_ptr    new_handler,
941  proc_ptr   *old_handler
942);
943
944#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
945
946/*
947 *  _CPU_Thread_Idle_body
948 *
949 *  Some SPARC implementations have low power, sleep, or idle modes.  This
950 *  tries to take advantage of those models.
951 */
952
953void *_CPU_Thread_Idle_body( uintptr_t ignored );
954
955#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
956
957/*
958 *  _CPU_Context_switch
959 *
960 *  This routine switches from the run context to the heir context.
961 */
962
963void _CPU_Context_switch(
964  Context_Control  *run,
965  Context_Control  *heir
966);
967
968/*
969 *  _CPU_Context_restore
970 *
971 *  This routine is generally used only to restart self in an
972 *  efficient manner.
973 */
974
975void _CPU_Context_restore(
976  Context_Control *new_context
977) RTEMS_NO_RETURN;
978
979/*
980 *  _CPU_Context_save_fp
981 *
982 *  This routine saves the floating point context passed to it.
983 */
984
985void _CPU_Context_save_fp(
986  Context_Control_fp **fp_context_ptr
987);
988
989/*
990 *  _CPU_Context_restore_fp
991 *
992 *  This routine restores the floating point context passed to it.
993 */
994
995void _CPU_Context_restore_fp(
996  Context_Control_fp **fp_context_ptr
997);
998
999static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1000{
1001  /* TODO */
1002}
1003
1004static inline void _CPU_Context_validate( uintptr_t pattern )
1005{
1006  while (1) {
1007    /* TODO */
1008  }
1009}
1010
1011/* FIXME */
1012typedef CPU_Interrupt_frame CPU_Exception_frame;
1013
1014void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1015
1016/*
1017 *  CPU_swap_u32
1018 *
1019 *  The following routine swaps the endian format of an unsigned int.
1020 *  It must be static because it is referenced indirectly.
1021 *
1022 *  This version will work on any processor, but if you come across a better
1023 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
1024 *  entity as shown below is not any more efficient on the SPARC.
1025 *
1026 *     swap least significant two bytes with 16-bit rotate
1027 *     swap upper and lower 16-bits
1028 *     swap most significant two bytes with 16-bit rotate
1029 *
1030 *  It is not obvious how the SPARC can do significantly better than the
1031 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
1032 *  following code at optimization level four (i.e. -O4).
1033 */
1034
1035static inline uint32_t CPU_swap_u32(
1036  uint32_t value
1037)
1038{
1039  uint32_t   byte1, byte2, byte3, byte4, swapped;
1040
1041  byte4 = (value >> 24) & 0xff;
1042  byte3 = (value >> 16) & 0xff;
1043  byte2 = (value >> 8)  & 0xff;
1044  byte1 =  value        & 0xff;
1045
1046  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1047  return( swapped );
1048}
1049
1050#define CPU_swap_u16( value ) \
1051  (((value&0xff) << 8) | ((value >> 8)&0xff))
1052
1053typedef uint32_t CPU_Counter_ticks;
1054
1055CPU_Counter_ticks _CPU_Counter_read( void );
1056
1057static inline CPU_Counter_ticks _CPU_Counter_difference(
1058  CPU_Counter_ticks second,
1059  CPU_Counter_ticks first
1060)
1061{
1062  return second - first;
1063}
1064
1065#endif /* ASM */
1066
1067#ifdef __cplusplus
1068}
1069#endif
1070
1071#endif
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