source: rtems/cpukit/score/cpu/sparc64/cpu.c @ d18560a

5
Last change on this file since d18560a was d18560a, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 11, 2016 at 10:16:33 AM

sparc64: Rename CPU_Minimum_stack_frame

Rename SPARC64-specific CPU_Minimum_stack_frame to
SPARC64_Minimum_stack_frame. Rename SPARC64-specific
CPU_MINIMUM_STACK_FRAME_SIZE to SPARC64_MINIMUM_STACK_FRAME_SIZE.

Update #2809.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief SPARC64 CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR).
9 *
10 *  This file is based on the SPARC cpu.c file. Modifications are made to
11 *  provide support for the SPARC-v9.
12 *  COPYRIGHT (c) 2010. Gedare Bloom.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#include <rtems/system.h>
20#include <rtems/asm.h>
21#include <rtems/score/isr.h>
22#include <rtems/score/tls.h>
23#include <rtems/rtems/cache.h>
24
25#if (SPARC_HAS_FPU == 1)
26Context_Control_fp _CPU_Null_fp_context;
27#endif
28
29volatile uint32_t _CPU_ISR_Dispatch_disable;
30
31/*
32 *  _CPU_Initialize
33 *
34 *  This routine performs processor dependent initialization.
35 *
36 *  INPUT PARAMETERS: NONE
37 *
38 *  Output Parameters: NONE
39 *
40 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
41 *        The SPARC's assembly code can reference it directly with no problems.
42 */
43
44void _CPU_Initialize(void)
45{
46#if (SPARC_HAS_FPU == 1)
47  Context_Control_fp *pointer;
48
49  /*
50   *  This seems to be the most appropriate way to obtain an initial
51   *  FP context on the SPARC.  The NULL fp context is copied in to
52   *  the task's FP context during Context_Initialize_fp.
53   */
54
55  pointer = &_CPU_Null_fp_context;
56  _CPU_Context_save_fp( &pointer );
57
58#endif
59
60  /*
61   *  Since no tasks have been created yet and no interrupts have occurred,
62   *  there is no way that the currently executing thread can have an
63   *  _ISR_Dispatch stack frame on its stack.
64   */
65  _CPU_ISR_Dispatch_disable = 0;
66}
67
68void _CPU_Context_Initialize(
69  Context_Control  *the_context,
70  void         *stack_base,
71  uint32_t          size,
72  uint32_t          new_level,
73  void             *entry_point,
74  bool              is_fp,
75  void             *tls_area
76)
77{
78    uint64_t     stack_high;  /* highest "stack aligned" address */
79
80    /*
81     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
82     *  based on the stack_high address.
83     */
84
85    stack_high = ((uint64_t)(stack_base) + size);
86    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
87
88    /*
89     *  See the README in this directory for a diagram of the stack.
90     */
91
92    the_context->o7    = ((uint64_t) entry_point) - 8;
93    the_context->o6_sp = stack_high - SPARC64_MINIMUM_STACK_FRAME_SIZE - STACK_BIAS;
94    the_context->i6_fp = 0;
95
96    /* ABI uses g4 as segment register, make sure it is zeroed */
97    the_context->g4    = 0;
98
99    /* PSTATE used to be built here, but is no longer included in context */
100
101  /*
102   *  Since THIS thread is being created, there is no way that THIS
103   *  thread can have an _ISR_Dispatch stack frame on its stack.
104   */
105    the_context->isr_dispatch_disable = 0;
106
107  if ( tls_area != NULL ) {
108    void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
109
110    the_context->g7 = (uintptr_t) tcb;
111  }
112}
Note: See TracBrowser for help on using the repository browser.