source: rtems/cpukit/score/cpu/sparc64/cpu.c @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief SPARC64 CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2007.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  This file is based on the SPARC cpu.c file. Modifications are made to
12 *  provide support for the SPARC-v9.
13 *    COPYRIGHT (c) 2010. Gedare Bloom.
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#include <rtems/system.h>
21#include <rtems/asm.h>
22#include <rtems/score/isr.h>
23#include <rtems/score/tls.h>
24#include <rtems/rtems/cache.h>
25
26/*
27 *  _CPU_Initialize
28 *
29 *  This routine performs processor dependent initialization.
30 *
31 *  INPUT PARAMETERS: NONE
32 *
33 *  Output Parameters: NONE
34 *
35 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
36 *        The SPARC's assembly code can reference it directly with no problems.
37 */
38
39void _CPU_Initialize(void)
40{
41#if (SPARC_HAS_FPU == 1)
42  Context_Control_fp *pointer;
43
44  /*
45   *  This seems to be the most appropriate way to obtain an initial
46   *  FP context on the SPARC.  The NULL fp context is copied in to
47   *  the task's FP context during Context_Initialize_fp.
48   */
49
50  pointer = &_CPU_Null_fp_context;
51  _CPU_Context_save_fp( &pointer );
52
53#endif
54
55  /*
56   *  Since no tasks have been created yet and no interrupts have occurred,
57   *  there is no way that the currently executing thread can have an
58   *  _ISR_Dispatch stack frame on its stack.
59   */
60  _CPU_ISR_Dispatch_disable = 0;
61}
62
63void _CPU_Context_Initialize(
64  Context_Control  *the_context,
65  void         *stack_base,
66  uint32_t          size,
67  uint32_t          new_level,
68  void             *entry_point,
69  bool              is_fp,
70  void             *tls_area
71)
72{
73    uint64_t     stack_high;  /* highest "stack aligned" address */
74    uint32_t     the_size;
75
76    /*
77     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
78     *  based on the stack_high address.
79     */
80
81    stack_high = ((uint64_t)(stack_base) + size);
82    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
83
84    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
85
86    /*
87     *  See the README in this directory for a diagram of the stack.
88     */
89
90    the_context->o7    = ((uint64_t) entry_point) - 8;
91    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE - STACK_BIAS;
92    the_context->i6_fp = 0;
93
94    /* ABI uses g4 as segment register, make sure it is zeroed */
95    the_context->g4    = 0;
96
97    /* PSTATE used to be built here, but is no longer included in context */
98
99  /*
100   *  Since THIS thread is being created, there is no way that THIS
101   *  thread can have an _ISR_Dispatch stack frame on its stack.
102   */
103    the_context->isr_dispatch_disable = 0;
104
105  if ( tls_area != NULL ) {
106    void *tcb = _TLS_TCB_after_tls_block_initialize( tls_area );
107
108    the_context->g7 = (uintptr_t) tcb;
109  }
110}
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