1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief SPARC64 CPU Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * This file is based on the SPARC cpu.c file. Modifications are made to |
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11 | * provide support for the SPARC-v9. |
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12 | * COPYRIGHT (c) 2010. Gedare Bloom. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <rtems/system.h> |
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20 | #include <rtems/asm.h> |
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21 | #include <rtems/score/isr.h> |
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22 | #include <rtems/score/tls.h> |
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23 | #include <rtems/rtems/cache.h> |
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24 | |
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25 | #if (SPARC_HAS_FPU == 1) |
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26 | Context_Control_fp _CPU_Null_fp_context; |
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27 | #endif |
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28 | |
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29 | volatile uint32_t _CPU_ISR_Dispatch_disable; |
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30 | |
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31 | /* |
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32 | * _CPU_Initialize |
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33 | * |
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34 | * This routine performs processor dependent initialization. |
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35 | * |
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36 | * INPUT PARAMETERS: NONE |
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37 | * |
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38 | * Output Parameters: NONE |
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39 | * |
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40 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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41 | * The SPARC's assembly code can reference it directly with no problems. |
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42 | */ |
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43 | |
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44 | void _CPU_Initialize(void) |
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45 | { |
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46 | #if (SPARC_HAS_FPU == 1) |
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47 | Context_Control_fp *pointer; |
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48 | |
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49 | /* |
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50 | * This seems to be the most appropriate way to obtain an initial |
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51 | * FP context on the SPARC. The NULL fp context is copied in to |
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52 | * the task's FP context during Context_Initialize_fp. |
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53 | */ |
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54 | |
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55 | pointer = &_CPU_Null_fp_context; |
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56 | _CPU_Context_save_fp( &pointer ); |
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57 | |
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58 | #endif |
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59 | |
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60 | /* |
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61 | * Since no tasks have been created yet and no interrupts have occurred, |
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62 | * there is no way that the currently executing thread can have an |
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63 | * _ISR_Dispatch stack frame on its stack. |
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64 | */ |
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65 | _CPU_ISR_Dispatch_disable = 0; |
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66 | } |
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67 | |
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68 | void _CPU_Context_Initialize( |
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69 | Context_Control *the_context, |
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70 | void *stack_base, |
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71 | uint32_t size, |
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72 | uint32_t new_level, |
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73 | void *entry_point, |
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74 | bool is_fp, |
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75 | void *tls_area |
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76 | ) |
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77 | { |
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78 | uint64_t stack_high; /* highest "stack aligned" address */ |
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79 | |
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80 | /* |
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81 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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82 | * based on the stack_high address. |
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83 | */ |
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84 | |
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85 | stack_high = ((uint64_t)(stack_base) + size); |
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86 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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87 | |
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88 | /* |
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89 | * See the README in this directory for a diagram of the stack. |
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90 | */ |
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91 | |
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92 | the_context->o7 = ((uint64_t) entry_point) - 8; |
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93 | the_context->o6_sp = stack_high - SPARC64_MINIMUM_STACK_FRAME_SIZE - STACK_BIAS; |
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94 | the_context->i6_fp = 0; |
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95 | |
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96 | /* ABI uses g4 as segment register, make sure it is zeroed */ |
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97 | the_context->g4 = 0; |
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98 | |
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99 | /* PSTATE used to be built here, but is no longer included in context */ |
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100 | |
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101 | /* |
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102 | * Since THIS thread is being created, there is no way that THIS |
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103 | * thread can have an _ISR_Dispatch stack frame on its stack. |
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104 | */ |
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105 | the_context->isr_dispatch_disable = 0; |
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106 | |
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107 | if ( tls_area != NULL ) { |
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108 | void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area ); |
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109 | |
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110 | the_context->g7 = (uintptr_t) tcb; |
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111 | } |
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112 | } |
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113 | |
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114 | /* |
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115 | * This initializes the set of opcodes placed in each trap |
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116 | * table entry. The routine which installs a handler is responsible |
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117 | * for filling in the fields for the _handler address and the _vector |
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118 | * trap type. |
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119 | * |
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120 | * The constants following this structure are masks for the fields which |
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121 | * must be filled in when the handler is installed. |
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122 | */ |
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123 | |
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124 | /* 64-bit registers complicate this. Also, in sparc v9, |
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125 | * each trap level gets its own set of global registers, but |
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126 | * does not get its own dedicated register window. so we avoid |
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127 | * using the local registers in the trap handler. |
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128 | */ |
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129 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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130 | 0x89508000, /* rdpr %tstate, %g4 */ |
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131 | 0x05000000, /* sethi %hh(_handler), %g2 */ |
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132 | 0x8410a000, /* or %g2, %hm(_handler), %g2 */ |
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133 | 0x8528b020, /* sllx %g2, 32, %g2 */ |
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134 | 0x07000000, /* sethi %hi(_handler), %g3 */ |
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135 | 0x8610c002, /* or %g3, %g2, %g3 */ |
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136 | 0x81c0e000, /* jmp %g3 + %lo(_handler) */ |
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137 | 0x84102000 /* mov _vector, %g2 */ |
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138 | }; |
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139 | |
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140 | |
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141 | /* |
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142 | * _CPU_ISR_Get_level |
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143 | * |
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144 | * Input Parameters: NONE |
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145 | * |
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146 | * Output Parameters: |
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147 | * returns the current interrupt level (PIL field of the PSR) |
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148 | */ |
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149 | uint32_t _CPU_ISR_Get_level( void ) |
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150 | { |
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151 | uint32_t level; |
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152 | |
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153 | sparc64_get_interrupt_level( level ); |
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154 | |
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155 | return level; |
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156 | } |
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157 | |
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158 | /* |
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159 | * _CPU_ISR_install_raw_handler |
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160 | * |
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161 | * This routine installs the specified handler as a "raw" non-executive |
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162 | * supported trap handler (a.k.a. interrupt service routine). |
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163 | * |
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164 | * Input Parameters: |
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165 | * vector - trap table entry number plus synchronous |
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166 | * vs. asynchronous information |
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167 | * new_handler - address of the handler to be installed |
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168 | * old_handler - pointer to an address of the handler previously installed |
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169 | * |
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170 | * Output Parameters: NONE |
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171 | * *new_handler - address of the handler previously installed |
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172 | * |
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173 | * NOTE: |
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174 | * |
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175 | * On the SPARC v9, there are really only 512 vectors. However, the executive |
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176 | * has no easy, fast, reliable way to determine which traps are synchronous |
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177 | * and which are asynchronous. By default, traps return to the |
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178 | * instruction which caused the interrupt. So if you install a software |
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179 | * trap handler as an executive interrupt handler (which is desirable since |
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180 | * RTEMS takes care of window and register issues), then the executive needs |
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181 | * to know that the return address is to the trap rather than the instruction |
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182 | * following the trap. |
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183 | * |
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184 | * So vectors 0 through 511 are treated as regular asynchronous traps which |
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185 | * provide the "correct" return address. Vectors 512 through 1023 are assumed |
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186 | * by the executive to be synchronous and to require that the return be to the |
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187 | * trapping instruction. |
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188 | * |
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189 | * If you use this mechanism to install a trap handler which must reexecute |
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190 | * the instruction which caused the trap, then it should be installed as |
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191 | * a synchronous trap. This will avoid the executive changing the return |
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192 | * address. |
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193 | */ |
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194 | void _CPU_ISR_install_raw_handler( |
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195 | uint32_t vector, |
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196 | proc_ptr new_handler, |
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197 | proc_ptr *old_handler |
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198 | ) |
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199 | { |
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200 | uint32_t real_vector; |
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201 | CPU_Trap_table_entry *tba; |
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202 | CPU_Trap_table_entry *slot; |
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203 | uint64_t u64_tba; |
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204 | uint64_t u64_handler; |
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205 | |
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206 | /* |
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207 | * Get the "real" trap number for this vector ignoring the synchronous |
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208 | * versus asynchronous indicator included with our vector numbers. |
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209 | */ |
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210 | |
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211 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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212 | |
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213 | /* |
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214 | * Get the current base address of the trap table and calculate a pointer |
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215 | * to the slot we are interested in. |
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216 | */ |
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217 | |
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218 | sparc64_get_tba( u64_tba ); |
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219 | |
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220 | /* u32_tbr &= 0xfffff000; */ |
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221 | u64_tba &= 0xffffffffffff8000; /* keep only trap base address */ |
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222 | |
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223 | tba = (CPU_Trap_table_entry *) u64_tba; |
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224 | |
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225 | /* use array indexing to fill in lower bits -- require |
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226 | * CPU_Trap_table_entry to be full-sized. */ |
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227 | slot = &tba[ real_vector ]; |
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228 | |
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229 | /* |
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230 | * Get the address of the old_handler from the trap table. |
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231 | * |
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232 | * NOTE: The old_handler returned will be bogus if it does not follow |
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233 | * the RTEMS model. |
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234 | */ |
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235 | |
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236 | /* shift amount to shift of hi bits (31:10) */ |
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237 | #define HI_BITS_SHIFT 10 |
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238 | |
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239 | /* shift amount of hm bits (41:32) */ |
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240 | #define HM_BITS_SHIFT 32 |
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241 | |
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242 | /* shift amount of hh bits (63:42) */ |
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243 | #define HH_BITS_SHIFT 42 |
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244 | |
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245 | /* We're only interested in bits 0-9 of the immediate field*/ |
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246 | #define IMM_MASK 0x000003FF |
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247 | |
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248 | if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) { |
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249 | u64_handler = |
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250 | (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) | |
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251 | (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) | |
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252 | ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) | |
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253 | (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK)); |
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254 | *old_handler = (proc_ptr) u64_handler; |
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255 | } else |
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256 | *old_handler = 0; |
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257 | |
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258 | /* |
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259 | * Copy the template to the slot and then fix it. |
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260 | */ |
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261 | |
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262 | *slot = _CPU_Trap_slot_template; |
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263 | |
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264 | u64_handler = (uint64_t) new_handler; |
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265 | |
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266 | /* mask for extracting %hh */ |
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267 | #define HH_BITS_MASK 0xFFFFFC0000000000 |
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268 | |
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269 | /* mask for extracting %hm */ |
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270 | #define HM_BITS_MASK 0x000003FF00000000 |
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271 | |
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272 | /* mask for extracting %hi */ |
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273 | #define HI_BITS_MASK 0x00000000FFFFFC00 |
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274 | |
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275 | /* mask for extracting %lo */ |
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276 | #define LO_BITS_MASK 0x00000000000003FF |
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277 | |
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278 | |
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279 | slot->mov_vector_g2 |= vector; |
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280 | slot->sethi_of_hh_handler_to_g2 |= |
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281 | (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT; |
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282 | slot->or_g2_hm_handler_to_g2 |= |
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283 | (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT; |
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284 | slot->sethi_of_handler_to_g3 |= |
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285 | (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT; |
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286 | slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK); |
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287 | |
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288 | /* need to flush icache after this !!! */ |
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289 | |
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290 | /* need to flush icache in case old trap handler is in cache */ |
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291 | rtems_cache_invalidate_entire_instruction(); |
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292 | |
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293 | } |
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294 | |
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295 | /* |
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296 | * _CPU_ISR_install_vector |
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297 | * |
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298 | * This kernel routine installs the RTEMS handler for the |
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299 | * specified vector. |
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300 | * |
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301 | * Input parameters: |
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302 | * vector - interrupt vector number |
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303 | * new_handler - replacement ISR for this vector number |
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304 | * old_handler - pointer to former ISR for this vector number |
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305 | * |
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306 | * Output parameters: |
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307 | * *old_handler - former ISR for this vector number |
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308 | */ |
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309 | void _CPU_ISR_install_vector( |
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310 | uint64_t vector, |
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311 | proc_ptr new_handler, |
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312 | proc_ptr *old_handler |
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313 | ) |
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314 | { |
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315 | uint64_t real_vector; |
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316 | proc_ptr ignored; |
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317 | |
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318 | /* |
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319 | * Get the "real" trap number for this vector ignoring the synchronous |
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320 | * versus asynchronous indicator included with our vector numbers. |
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321 | */ |
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322 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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323 | /* |
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324 | * Return the previous ISR handler. |
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325 | */ |
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326 | |
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327 | *old_handler = _ISR_Vector_table[ vector ]; |
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328 | |
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329 | /* |
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330 | * Install the wrapper so this ISR can be invoked properly. |
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331 | */ |
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332 | |
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333 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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334 | |
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335 | /* |
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336 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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337 | * be used by the _ISR_Handler so the user gets control. |
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338 | */ |
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339 | |
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340 | _ISR_Vector_table[ real_vector ] = new_handler; |
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341 | } |
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