| 1 | /* context.S |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 5 | * in assembly language. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-2007. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | * |
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| 14 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 15 | * Research Corporation (OAR) under contract to the European Space |
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| 16 | * Agency (ESA). |
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| 17 | * |
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| 18 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 19 | * European Space Agency. |
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| 20 | * |
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| 21 | * Ported to UltraSPARC T1 Niagara implementation of the SPARC-v9. |
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| 22 | * Niagara modifications of respective RTEMS file: |
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| 23 | * COPYRIGHT (c) 2010. Gedare Bloom. |
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| 24 | * |
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| 25 | * $Id$ |
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| 26 | */ |
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| 27 | |
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| 28 | #include <rtems/asm.h> |
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| 29 | |
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| 30 | |
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| 31 | /* |
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| 32 | * The assembler needs to be told that we know what to do with |
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| 33 | * the global registers. |
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| 34 | */ |
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| 35 | .register %g2, #scratch |
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| 36 | .register %g3, #scratch |
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| 37 | .register %g6, #scratch |
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| 38 | .register %g7, #scratch |
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| 39 | |
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| 40 | #if (SPARC_HAS_FPU == 1) |
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| 41 | |
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| 42 | /* |
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| 43 | * void _CPU_Context_save_fp( |
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| 44 | * void **fp_context_ptr |
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| 45 | * ) |
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| 46 | * |
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| 47 | * This routine is responsible for saving the FP context |
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| 48 | * at *fp_context_ptr. If the point to load the FP context |
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| 49 | * from is changed then the pointer is modified by this routine. |
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| 50 | * |
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| 51 | */ |
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| 52 | |
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| 53 | .align 4 |
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| 54 | PUBLIC(_CPU_Context_save_fp) |
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| 55 | SYM(_CPU_Context_save_fp): |
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| 56 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 57 | |
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| 58 | /* |
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| 59 | * The following enables the floating point unit. |
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| 60 | */ |
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| 61 | |
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| 62 | sparc64_enable_FPU(%l0) |
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| 63 | |
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| 64 | /* |
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| 65 | * Although sun4v supports alternate register names for double- |
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| 66 | * and quad-word floating point, SPARC v9 only uses f[#] |
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| 67 | * |
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| 68 | * Because quad-word fp is not supported by the hardware in |
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| 69 | * many situations, we stick with double-word fp operations |
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| 70 | */ |
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| 71 | ldx [%i0], %l0 |
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| 72 | std %f0, [%l0] |
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| 73 | std %f2, [%l0 + F2_OFFSET] |
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| 74 | std %f4, [%l0 + F4_OFFSET] |
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| 75 | std %f6, [%l0 + F6_OFFSET] |
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| 76 | std %f8, [%l0 + F8_OFFSET] |
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| 77 | std %f10, [%l0 + F1O_OFFSET] |
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| 78 | std %f12, [%l0 + F12_OFFSET] |
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| 79 | std %f14, [%l0 + F14_OFFSET] |
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| 80 | std %f16, [%l0 + F16_OFFSET] |
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| 81 | std %f18, [%l0 + F18_OFFSET] |
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| 82 | std %f20, [%l0 + F2O_OFFSET] |
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| 83 | std %f22, [%l0 + F22_OFFSET] |
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| 84 | std %f24, [%l0 + F24_OFFSET] |
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| 85 | std %f26, [%l0 + F26_OFFSET] |
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| 86 | std %f28, [%l0 + F28_OFFSET] |
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| 87 | std %f30, [%l0 + F3O_OFFSET] |
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| 88 | std %f32, [%l0 + F32_OFFSET] |
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| 89 | std %f34, [%l0 + F34_OFFSET] |
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| 90 | std %f36, [%l0 + F36_OFFSET] |
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| 91 | std %f38, [%l0 + F38_OFFSET] |
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| 92 | std %f40, [%l0 + F4O_OFFSET] |
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| 93 | std %f42, [%l0 + F42_OFFSET] |
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| 94 | std %f44, [%l0 + F44_OFFSET] |
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| 95 | std %f46, [%l0 + F46_OFFSET] |
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| 96 | std %f48, [%l0 + F48_OFFSET] |
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| 97 | std %f50, [%l0 + F5O_OFFSET] |
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| 98 | std %f52, [%l0 + F52_OFFSET] |
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| 99 | std %f54, [%l0 + F54_OFFSET] |
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| 100 | std %f56, [%l0 + F56_OFFSET] |
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| 101 | std %f58, [%l0 + F58_OFFSET] |
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| 102 | std %f60, [%l0 + F6O_OFFSET] |
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| 103 | std %f62, [%l0 + F62_OFFSET] |
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| 104 | stx %fsr, [%l0 + FSR_OFFSET] |
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| 105 | ret |
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| 106 | restore |
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| 107 | |
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| 108 | /* |
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| 109 | * void _CPU_Context_restore_fp( |
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| 110 | * void **fp_context_ptr |
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| 111 | * ) |
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| 112 | * |
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| 113 | * This routine is responsible for restoring the FP context |
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| 114 | * at *fp_context_ptr. If the point to load the FP context |
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| 115 | * from is changed then the pointer is modified by this routine. |
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| 116 | * |
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| 117 | */ |
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| 118 | |
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| 119 | .align 4 |
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| 120 | PUBLIC(_CPU_Context_restore_fp) |
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| 121 | SYM(_CPU_Context_restore_fp): |
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| 122 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp |
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| 123 | |
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| 124 | /* |
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| 125 | * The following enables the floating point unit. |
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| 126 | */ |
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| 127 | |
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| 128 | sparc64_enable_FPU(%l0) |
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| 129 | |
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| 130 | ldx [%i0], %l0 |
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| 131 | ldd [%l0 + FO_OFFSET], %f0 |
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| 132 | ldd [%l0 + F2_OFFSET], %f2 |
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| 133 | ldd [%l0 + F4_OFFSET], %f4 |
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| 134 | ldd [%l0 + F6_OFFSET], %f6 |
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| 135 | ldd [%l0 + F8_OFFSET], %f8 |
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| 136 | ldd [%l0 + F1O_OFFSET], %f10 |
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| 137 | ldd [%l0 + F12_OFFSET], %f12 |
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| 138 | ldd [%l0 + F14_OFFSET], %f14 |
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| 139 | ldd [%l0 + F16_OFFSET], %f16 |
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| 140 | ldd [%l0 + F18_OFFSET], %f18 |
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| 141 | ldd [%l0 + F2O_OFFSET], %f20 |
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| 142 | ldd [%l0 + F22_OFFSET], %f22 |
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| 143 | ldd [%l0 + F24_OFFSET], %f24 |
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| 144 | ldd [%l0 + F26_OFFSET], %f26 |
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| 145 | ldd [%l0 + F28_OFFSET], %f28 |
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| 146 | ldd [%l0 + F3O_OFFSET], %f30 |
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| 147 | ldd [%l0 + F32_OFFSET], %f32 |
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| 148 | ldd [%l0 + F34_OFFSET], %f34 |
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| 149 | ldd [%l0 + F36_OFFSET], %f36 |
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| 150 | ldd [%l0 + F38_OFFSET], %f38 |
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| 151 | ldd [%l0 + F4O_OFFSET], %f40 |
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| 152 | ldd [%l0 + F42_OFFSET], %f42 |
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| 153 | ldd [%l0 + F44_OFFSET], %f44 |
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| 154 | ldd [%l0 + F46_OFFSET], %f46 |
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| 155 | ldd [%l0 + F48_OFFSET], %f48 |
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| 156 | ldd [%l0 + F5O_OFFSET], %f50 |
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| 157 | ldd [%l0 + F52_OFFSET], %f52 |
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| 158 | ldd [%l0 + F54_OFFSET], %f54 |
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| 159 | ldd [%l0 + F56_OFFSET], %f56 |
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| 160 | ldd [%l0 + F58_OFFSET], %f58 |
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| 161 | ldd [%l0 + F6O_OFFSET], %f60 |
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| 162 | ldd [%l0 + F62_OFFSET], %f62 |
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| 163 | ldx [%l0 + FSR_OFFSET], %fsr |
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| 164 | ret |
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| 165 | restore |
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| 166 | |
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| 167 | #endif /* SPARC_HAS_FPU */ |
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| 168 | |
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| 169 | /* |
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| 170 | * void _CPU_Context_switch( |
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| 171 | * Context_Control *run, |
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| 172 | * Context_Control *heir |
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| 173 | * ) |
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| 174 | * |
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| 175 | * This routine performs a normal non-FP context switch. |
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| 176 | */ |
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| 177 | |
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| 178 | .align 4 |
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| 179 | PUBLIC(_CPU_Context_switch) |
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| 180 | SYM(_CPU_Context_switch): |
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| 181 | ! skip g0 |
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| 182 | stx %g1, [%o0 + G1_OFFSET] ! save the global registers |
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| 183 | stx %g2, [%o0 + G2_OFFSET] |
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| 184 | stx %g3, [%o0 + G3_OFFSET] |
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| 185 | stx %g4, [%o0 + G4_OFFSET] |
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| 186 | stx %g5, [%o0 + G5_OFFSET] |
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| 187 | stx %g6, [%o0 + G6_OFFSET] |
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| 188 | stx %g7, [%o0 + G7_OFFSET] |
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| 189 | |
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| 190 | ! load the address of the ISR stack nesting prevention flag |
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| 191 | setx SYM(_CPU_ISR_Dispatch_disable), %g1, %g2 |
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| 192 | lduw [%g2], %g2 |
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| 193 | |
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| 194 | ! save it a bit later so we do not waste a couple of cycles |
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| 195 | |
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| 196 | stx %l0, [%o0 + L0_OFFSET] ! save the local registers |
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| 197 | stx %l1, [%o0 + L1_OFFSET] |
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| 198 | stx %l2, [%o0 + L2_OFFSET] |
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| 199 | stx %l3, [%o0 + L3_OFFSET] |
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| 200 | stx %l4, [%o0 + L4_OFFSET] |
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| 201 | stx %l5, [%o0 + L5_OFFSET] |
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| 202 | stx %l6, [%o0 + L6_OFFSET] |
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| 203 | stx %l7, [%o0 + L7_OFFSET] |
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| 204 | |
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| 205 | ! Now actually save ISR stack nesting prevention flag |
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| 206 | stuw %g2, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET] |
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| 207 | |
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| 208 | stx %i0, [%o0 + I0_OFFSET] ! save the input registers |
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| 209 | stx %i1, [%o0 + I1_OFFSET] |
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| 210 | stx %i2, [%o0 + I2_OFFSET] |
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| 211 | stx %i3, [%o0 + I3_OFFSET] |
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| 212 | stx %i4, [%o0 + I4_OFFSET] |
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| 213 | stx %i5, [%o0 + I5_OFFSET] |
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| 214 | stx %i6, [%o0 + I6_FP_OFFSET] |
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| 215 | stx %i7, [%o0 + I7_OFFSET] |
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| 216 | |
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| 217 | stx %o0, [%o0 + O0_OFFSET] ! save the output registers |
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| 218 | stx %o1, [%o0 + O1_OFFSET] |
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| 219 | stx %o2, [%o0 + O2_OFFSET] |
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| 220 | stx %o3, [%o0 + O3_OFFSET] |
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| 221 | stx %o4, [%o0 + O4_OFFSET] |
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| 222 | stx %o5, [%o0 + O5_OFFSET] |
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| 223 | stx %o6, [%o0 + O6_SP_OFFSET] |
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| 224 | stx %o7, [%o0 + O7_OFFSET] ! o7 is the PC |
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| 225 | |
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| 226 | ! rdpr %pil, %o2 |
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| 227 | ! stuw %o2, [%o0 + PIL_OFFSET] ! save pil |
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| 228 | |
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| 229 | ! rdpr %pstate, %o2 |
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| 230 | ! stx %o2, [%o0 + PSTATE_OFFSET] ! save status register |
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| 231 | |
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| 232 | /* |
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| 233 | * This is entered from _CPU_Context_restore with: |
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| 234 | * o1 = context to restore |
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| 235 | ! * o2 = pstate |
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| 236 | * |
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| 237 | * NOTE: Flushing the register windows is necessary, but it adds |
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| 238 | * an unpredictable (but bounded) overhead to context switching. |
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| 239 | */ |
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| 240 | |
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| 241 | PUBLIC(_CPU_Context_restore_heir) |
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| 242 | SYM(_CPU_Context_restore_heir): |
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| 243 | |
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| 244 | flushw |
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| 245 | |
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| 246 | |
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| 247 | |
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| 248 | ! skip g0 |
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| 249 | ldx [%o1 + G1_OFFSET], %g1 ! restore the global registers |
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| 250 | ldx [%o1 + G2_OFFSET], %g2 |
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| 251 | ldx [%o1 + G3_OFFSET], %g3 |
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| 252 | ldx [%o1 + G4_OFFSET], %g4 |
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| 253 | ldx [%o1 + G5_OFFSET], %g5 |
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| 254 | ldx [%o1 + G6_OFFSET], %g6 |
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| 255 | ldx [%o1 + G7_OFFSET], %g7 |
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| 256 | |
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| 257 | ! Load thread specific ISR dispatch prevention flag |
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| 258 | ldx [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2 |
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| 259 | setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o3 |
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| 260 | ! Store it to memory later to use the cycles |
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| 261 | |
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| 262 | ldx [%o1 + L0_OFFSET], %l0 ! restore the local registers |
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| 263 | ldx [%o1 + L1_OFFSET], %l1 |
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| 264 | ldx [%o1 + L2_OFFSET], %l2 |
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| 265 | ldx [%o1 + L3_OFFSET], %l3 |
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| 266 | ldx [%o1 + L4_OFFSET], %l4 |
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| 267 | ldx [%o1 + L5_OFFSET], %l5 |
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| 268 | ldx [%o1 + L6_OFFSET], %l6 |
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| 269 | ldx [%o1 + L7_OFFSET], %l7 |
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| 270 | |
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| 271 | ! Now restore thread specific ISR dispatch prevention flag |
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| 272 | stuw %o2, [%o3] |
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| 273 | |
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| 274 | ldx [%o1 + I0_OFFSET], %i0 ! restore the input registers |
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| 275 | ldx [%o1 + I1_OFFSET], %i1 |
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| 276 | ldx [%o1 + I2_OFFSET], %i2 |
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| 277 | ldx [%o1 + I3_OFFSET], %i3 |
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| 278 | ldx [%o1 + I4_OFFSET], %i4 |
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| 279 | ldx [%o1 + I5_OFFSET], %i5 |
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| 280 | ldx [%o1 + I6_FP_OFFSET], %i6 |
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| 281 | ldx [%o1 + I7_OFFSET], %i7 |
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| 282 | |
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| 283 | ldx [%o1 + O0_OFFSET], %o0 |
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| 284 | ldx [%o1 + O2_OFFSET], %o2 ! restore the output registers |
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| 285 | ldx [%o1 + O3_OFFSET], %o3 |
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| 286 | ldx [%o1 + O4_OFFSET], %o4 |
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| 287 | ldx [%o1 + O5_OFFSET], %o5 |
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| 288 | ldx [%o1 + O6_SP_OFFSET], %o6 |
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| 289 | ldx [%o1 + O7_OFFSET], %o7 ! PC |
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| 290 | |
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| 291 | ! on a hunch... we should be able to use some of the %o regs |
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| 292 | ! lduw [%o1 + PIL_OFFSET], %o2 |
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| 293 | ! wrpr %g0, %o2, %pil |
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| 294 | |
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| 295 | ! ldx [%o1 + PSTATE_OFFSET], %o2 |
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| 296 | |
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| 297 | ! do o1 last to avoid destroying heir context pointer |
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| 298 | ldx [%o1 + O1_OFFSET], %o1 ! overwrite heir pointer |
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| 299 | ! wrpr %g0, %o2, %pstate |
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| 300 | |
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| 301 | retl |
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| 302 | nop |
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| 303 | |
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| 304 | /* |
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| 305 | * void _CPU_Context_restore( |
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| 306 | * Context_Control *new_context |
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| 307 | * ) |
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| 308 | * |
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| 309 | * This routine is generally used only to perform restart self. |
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| 310 | * |
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| 311 | * NOTE: It is unnecessary to reload some registers. |
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| 312 | */ |
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| 313 | /* if _CPU_Context_restore_heir does not flushw, then do it here */ |
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| 314 | .align 4 |
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| 315 | PUBLIC(_CPU_Context_restore) |
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| 316 | SYM(_CPU_Context_restore): |
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| 317 | save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 318 | ! rdpr %pstate, %o2 |
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| 319 | ba SYM(_CPU_Context_restore_heir) |
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| 320 | mov %i0, %o1 ! in the delay slot |
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| 321 | |
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| 322 | /* end of file */ |
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