source: rtems/cpukit/score/cpu/sparc/sparc-counter-asm.S @ b2da982

Last change on this file since b2da982 was b2da982, checked in by Daniel Hellstrom <daniel@…>, on 04/21/20 at 09:57:50

leon,tn-0018: work around GRLIB-TN-0018 errata

Overview
========

The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:

www.gaisler.com/notes

Affected RTEMS target BSPs:

  • GR712RC
  • UT699
  • UT700/699E

The work around is enabled by defining FIX_LEON3_TN0018 at build time.
After applying the following GCC patch, GCC will set the define when
compiling for an affected multilib:

  • GR712RC (-mcpu=leon3 -mfix-gr712rc)
  • UT700/UT699E (-mpcu=leon3 -mfix-ut700)
  • UT699 (-mcpu=leon -mfix-ut699)

When building for another multilib and TN0018 is still required, it
is possible to enable it on the RTEMS kernel configure line using the
TARGET_CFLAGS (-DFIX_LEON3FT_TN0018) or other by other means.

The following GCC patch sets FIX_LEON3FT_TN0018 for the affected RTEMS
multilibs:


diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h
index 6570590..ddec98c 100644
--- a/gcc/config/sparc/rtemself.h
+++ b/gcc/config/sparc/rtemself.h
@@ -33,6 +33,8 @@

builtin_assert ("system=rtems"); \
if (sparc_fix_b2bst) \

builtin_define ("FIX_LEON3FT_B2BST"); \

+ if (sparc_fix_gr712rc

sparc_fix_ut700 sparc_fix_ut699) \
+ builtin_define ("FIX_LEON3FT_TN0018"); \

} \

while (0)


Workaround Implementation
=========================

In general there are two approaches that the workaround uses:

A) avoid ECC restarting the RETT instruction
B) avoid returning from trap to a JMPL instruction

Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.

A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.

B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.

RTEMS SPARC traps workaround implementation:

NAME NOTE TRAP COMMENT

  • window overflow 1 - 0x05 always returns to a SAVE
  • window underflow 1 - 0x06 always returns to a RESTORE
  • interrupt traps 2 - 0x10..1f special rett sequence workaround
  • syscall 3 - 0x80 shutdown system - never returns
  • ABI flush windows 2 - 0x83 special rett sequence workaround
  • syscall_irqdis 4 - 0x89
  • syscall_irqen 4 - 0x8A
  • syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction
  • syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to

B) _Internal_error() starting with SAVE

Notes:
1) no workaround needed because trap always returns to non-JMPL instruction
2) workaround implemented by special rett sequence
3) no workaround needed because system call never returns
4) workaround implemented by inserting NOP in system call generation. Thus

fall into 1) when workaround is enabled and no trap handler fix needed.

5) trap handler branches into both 1) and returning to _Internal_error()

which starts with a SAVE and besides since it shuts down the system that
RETT should never be in cache (only executed once) so fix not necessary
in this case.

Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <libcpu/grlib-tn-0018.h>.

Close #4155.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 * Copyright (c) 2016, 2018 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16#include "config.h"
17#endif
18
19#include <rtems/asm.h>
20
21        /*
22         * All functions except _SPARC_Counter_read_clock() in this module are
23         * sometimes called with traps disabled.
24         */
25
26        .section        ".text"
27        .align  4
28
29        PUBLIC(_SPARC_Counter_read_default)
30SYM(_SPARC_Counter_read_default):
31        sethi   %hi(_SPARC_Counter + 12), %o1
32        ld      [%o1 + %lo(_SPARC_Counter + 12)], %o0
33        add     %o0, 1, %o0
34        st      %o0, [%o1 + %lo(_SPARC_Counter + 12)]
35        jmp     %o7 + 8
36         nop
37
38        PUBLIC(_SPARC_Counter_read_up)
39        PUBLIC(_SPARC_Get_timecount_up)
40SYM(_SPARC_Counter_read_up):
41SYM(_SPARC_Get_timecount_up):
42        sethi   %hi(_SPARC_Counter + 8), %o0
43        ld      [%o0 + %lo(_SPARC_Counter + 8)], %o0
44        jmp     %o7 + 8
45         ld     [%o0], %o0
46
47        PUBLIC(_SPARC_Counter_read_down)
48        PUBLIC(_SPARC_Get_timecount_down)
49SYM(_SPARC_Counter_read_down):
50SYM(_SPARC_Get_timecount_down):
51        sethi   %hi(_SPARC_Counter + 8), %o0
52        ld      [%o0 + %lo(_SPARC_Counter + 8)], %o0
53        ld      [%o0], %o0
54        jmp     %o7 + 8
55         xnor   %g0, %o0, %o0
56
57        /*
58         * For the corresponding C code is something like this:
59         *
60         * CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void )
61         * {
62         *   const SPARC_Counter *ctr;
63         *   CPU_Counter_ticks    ticks;
64         *   CPU_Counter_ticks    accumulated;
65         *
66         *   ctr = &_SPARC_Counter;
67         *   ticks = *ctr->counter_register;
68         *   accumulated = ctr->accumulated;
69         *
70         *   if ( ( *ctr->pending_register & ctr->pending_mask ) != 0 ) {
71         *     ticks = *ctr->counter_register;
72         *     accumulated += ctr->interval;
73         *   }
74         *
75         *   return accumulated - ticks;
76         * }
77         */
78        PUBLIC(_SPARC_Counter_read_clock_isr_disabled)
79SYM(_SPARC_Counter_read_clock_isr_disabled):
80        sethi   %hi(_SPARC_Counter), %o5
81        or      %o5, %lo(_SPARC_Counter), %o5
82        ld      [%o5 + 8], %o3
83        ld      [%o5 + 12], %o4
84        ld      [%o5 + 16], %o2
85        ld      [%o3], %o0
86        ld      [%o4], %o1
87        btst    %o1, %o2
88        bne     .Lpending_isr_disabled
89         ld     [%o5 + 20], %o4
90        jmp     %o7 + 8
91         sub    %o4, %o0, %o0
92.Lpending_isr_disabled:
93        ld      [%o5 + 24], %o5
94        ld      [%o3], %o0
95        add     %o4, %o5, %o4
96        jmp     %o7 + 8
97         sub    %o4, %o0, %o0
98
99        /*
100         * For the corresponding C code see
101         * _SPARC_Counter_read_clock_isr_disabled() above.
102         */
103        PUBLIC(_SPARC_Counter_read_clock)
104        PUBLIC(_SPARC_Get_timecount_clock)
105SYM(_SPARC_Counter_read_clock):
106SYM(_SPARC_Get_timecount_clock):
107        sethi   %hi(_SPARC_Counter), %o5
108        or      %o5, %lo(_SPARC_Counter), %o5
109        ta      SPARC_SWTRAP_IRQDIS
110        ld      [%o5 + 8], %o3
111        ld      [%o5 + 12], %o4
112        ld      [%o5 + 16], %o2
113        ld      [%o3], %o0
114        ld      [%o4], %o1
115        btst    %o1, %o2
116        bne     .Lpending
117         ld     [%o5 + 20], %o4
118        ta      SPARC_SWTRAP_IRQEN
119#ifdef __FIX_LEON3FT_TN0018
120        /* A nop is added to work around the GRLIB-TN-0018 errata */
121        nop
122#endif
123        jmp     %o7 + 8
124         sub    %o4, %o0, %o0
125.Lpending:
126        ld      [%o5 + 24], %o5
127        ld      [%o3], %o0
128        ta      SPARC_SWTRAP_IRQEN
129        add     %o4, %o5, %o4
130        jmp     %o7 + 8
131         sub    %o4, %o0, %o0
132
133        PUBLIC(_SPARC_Counter_read_asr23)
134        PUBLIC(_SPARC_Get_timecount_asr23)
135SYM(_SPARC_Counter_read_asr23):
136SYM(_SPARC_Get_timecount_asr23):
137        jmp     %o7 + 8
138         mov    %asr23, %o0
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