source: rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h @ f6ed46df

4.104.114.84.95
Last change on this file since f6ed46df was f6ed46df, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 4, 2005 at 5:40:52 AM

Header guards cleanup.

  • Property mode set to 100644
File size: 6.5 KB
Line 
1/**
2 * @file rtems/score/sparc.h
3 */
4
5/*
6 *  This include file contains information pertaining to the SPARC
7 *  processor family.
8 *
9 *  COPYRIGHT (c) 1989-1999.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_SPARC_H
20#define _RTEMS_SCORE_SPARC_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 *  This file contains the information required to build
28 *  RTEMS for a particular member of the "sparc" family.  It does
29 *  this by setting variables to indicate which implementation
30 *  dependent features are present in a particular member
31 *  of the family.
32 *
33 *  Currently recognized feature flags:
34 *
35 *    + SPARC_HAS_FPU
36 *        0 - no HW FPU
37 *        1 - has HW FPU (assumed to be compatible w/90C602)
38 *
39 *    + SPARC_HAS_BITSCAN
40 *        0 - does not have scan instructions
41 *        1 - has scan instruction  (not currently implemented)
42 *
43 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
44 *        8 is the most common number supported by SPARC implementations.
45 *        SPARC_PSR_CWP_MASK is derived from this value.
46 */
47 
48/*
49 *  Some higher end SPARCs have a bitscan instructions. It would
50 *  be nice to take advantage of them.  Right now, there is no
51 *  port to a CPU model with this feature and no (untested) code
52 *  that is based on this feature flag.
53 */
54
55#define SPARC_HAS_BITSCAN                0
56
57/*
58 *  This should be OK until a port to a higher end SPARC processor
59 *  is made that has more than 8 register windows.  If this cannot
60 *  be determined based on multilib settings (v7/v8/v9), then the
61 *  cpu_asm.S code that depends on this will have to move to libcpu.
62 */
63
64#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
65 
66/*
67 *  This should be determined based on some soft float derived
68 *  cpp predefine but gcc does not currently give us that information.
69 */
70
71
72#if defined(_SOFT_FLOAT)
73#define SPARC_HAS_FPU 0
74#else
75#define SPARC_HAS_FPU 1
76#endif
77
78#if SPARC_HAS_FPU
79#define CPU_MODEL_NAME "w/FPU"
80#else
81#define CPU_MODEL_NAME "w/soft-float"
82#endif
83
84/*
85 *  Define the name of the CPU family.
86 */
87
88#define CPU_NAME "SPARC"
89
90/*
91 *  Miscellaneous constants
92 */
93
94/*
95 *  PSR masks and starting bit positions
96 *
97 *  NOTE: Reserved bits are ignored.
98 */
99
100#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
101#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
102#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
103#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
104#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
105#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
106#else
107#error "Unsupported number of register windows for this cpu"
108#endif
109
110#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
111#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
112#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
113#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
114#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
115#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
116#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
117#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
118#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
119
120#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
121#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
122#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
123#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
124#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
125#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
126#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
127#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
128#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
129#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
130
131#ifndef ASM
132
133/*
134 *  Standard nop
135 */
136
137#define nop() \
138  do { \
139    asm volatile ( "nop" ); \
140  } while ( 0 )
141
142/*
143 *  Get and set the PSR
144 */
145
146#define sparc_get_psr( _psr ) \
147  do { \
148     (_psr) = 0; \
149     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
150  } while ( 0 )
151
152#define sparc_set_psr( _psr ) \
153  do { \
154    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
155    nop(); \
156    nop(); \
157    nop(); \
158  } while ( 0 )
159
160/*
161 *  Get and set the TBR
162 */
163
164#define sparc_get_tbr( _tbr ) \
165  do { \
166     (_tbr) = 0; /* to avoid unitialized warnings */ \
167     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
168  } while ( 0 )
169
170#define sparc_set_tbr( _tbr ) \
171  do { \
172     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
173  } while ( 0 )
174
175/*
176 *  Get and set the WIM
177 */
178
179#define sparc_get_wim( _wim ) \
180  do { \
181    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
182  } while ( 0 )
183
184#define sparc_set_wim( _wim ) \
185  do { \
186    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
187    nop(); \
188    nop(); \
189    nop(); \
190  } while ( 0 )
191
192/*
193 *  Get and set the Y
194 */
195 
196#define sparc_get_y( _y ) \
197  do { \
198    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
199  } while ( 0 )
200 
201#define sparc_set_y( _y ) \
202  do { \
203    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
204  } while ( 0 )
205
206/*
207 *  Manipulate the interrupt level in the psr
208 *
209 */
210
211/*
212#define sparc_disable_interrupts( _level ) \
213  do { \
214    register unsigned int _newlevel; \
215    \
216    sparc_get_psr( _level ); \
217    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
218    sparc_set_psr( _newlevel ); \
219  } while ( 0 )
220
221#define sparc_enable_interrupts( _level ) \
222  do { \
223    unsigned int _tmp; \
224    \
225    sparc_get_psr( _tmp ); \
226    _tmp &= ~SPARC_PSR_PIL_MASK; \
227    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
228    sparc_set_psr( _tmp ); \
229  } while ( 0 )
230*/
231 
232#define sparc_flash_interrupts( _level ) \
233  do { \
234    register uint32_t   _ignored = 0; \
235    \
236    sparc_enable_interrupts( (_level) ); \
237    sparc_disable_interrupts( _ignored ); \
238  } while ( 0 )
239
240/*
241#define sparc_set_interrupt_level( _new_level ) \
242  do { \
243    register uint32_t   _new_psr_level = 0; \
244    \
245    sparc_get_psr( _new_psr_level ); \
246    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
247    _new_psr_level |= \
248      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
249    sparc_set_psr( _new_psr_level ); \
250  } while ( 0 )
251*/
252
253#define sparc_get_interrupt_level( _level ) \
254  do { \
255    register uint32_t   _psr_level = 0; \
256    \
257    sparc_get_psr( _psr_level ); \
258    (_level) = \
259      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
260  } while ( 0 )
261
262#endif
263
264#ifdef __cplusplus
265}
266#endif
267
268#endif /* _RTEMS_SCORE_SPARC_H */
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