source: rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h @ df49c60

4.104.114.84.95
Last change on this file since df49c60 was df49c60, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 15:00:15

Merged from 4.5.0-beta3a

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File size: 6.7 KB
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1/*  sparc.h
2 *
3 *  This include file contains information pertaining to the SPARC
4 *  processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
14 *  Research Corporation (OAR) under contract to the European Space
15 *  Agency (ESA).
16 *
17 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
18 *  European Space Agency.
19 *
20 *  $Id$
21 */
22
23#ifndef _INCLUDE_SPARC_h
24#define _INCLUDE_SPARC_h
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/*
31 *  This file contains the information required to build
32 *  RTEMS for a particular member of the "sparc" family.  It does
33 *  this by setting variables to indicate which implementation
34 *  dependent features are present in a particular member
35 *  of the family.
36 *
37 *  Currently recognized feature flags:
38 *
39 *    + SPARC_HAS_FPU
40 *        0 - no HW FPU
41 *        1 - has HW FPU (assumed to be compatible w/90C602)
42 *
43 *    + SPARC_HAS_BITSCAN
44 *        0 - does not have scan instructions
45 *        1 - has scan instruction  (not currently implemented)
46 *
47 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
48 *        8 is the most common number supported by SPARC implementations.
49 *        SPARC_PSR_CWP_MASK is derived from this value.
50 *
51 *    + SPARC_HAS_LOW_POWER_MODE
52 *        0 - does not have low power mode support (or not supported)
53 *        1 - has low power mode and thus a CPU model dependent idle task.
54 *
55 */
56 
57#if defined(rtems_multilib)
58/*
59 *  Figure out all CPU Model Feature Flags based upon compiler
60 *  predefines.
61 */
62
63#define CPU_MODEL_NAME                   "rtems_multilib"
64#define SPARC_HAS_FPU                    1
65#define SPARC_HAS_BITSCAN                0
66#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
67#define SPARC_HAS_LOW_POWER_MODE         1
68
69#elif defined(erc32)
70 
71#define CPU_MODEL_NAME                   "erc32"
72#define SPARC_HAS_FPU                    1
73#define SPARC_HAS_BITSCAN                0
74#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
75#define SPARC_HAS_LOW_POWER_MODE         1
76 
77#else
78 
79#error "Unsupported CPU Model"
80 
81#endif
82
83/*
84 *  Define the name of the CPU family.
85 */
86
87#define CPU_NAME "SPARC"
88
89/*
90 *  Miscellaneous constants
91 */
92
93/*
94 *  PSR masks and starting bit positions
95 *
96 *  NOTE: Reserved bits are ignored.
97 */
98
99#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
100#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
101#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
102#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
103#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
104#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
105#else
106#error "Unsupported number of register windows for this cpu"
107#endif
108
109#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
110#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
111#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
112#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
113#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
114#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
115#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
116#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
117#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
118
119#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
120#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
121#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
122#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
123#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
124#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
125#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
126#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
127#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
128#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
129
130#ifndef ASM
131
132/*
133 *  Standard nop
134 */
135
136#define nop() \
137  do { \
138    asm volatile ( "nop" ); \
139  } while ( 0 )
140
141/*
142 *  Get and set the PSR
143 */
144
145#define sparc_get_psr( _psr ) \
146  do { \
147     (_psr) = 0; \
148     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
149  } while ( 0 )
150
151#define sparc_set_psr( _psr ) \
152  do { \
153    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
154    nop(); \
155    nop(); \
156    nop(); \
157  } while ( 0 )
158
159/*
160 *  Get and set the TBR
161 */
162
163#define sparc_get_tbr( _tbr ) \
164  do { \
165     (_tbr) = 0; /* to avoid unitialized warnings */ \
166     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
167  } while ( 0 )
168
169#define sparc_set_tbr( _tbr ) \
170  do { \
171     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
172  } while ( 0 )
173
174/*
175 *  Get and set the WIM
176 */
177
178#define sparc_get_wim( _wim ) \
179  do { \
180    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
181  } while ( 0 )
182
183#define sparc_set_wim( _wim ) \
184  do { \
185    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
186    nop(); \
187    nop(); \
188    nop(); \
189  } while ( 0 )
190
191/*
192 *  Get and set the Y
193 */
194 
195#define sparc_get_y( _y ) \
196  do { \
197    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
198  } while ( 0 )
199 
200#define sparc_set_y( _y ) \
201  do { \
202    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
203  } while ( 0 )
204
205/*
206 *  Manipulate the interrupt level in the psr
207 *
208 */
209
210/*
211#define sparc_disable_interrupts( _level ) \
212  do { \
213    register unsigned int _newlevel; \
214    \
215    sparc_get_psr( _level ); \
216    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
217    sparc_set_psr( _newlevel ); \
218  } while ( 0 )
219
220#define sparc_enable_interrupts( _level ) \
221  do { \
222    unsigned int _tmp; \
223    \
224    sparc_get_psr( _tmp ); \
225    _tmp &= ~SPARC_PSR_PIL_MASK; \
226    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
227    sparc_set_psr( _tmp ); \
228  } while ( 0 )
229*/
230 
231#define sparc_flash_interrupts( _level ) \
232  do { \
233    register unsigned32 _ignored = 0; \
234    \
235    sparc_enable_interrupts( (_level) ); \
236    sparc_disable_interrupts( _ignored ); \
237  } while ( 0 )
238
239/*
240#define sparc_set_interrupt_level( _new_level ) \
241  do { \
242    register unsigned32 _new_psr_level = 0; \
243    \
244    sparc_get_psr( _new_psr_level ); \
245    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
246    _new_psr_level |= \
247      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
248    sparc_set_psr( _new_psr_level ); \
249  } while ( 0 )
250*/
251
252#define sparc_get_interrupt_level( _level ) \
253  do { \
254    register unsigned32 _psr_level = 0; \
255    \
256    sparc_get_psr( _psr_level ); \
257    (_level) = \
258      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
259  } while ( 0 )
260
261#endif
262
263#ifdef __cplusplus
264}
265#endif
266
267#endif /* ! _INCLUDE_SPARC_h */
268/* end of include file */
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