1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Information Required to Build RTEMS for a Particular Member |
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5 | * of the SPARC Family |
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6 | * |
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7 | * This file contains the information required to build |
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8 | * RTEMS for a particular member of the SPARC family. It does |
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9 | * this by setting variables to indicate which implementation |
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10 | * dependent features are present in a particular member |
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11 | * of the family. |
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12 | */ |
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13 | |
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14 | /* |
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15 | * COPYRIGHT (c) 1989-2011. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef _RTEMS_SCORE_SPARC_H |
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24 | #define _RTEMS_SCORE_SPARC_H |
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25 | |
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26 | #include <rtems/score/types.h> |
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27 | |
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28 | #ifdef __cplusplus |
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29 | extern "C" { |
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30 | #endif |
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31 | |
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32 | /* |
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33 | * |
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34 | * Currently recognized feature flags: |
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35 | * |
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36 | * + SPARC_HAS_FPU |
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37 | * 0 - no HW FPU |
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38 | * 1 - has HW FPU (assumed to be compatible w/90C602) |
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39 | * |
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40 | * + SPARC_HAS_BITSCAN |
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41 | * 0 - does not have scan instructions |
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42 | * 1 - has scan instruction (not currently implemented) |
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43 | * |
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44 | * + SPARC_NUMBER_OF_REGISTER_WINDOWS |
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45 | * 8 is the most common number supported by SPARC implementations. |
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46 | * SPARC_PSR_CWP_MASK is derived from this value. |
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47 | */ |
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48 | |
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49 | /** |
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50 | * Some higher end SPARCs have a bitscan instructions. It would |
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51 | * be nice to take advantage of them. Right now, there is no |
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52 | * port to a CPU model with this feature and no (untested) code |
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53 | * that is based on this feature flag. |
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54 | */ |
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55 | #define SPARC_HAS_BITSCAN 0 |
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56 | |
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57 | /** |
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58 | * This should be OK until a port to a higher end SPARC processor |
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59 | * is made that has more than 8 register windows. If this cannot |
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60 | * be determined based on multilib settings (v7/v8/v9), then the |
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61 | * cpu_asm.S code that depends on this will have to move to libcpu. |
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62 | */ |
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63 | #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 |
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64 | |
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65 | /** |
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66 | * This macro indicates whether this multilib variation has hardware |
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67 | * floating point or not. We use the gcc cpp predefine _SOFT_FLOAT |
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68 | * to determine that. |
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69 | */ |
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70 | #if defined(_SOFT_FLOAT) |
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71 | #define SPARC_HAS_FPU 0 |
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72 | #else |
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73 | #define SPARC_HAS_FPU 1 |
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74 | #endif |
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75 | |
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76 | /** |
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77 | * This macro contains a string describing the multilib variant being |
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78 | * build. |
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79 | */ |
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80 | #if SPARC_HAS_FPU |
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81 | #define CPU_MODEL_NAME "w/FPU" |
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82 | #else |
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83 | #define CPU_MODEL_NAME "w/soft-float" |
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84 | #endif |
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85 | |
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86 | /** |
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87 | * Define the name of the CPU family. |
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88 | */ |
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89 | #define CPU_NAME "SPARC" |
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90 | |
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91 | /* |
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92 | * Miscellaneous constants |
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93 | */ |
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94 | |
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95 | /** |
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96 | * PSR masks and starting bit positions |
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97 | * |
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98 | * NOTE: Reserved bits are ignored. |
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99 | */ |
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100 | #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) |
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101 | #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ |
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102 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) |
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103 | #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ |
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104 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) |
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105 | #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ |
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106 | #else |
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107 | #error "Unsupported number of register windows for this cpu" |
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108 | #endif |
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109 | |
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110 | /** This constant is a mask for the ET bits in the PSR. */ |
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111 | #define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ |
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112 | /** This constant is a mask for the PS bits in the PSR. */ |
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113 | #define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ |
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114 | /** This constant is a mask for the S bits in the PSR. */ |
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115 | #define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ |
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116 | /** This constant is a mask for the PIL bits in the PSR. */ |
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117 | #define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ |
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118 | /** This constant is a mask for the EF bits in the PSR. */ |
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119 | #define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ |
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120 | /** This constant is a mask for the EC bits in the PSR. */ |
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121 | #define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ |
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122 | /** This constant is a mask for the ICC bits in the PSR. */ |
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123 | #define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ |
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124 | /** This constant is a mask for the VER bits in the PSR. */ |
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125 | #define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ |
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126 | /** This constant is a mask for the IMPL bits in the PSR. */ |
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127 | #define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ |
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128 | |
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129 | /** This constant is the starting bit position of the CWP in the PSR. */ |
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130 | #define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ |
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131 | /** This constant is the starting bit position of the ET in the PSR. */ |
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132 | #define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ |
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133 | /** This constant is the starting bit position of the PS in the PSR. */ |
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134 | #define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ |
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135 | /** This constant is the starting bit position of the S in the PSR. */ |
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136 | #define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ |
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137 | /** This constant is the starting bit position of the PIL in the PSR. */ |
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138 | #define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ |
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139 | /** This constant is the starting bit position of the EF in the PSR. */ |
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140 | #define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ |
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141 | /** This constant is the starting bit position of the EC in the PSR. */ |
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142 | #define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ |
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143 | /** This constant is the starting bit position of the ICC in the PSR. */ |
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144 | #define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ |
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145 | /** This constant is the starting bit position of the VER in the PSR. */ |
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146 | #define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ |
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147 | /** This constant is the starting bit position of the IMPL in the PSR. */ |
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148 | #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ |
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149 | |
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150 | #define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28 |
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151 | |
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152 | #ifndef ASM |
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153 | |
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154 | /** |
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155 | * This macro is a standard nop instruction. |
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156 | */ |
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157 | #define nop() \ |
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158 | do { \ |
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159 | __asm__ volatile ( "nop" ); \ |
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160 | } while ( 0 ) |
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161 | |
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162 | /** |
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163 | * @brief Macro to obtain the PSR. |
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164 | * |
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165 | * This macro returns the current contents of the PSR register in @a _psr. |
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166 | */ |
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167 | #define sparc_get_psr( _psr ) \ |
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168 | do { \ |
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169 | (_psr) = 0; \ |
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170 | __asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ |
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171 | } while ( 0 ) |
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172 | |
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173 | /** |
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174 | * @brief Macro to set the PSR. |
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175 | * |
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176 | * This macro sets the PSR register to the value in @a _psr. |
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177 | */ |
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178 | #define sparc_set_psr( _psr ) \ |
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179 | do { \ |
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180 | __asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ |
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181 | nop(); \ |
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182 | nop(); \ |
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183 | nop(); \ |
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184 | } while ( 0 ) |
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185 | |
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186 | /** |
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187 | * @brief Macro to obtain the TBR. |
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188 | * |
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189 | * This macro returns the current contents of the TBR register in @a _tbr. |
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190 | */ |
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191 | #define sparc_get_tbr( _tbr ) \ |
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192 | do { \ |
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193 | (_tbr) = 0; /* to avoid unitialized warnings */ \ |
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194 | __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ |
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195 | } while ( 0 ) |
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196 | |
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197 | /** |
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198 | * @brief Macro to set the TBR. |
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199 | * |
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200 | * This macro sets the TBR register to the value in @a _tbr. |
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201 | */ |
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202 | #define sparc_set_tbr( _tbr ) \ |
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203 | do { \ |
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204 | __asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ |
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205 | } while ( 0 ) |
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206 | |
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207 | /** |
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208 | * @brief Macro to obtain the WIM. |
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209 | * |
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210 | * This macro returns the current contents of the WIM field in @a _wim. |
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211 | */ |
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212 | #define sparc_get_wim( _wim ) \ |
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213 | do { \ |
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214 | __asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ |
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215 | } while ( 0 ) |
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216 | |
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217 | /** |
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218 | * @brief Macro to set the WIM. |
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219 | * |
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220 | * This macro sets the WIM field to the value in @a _wim. |
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221 | */ |
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222 | #define sparc_set_wim( _wim ) \ |
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223 | do { \ |
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224 | __asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ |
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225 | nop(); \ |
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226 | nop(); \ |
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227 | nop(); \ |
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228 | } while ( 0 ) |
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229 | |
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230 | /** |
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231 | * @brief Macro to obtain the Y register. |
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232 | * |
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233 | * This macro returns the current contents of the Y register in @a _y. |
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234 | */ |
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235 | #define sparc_get_y( _y ) \ |
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236 | do { \ |
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237 | __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ |
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238 | } while ( 0 ) |
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239 | |
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240 | /** |
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241 | * @brief Macro to set the Y register. |
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242 | * |
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243 | * This macro sets the Y register to the value in @a _y. |
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244 | */ |
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245 | #define sparc_set_y( _y ) \ |
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246 | do { \ |
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247 | __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ |
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248 | } while ( 0 ) |
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249 | |
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250 | /** |
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251 | * @brief SPARC disable processor interrupts. |
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252 | * |
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253 | * This method is invoked to disable all maskable interrupts. |
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254 | * |
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255 | * @return This method returns the entire PSR contents. |
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256 | */ |
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257 | uint32_t sparc_disable_interrupts(void); |
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258 | |
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259 | /** |
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260 | * @brief SPARC enable processor interrupts. |
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261 | * |
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262 | * This method is invoked to enable all maskable interrupts. |
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263 | * |
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264 | * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. |
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265 | */ |
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266 | void sparc_enable_interrupts(uint32_t psr); |
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267 | |
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268 | /** |
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269 | * @brief SPARC exit through system call 1 |
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270 | * |
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271 | * This method is invoked to go into system error halt. The optional |
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272 | * arguments can be given to hypervisor, hardware debugger, simulator or |
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273 | * similar. |
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274 | * |
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275 | * System error mode is entered when taking a trap when traps have been |
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276 | * disabled. What happens when error mode is entered depends on the motherboard. |
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277 | * In a typical development systems the CPU relingish control to the debugger, |
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278 | * simulator, hypervisor or similar. The following steps are taken: |
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279 | * |
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280 | * 1. Going into system error mode by Software Trap 0 |
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281 | * 2. %g1=1 (syscall 1 - Exit) |
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282 | * 3. %g2=Primary exit code |
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283 | * 4. %g3=Secondary exit code. Dependends on %g2 exit type. |
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284 | * |
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285 | * This function never returns. |
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286 | * |
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287 | * @param[in] exitcode1 Primary exit code stored in CPU g2 register after exit |
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288 | * @param[in] exitcode2 Primary exit code stored in CPU g3 register after exit |
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289 | */ |
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290 | void sparc_syscall_exit(uint32_t exitcode1, uint32_t exitcode2) |
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291 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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292 | |
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293 | /** |
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294 | * @brief SPARC flash processor interrupts. |
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295 | * |
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296 | * This method is invoked to temporarily enable all maskable interrupts. |
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297 | * |
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298 | * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts. |
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299 | */ |
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300 | #define sparc_flash_interrupts( _psr ) \ |
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301 | do { \ |
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302 | sparc_enable_interrupts( (_psr) ); \ |
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303 | _psr = sparc_disable_interrupts(); \ |
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304 | } while ( 0 ) |
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305 | |
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306 | /** |
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307 | * @brief SPARC obtain interrupt level. |
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308 | * |
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309 | * This method is invoked to obtain the current interrupt disable level. |
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310 | * |
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311 | * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts. |
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312 | */ |
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313 | #define sparc_get_interrupt_level( _level ) \ |
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314 | do { \ |
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315 | register uint32_t _psr_level = 0; \ |
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316 | \ |
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317 | sparc_get_psr( _psr_level ); \ |
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318 | (_level) = \ |
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319 | (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ |
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320 | } while ( 0 ) |
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321 | |
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322 | static inline uint32_t _LEON3_Get_current_processor( void ) |
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323 | { |
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324 | uint32_t asr17; |
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325 | |
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326 | __asm__ volatile ( |
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327 | "rd %%asr17, %0" |
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328 | : "=&r" (asr17) |
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329 | ); |
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330 | |
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331 | return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT; |
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332 | } |
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333 | |
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334 | #endif |
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335 | |
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336 | #ifdef __cplusplus |
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337 | } |
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338 | #endif |
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339 | |
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340 | #endif /* _RTEMS_SCORE_SPARC_H */ |
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