source: rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h @ 7908ba5b

4.104.114.84.95
Last change on this file since 7908ba5b was 7908ba5b, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 18, 1999 at 6:28:24 PM

Part of the automake VI patch from Ralf Corsepius <corsepiu@…>:

4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh

reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
contains the diffs after reorg-score-cpu.sh has been run on a
rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.

This patch is rather nasty and may break something. However, I've tested
it for about 10 different target/bsp pairs and believe to have shaken
out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h

  • Property mode set to 100644
File size: 6.4 KB
Line 
1/*  sparc.h
2 *
3 *  This include file contains information pertaining to the SPARC
4 *  processor family.
5 *
6 *  COPYRIGHT (c) 1989-1998.
7 *  On-Line Applications Research Corporation (OAR).
8 *  Copyright assigned to U.S. Government, 1994.
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
15 *  Research Corporation (OAR) under contract to the European Space
16 *  Agency (ESA).
17 *
18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19 *  European Space Agency.
20 *
21 *  $Id$
22 */
23
24#ifndef _INCLUDE_SPARC_h
25#define _INCLUDE_SPARC_h
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/*
32 *  This file contains the information required to build
33 *  RTEMS for a particular member of the "sparc" family.  It does
34 *  this by setting variables to indicate which implementation
35 *  dependent features are present in a particular member
36 *  of the family.
37 *
38 *  Currently recognized feature flags:
39 *
40 *    + SPARC_HAS_FPU
41 *        0 - no HW FPU
42 *        1 - has HW FPU (assumed to be compatible w/90C602)
43 *
44 *    + SPARC_HAS_BITSCAN
45 *        0 - does not have scan instructions
46 *        1 - has scan instruction  (not currently implemented)
47 *
48 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
49 *        8 is the most common number supported by SPARC implementations.
50 *        SPARC_PSR_CWP_MASK is derived from this value.
51 *
52 *    + SPARC_HAS_LOW_POWER_MODE
53 *        0 - does not have low power mode support (or not supported)
54 *        1 - has low power mode and thus a CPU model dependent idle task.
55 *
56 */
57 
58#if defined(erc32)
59 
60#define CPU_MODEL_NAME                   "erc32"
61#define SPARC_HAS_FPU                    1
62#define SPARC_HAS_BITSCAN                0
63#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
64#define SPARC_HAS_LOW_POWER_MODE         1
65 
66#else
67 
68#error "Unsupported CPU Model"
69 
70#endif
71
72/*
73 *  Define the name of the CPU family.
74 */
75
76#define CPU_NAME "SPARC"
77
78/*
79 *  Miscellaneous constants
80 */
81
82/*
83 *  PSR masks and starting bit positions
84 *
85 *  NOTE: Reserved bits are ignored.
86 */
87
88#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
89#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
90#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
91#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
92#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
93#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
94#else
95#error "Unsupported number of register windows for this cpu"
96#endif
97
98#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
99#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
100#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
101#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
102#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
103#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
104#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
105#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
106#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
107
108#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
109#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
110#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
111#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
112#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
113#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
114#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
115#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
116#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
117#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
118
119#ifndef ASM
120
121/*
122 *  Standard nop
123 */
124
125#define nop() \
126  do { \
127    asm volatile ( "nop" ); \
128  } while ( 0 )
129
130/*
131 *  Get and set the PSR
132 */
133
134#define sparc_get_psr( _psr ) \
135  do { \
136     (_psr) = 0; \
137     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
138  } while ( 0 )
139
140#define sparc_set_psr( _psr ) \
141  do { \
142    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
143    nop(); \
144    nop(); \
145    nop(); \
146  } while ( 0 )
147
148/*
149 *  Get and set the TBR
150 */
151
152#define sparc_get_tbr( _tbr ) \
153  do { \
154     (_tbr) = 0; /* to avoid unitialized warnings */ \
155     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
156  } while ( 0 )
157
158#define sparc_set_tbr( _tbr ) \
159  do { \
160     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
161  } while ( 0 )
162
163/*
164 *  Get and set the WIM
165 */
166
167#define sparc_get_wim( _wim ) \
168  do { \
169    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
170  } while ( 0 )
171
172#define sparc_set_wim( _wim ) \
173  do { \
174    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
175    nop(); \
176    nop(); \
177    nop(); \
178  } while ( 0 )
179
180/*
181 *  Get and set the Y
182 */
183 
184#define sparc_get_y( _y ) \
185  do { \
186    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
187  } while ( 0 )
188 
189#define sparc_set_y( _y ) \
190  do { \
191    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
192  } while ( 0 )
193
194/*
195 *  Manipulate the interrupt level in the psr
196 *
197 */
198
199#define sparc_disable_interrupts( _level ) \
200  do { \
201    register unsigned int _newlevel; \
202    \
203    sparc_get_psr( _level ); \
204    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
205    sparc_set_psr( _newlevel ); \
206  } while ( 0 )
207 
208#define sparc_enable_interrupts( _level ) \
209  do { \
210    unsigned int _tmp; \
211    \
212    sparc_get_psr( _tmp ); \
213    _tmp &= ~SPARC_PSR_PIL_MASK; \
214    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
215    sparc_set_psr( _tmp ); \
216  } while ( 0 )
217 
218#define sparc_flash_interrupts( _level ) \
219  do { \
220    register unsigned32 _ignored = 0; \
221    \
222    sparc_enable_interrupts( (_level) ); \
223    sparc_disable_interrupts( _ignored ); \
224  } while ( 0 )
225
226#define sparc_set_interrupt_level( _new_level ) \
227  do { \
228    register unsigned32 _new_psr_level = 0; \
229    \
230    sparc_get_psr( _new_psr_level ); \
231    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
232    _new_psr_level |= \
233      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
234    sparc_set_psr( _new_psr_level ); \
235  } while ( 0 )
236
237#define sparc_get_interrupt_level( _level ) \
238  do { \
239    register unsigned32 _psr_level = 0; \
240    \
241    sparc_get_psr( _psr_level ); \
242    (_level) = \
243      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
244  } while ( 0 )
245
246#endif
247
248#ifdef __cplusplus
249}
250#endif
251
252#endif /* ! _INCLUDE_SPARC_h */
253/* end of include file */
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