source: rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h @ 477e2d19

4.104.114.84.95
Last change on this file since 477e2d19 was 477e2d19, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 15, 2000 at 9:33:35 PM

2000-11-14 Jiri Gaisler <jgais@…>

  • cpu.c, rtems/cpu/sparc.h: Make floating point optional based on gcc arguments. Do not initialize FP context if there is no FPU. Flush instruction cache after installing RTEMS trap handler.
  • Property mode set to 100644
File size: 6.5 KB
Line 
1/*  sparc.h
2 *
3 *  This include file contains information pertaining to the SPARC
4 *  processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef _INCLUDE_SPARC_h
17#define _INCLUDE_SPARC_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This file contains the information required to build
25 *  RTEMS for a particular member of the "sparc" family.  It does
26 *  this by setting variables to indicate which implementation
27 *  dependent features are present in a particular member
28 *  of the family.
29 *
30 *  Currently recognized feature flags:
31 *
32 *    + SPARC_HAS_FPU
33 *        0 - no HW FPU
34 *        1 - has HW FPU (assumed to be compatible w/90C602)
35 *
36 *    + SPARC_HAS_BITSCAN
37 *        0 - does not have scan instructions
38 *        1 - has scan instruction  (not currently implemented)
39 *
40 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
41 *        8 is the most common number supported by SPARC implementations.
42 *        SPARC_PSR_CWP_MASK is derived from this value.
43 */
44 
45/*
46 *  Some higher end SPARCs have a bitscan instructions. It would
47 *  be nice to take advantage of them.  Right now, there is no
48 *  port to a CPU model with this feature and no (untested) code
49 *  that is based on this feature flag.
50 */
51
52#define SPARC_HAS_BITSCAN                0
53
54/*
55 *  This should be OK until a port to a higher end SPARC processor
56 *  is made that has more than 8 register windows.  If this cannot
57 *  be determined based on multilib settings (v7/v8/v9), then the
58 *  cpu_asm.S code that depends on this will have to move to libcpu.
59 */
60
61#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
62 
63/*
64 *  This should be determined based on some soft float derived
65 *  cpp predefine but gcc does not currently give us that information.
66 */
67
68
69#if defined(_SOFT_FLOAT)
70#define SPARC_HAS_FPU 0
71#else
72#define SPARC_HAS_FPU 1
73#endif
74
75#if SPARC_HAS_FPU
76#define CPU_MODEL_NAME "w/FPU"
77#else
78#define CPU_MODEL_NAME "w/soft-float"
79#endif
80
81/*
82 *  Define the name of the CPU family.
83 */
84
85#define CPU_NAME "SPARC"
86
87/*
88 *  Miscellaneous constants
89 */
90
91/*
92 *  PSR masks and starting bit positions
93 *
94 *  NOTE: Reserved bits are ignored.
95 */
96
97#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
98#define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
99#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
100#define SPARC_PSR_CWP_MASK               0x0F   /* bits  0 -  4 */
101#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
102#define SPARC_PSR_CWP_MASK               0x1F   /* bits  0 -  4 */
103#else
104#error "Unsupported number of register windows for this cpu"
105#endif
106
107#define SPARC_PSR_ET_MASK   0x00000020   /* bit   5 */
108#define SPARC_PSR_PS_MASK   0x00000040   /* bit   6 */
109#define SPARC_PSR_S_MASK    0x00000080   /* bit   7 */
110#define SPARC_PSR_PIL_MASK  0x00000F00   /* bits  8 - 11 */
111#define SPARC_PSR_EF_MASK   0x00001000   /* bit  12 */
112#define SPARC_PSR_EC_MASK   0x00002000   /* bit  13 */
113#define SPARC_PSR_ICC_MASK  0x00F00000   /* bits 20 - 23 */
114#define SPARC_PSR_VER_MASK  0x0F000000   /* bits 24 - 27 */
115#define SPARC_PSR_IMPL_MASK 0xF0000000   /* bits 28 - 31 */
116
117#define SPARC_PSR_CWP_BIT_POSITION   0   /* bits  0 -  4 */
118#define SPARC_PSR_ET_BIT_POSITION    5   /* bit   5 */
119#define SPARC_PSR_PS_BIT_POSITION    6   /* bit   6 */
120#define SPARC_PSR_S_BIT_POSITION     7   /* bit   7 */
121#define SPARC_PSR_PIL_BIT_POSITION   8   /* bits  8 - 11 */
122#define SPARC_PSR_EF_BIT_POSITION   12   /* bit  12 */
123#define SPARC_PSR_EC_BIT_POSITION   13   /* bit  13 */
124#define SPARC_PSR_ICC_BIT_POSITION  20   /* bits 20 - 23 */
125#define SPARC_PSR_VER_BIT_POSITION  24   /* bits 24 - 27 */
126#define SPARC_PSR_IMPL_BIT_POSITION 28   /* bits 28 - 31 */
127
128#ifndef ASM
129
130/*
131 *  Standard nop
132 */
133
134#define nop() \
135  do { \
136    asm volatile ( "nop" ); \
137  } while ( 0 )
138
139/*
140 *  Get and set the PSR
141 */
142
143#define sparc_get_psr( _psr ) \
144  do { \
145     (_psr) = 0; \
146     asm volatile( "rd %%psr, %0" :  "=r" (_psr) : "0" (_psr) ); \
147  } while ( 0 )
148
149#define sparc_set_psr( _psr ) \
150  do { \
151    asm volatile ( "mov  %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
152    nop(); \
153    nop(); \
154    nop(); \
155  } while ( 0 )
156
157/*
158 *  Get and set the TBR
159 */
160
161#define sparc_get_tbr( _tbr ) \
162  do { \
163     (_tbr) = 0; /* to avoid unitialized warnings */ \
164     asm volatile( "rd %%tbr, %0" :  "=r" (_tbr) : "0" (_tbr) ); \
165  } while ( 0 )
166
167#define sparc_set_tbr( _tbr ) \
168  do { \
169     asm volatile( "wr %0, 0, %%tbr" :  "=r" (_tbr) : "0" (_tbr) ); \
170  } while ( 0 )
171
172/*
173 *  Get and set the WIM
174 */
175
176#define sparc_get_wim( _wim ) \
177  do { \
178    asm volatile( "rd %%wim, %0" :  "=r" (_wim) : "0" (_wim) ); \
179  } while ( 0 )
180
181#define sparc_set_wim( _wim ) \
182  do { \
183    asm volatile( "wr %0, %%wim" :  "=r" (_wim) : "0" (_wim) ); \
184    nop(); \
185    nop(); \
186    nop(); \
187  } while ( 0 )
188
189/*
190 *  Get and set the Y
191 */
192 
193#define sparc_get_y( _y ) \
194  do { \
195    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
196  } while ( 0 )
197 
198#define sparc_set_y( _y ) \
199  do { \
200    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
201  } while ( 0 )
202
203/*
204 *  Manipulate the interrupt level in the psr
205 *
206 */
207
208/*
209#define sparc_disable_interrupts( _level ) \
210  do { \
211    register unsigned int _newlevel; \
212    \
213    sparc_get_psr( _level ); \
214    (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
215    sparc_set_psr( _newlevel ); \
216  } while ( 0 )
217
218#define sparc_enable_interrupts( _level ) \
219  do { \
220    unsigned int _tmp; \
221    \
222    sparc_get_psr( _tmp ); \
223    _tmp &= ~SPARC_PSR_PIL_MASK; \
224    _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
225    sparc_set_psr( _tmp ); \
226  } while ( 0 )
227*/
228 
229#define sparc_flash_interrupts( _level ) \
230  do { \
231    register unsigned32 _ignored = 0; \
232    \
233    sparc_enable_interrupts( (_level) ); \
234    sparc_disable_interrupts( _ignored ); \
235  } while ( 0 )
236
237/*
238#define sparc_set_interrupt_level( _new_level ) \
239  do { \
240    register unsigned32 _new_psr_level = 0; \
241    \
242    sparc_get_psr( _new_psr_level ); \
243    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
244    _new_psr_level |= \
245      (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
246    sparc_set_psr( _new_psr_level ); \
247  } while ( 0 )
248*/
249
250#define sparc_get_interrupt_level( _level ) \
251  do { \
252    register unsigned32 _psr_level = 0; \
253    \
254    sparc_get_psr( _psr_level ); \
255    (_level) = \
256      (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
257  } while ( 0 )
258
259#endif
260
261#ifdef __cplusplus
262}
263#endif
264
265#endif /* ! _INCLUDE_SPARC_h */
266/* end of include file */
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