1 | /* sparc.h |
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2 | * |
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3 | * This include file contains information pertaining to the SPARC |
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4 | * processor family. |
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5 | * |
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6 | * COPYRIGHT (c) 1989-1999. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.OARcorp.com/rtems/license.html. |
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12 | * |
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13 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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14 | * Research Corporation (OAR) under contract to the European Space |
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15 | * Agency (ESA). |
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16 | * |
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17 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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18 | * European Space Agency. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #ifndef _INCLUDE_SPARC_h |
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24 | #define _INCLUDE_SPARC_h |
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25 | |
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26 | #ifdef __cplusplus |
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27 | extern "C" { |
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28 | #endif |
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29 | |
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30 | /* |
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31 | * This file contains the information required to build |
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32 | * RTEMS for a particular member of the "sparc" family. It does |
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33 | * this by setting variables to indicate which implementation |
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34 | * dependent features are present in a particular member |
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35 | * of the family. |
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36 | * |
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37 | * Currently recognized feature flags: |
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38 | * |
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39 | * + SPARC_HAS_FPU |
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40 | * 0 - no HW FPU |
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41 | * 1 - has HW FPU (assumed to be compatible w/90C602) |
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42 | * |
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43 | * + SPARC_HAS_BITSCAN |
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44 | * 0 - does not have scan instructions |
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45 | * 1 - has scan instruction (not currently implemented) |
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46 | * |
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47 | * + SPARC_NUMBER_OF_REGISTER_WINDOWS |
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48 | * 8 is the most common number supported by SPARC implementations. |
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49 | * SPARC_PSR_CWP_MASK is derived from this value. |
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50 | * |
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51 | * + SPARC_HAS_LOW_POWER_MODE |
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52 | * 0 - does not have low power mode support (or not supported) |
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53 | * 1 - has low power mode and thus a CPU model dependent idle task. |
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54 | * |
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55 | */ |
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56 | |
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57 | #if defined(erc32) |
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58 | |
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59 | #define CPU_MODEL_NAME "erc32" |
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60 | #define SPARC_HAS_FPU 1 |
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61 | #define SPARC_HAS_BITSCAN 0 |
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62 | #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 |
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63 | #define SPARC_HAS_LOW_POWER_MODE 1 |
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64 | |
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65 | #else |
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66 | |
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67 | #error "Unsupported CPU Model" |
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68 | |
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69 | #endif |
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70 | |
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71 | /* |
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72 | * Define the name of the CPU family. |
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73 | */ |
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74 | |
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75 | #define CPU_NAME "SPARC" |
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76 | |
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77 | /* |
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78 | * Miscellaneous constants |
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79 | */ |
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80 | |
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81 | /* |
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82 | * PSR masks and starting bit positions |
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83 | * |
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84 | * NOTE: Reserved bits are ignored. |
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85 | */ |
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86 | |
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87 | #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) |
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88 | #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ |
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89 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) |
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90 | #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ |
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91 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) |
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92 | #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ |
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93 | #else |
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94 | #error "Unsupported number of register windows for this cpu" |
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95 | #endif |
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96 | |
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97 | #define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ |
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98 | #define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ |
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99 | #define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ |
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100 | #define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ |
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101 | #define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ |
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102 | #define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ |
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103 | #define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ |
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104 | #define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ |
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105 | #define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ |
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106 | |
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107 | #define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ |
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108 | #define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ |
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109 | #define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ |
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110 | #define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ |
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111 | #define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ |
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112 | #define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ |
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113 | #define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ |
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114 | #define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ |
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115 | #define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ |
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116 | #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ |
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117 | |
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118 | #ifndef ASM |
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119 | |
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120 | /* |
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121 | * Standard nop |
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122 | */ |
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123 | |
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124 | #define nop() \ |
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125 | do { \ |
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126 | asm volatile ( "nop" ); \ |
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127 | } while ( 0 ) |
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128 | |
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129 | /* |
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130 | * Get and set the PSR |
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131 | */ |
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132 | |
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133 | #define sparc_get_psr( _psr ) \ |
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134 | do { \ |
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135 | (_psr) = 0; \ |
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136 | asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ |
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137 | } while ( 0 ) |
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138 | |
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139 | #define sparc_set_psr( _psr ) \ |
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140 | do { \ |
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141 | asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ |
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142 | nop(); \ |
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143 | nop(); \ |
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144 | nop(); \ |
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145 | } while ( 0 ) |
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146 | |
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147 | /* |
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148 | * Get and set the TBR |
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149 | */ |
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150 | |
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151 | #define sparc_get_tbr( _tbr ) \ |
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152 | do { \ |
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153 | (_tbr) = 0; /* to avoid unitialized warnings */ \ |
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154 | asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ |
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155 | } while ( 0 ) |
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156 | |
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157 | #define sparc_set_tbr( _tbr ) \ |
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158 | do { \ |
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159 | asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ |
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160 | } while ( 0 ) |
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161 | |
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162 | /* |
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163 | * Get and set the WIM |
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164 | */ |
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165 | |
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166 | #define sparc_get_wim( _wim ) \ |
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167 | do { \ |
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168 | asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ |
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169 | } while ( 0 ) |
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170 | |
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171 | #define sparc_set_wim( _wim ) \ |
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172 | do { \ |
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173 | asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ |
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174 | nop(); \ |
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175 | nop(); \ |
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176 | nop(); \ |
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177 | } while ( 0 ) |
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178 | |
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179 | /* |
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180 | * Get and set the Y |
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181 | */ |
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182 | |
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183 | #define sparc_get_y( _y ) \ |
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184 | do { \ |
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185 | asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ |
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186 | } while ( 0 ) |
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187 | |
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188 | #define sparc_set_y( _y ) \ |
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189 | do { \ |
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190 | asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ |
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191 | } while ( 0 ) |
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192 | |
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193 | /* |
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194 | * Manipulate the interrupt level in the psr |
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195 | * |
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196 | */ |
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197 | |
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198 | /* |
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199 | #define sparc_disable_interrupts( _level ) \ |
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200 | do { \ |
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201 | register unsigned int _newlevel; \ |
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202 | \ |
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203 | sparc_get_psr( _level ); \ |
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204 | (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \ |
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205 | sparc_set_psr( _newlevel ); \ |
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206 | } while ( 0 ) |
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207 | |
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208 | #define sparc_enable_interrupts( _level ) \ |
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209 | do { \ |
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210 | unsigned int _tmp; \ |
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211 | \ |
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212 | sparc_get_psr( _tmp ); \ |
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213 | _tmp &= ~SPARC_PSR_PIL_MASK; \ |
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214 | _tmp |= (_level) & SPARC_PSR_PIL_MASK; \ |
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215 | sparc_set_psr( _tmp ); \ |
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216 | } while ( 0 ) |
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217 | */ |
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218 | |
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219 | #define sparc_flash_interrupts( _level ) \ |
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220 | do { \ |
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221 | register unsigned32 _ignored = 0; \ |
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222 | \ |
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223 | sparc_enable_interrupts( (_level) ); \ |
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224 | sparc_disable_interrupts( _ignored ); \ |
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225 | } while ( 0 ) |
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226 | |
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227 | /* |
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228 | #define sparc_set_interrupt_level( _new_level ) \ |
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229 | do { \ |
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230 | register unsigned32 _new_psr_level = 0; \ |
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231 | \ |
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232 | sparc_get_psr( _new_psr_level ); \ |
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233 | _new_psr_level &= ~SPARC_PSR_PIL_MASK; \ |
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234 | _new_psr_level |= \ |
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235 | (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \ |
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236 | sparc_set_psr( _new_psr_level ); \ |
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237 | } while ( 0 ) |
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238 | */ |
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239 | |
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240 | #define sparc_get_interrupt_level( _level ) \ |
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241 | do { \ |
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242 | register unsigned32 _psr_level = 0; \ |
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243 | \ |
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244 | sparc_get_psr( _psr_level ); \ |
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245 | (_level) = \ |
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246 | (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ |
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247 | } while ( 0 ) |
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248 | |
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249 | #endif |
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250 | |
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251 | #ifdef __cplusplus |
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252 | } |
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253 | #endif |
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254 | |
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255 | #endif /* ! _INCLUDE_SPARC_h */ |
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256 | /* end of include file */ |
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