[f4ae0c5] | 1 | /** |
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[1362b7a] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief Information Required to Build RTEMS for a Particular Member |
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| 5 | * of the SPARC Family |
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[4bafde5] | 6 | * |
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| 7 | * This file contains the information required to build |
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| 8 | * RTEMS for a particular member of the SPARC family. It does |
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| 9 | * this by setting variables to indicate which implementation |
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| 10 | * dependent features are present in a particular member |
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| 11 | * of the family. |
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[f4ae0c5] | 12 | */ |
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| 13 | |
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| 14 | /* |
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[4bafde5] | 15 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 16 | * On-Line Applications Research Corporation (OAR). |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 21 | */ |
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| 22 | |
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[7f70d1b7] | 23 | #ifndef _RTEMS_SCORE_SPARC_H |
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| 24 | #define _RTEMS_SCORE_SPARC_H |
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[7908ba5b] | 25 | |
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[ad4ef3c] | 26 | #include <rtems/score/types.h> |
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[b1ce6f29] | 27 | |
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[7908ba5b] | 28 | #ifdef __cplusplus |
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| 29 | extern "C" { |
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| 30 | #endif |
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| 31 | |
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| 32 | /* |
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| 33 | * |
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| 34 | * Currently recognized feature flags: |
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| 35 | * |
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[80f7732] | 36 | * + SPARC_HAS_FPU |
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[7908ba5b] | 37 | * 0 - no HW FPU |
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| 38 | * 1 - has HW FPU (assumed to be compatible w/90C602) |
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| 39 | * |
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[80f7732] | 40 | * + SPARC_HAS_BITSCAN |
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[7908ba5b] | 41 | * 0 - does not have scan instructions |
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| 42 | * 1 - has scan instruction (not currently implemented) |
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[80f7732] | 43 | * |
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[7908ba5b] | 44 | * + SPARC_NUMBER_OF_REGISTER_WINDOWS |
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| 45 | * 8 is the most common number supported by SPARC implementations. |
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| 46 | * SPARC_PSR_CWP_MASK is derived from this value. |
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| 47 | */ |
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[80f7732] | 48 | |
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[4bafde5] | 49 | /** |
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[1362b7a] | 50 | * Some higher end SPARCs have a bitscan instructions. It would |
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| 51 | * be nice to take advantage of them. Right now, there is no |
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| 52 | * port to a CPU model with this feature and no (untested) code |
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| 53 | * that is based on this feature flag. |
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[df49c60] | 54 | */ |
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| 55 | #define SPARC_HAS_BITSCAN 0 |
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| 56 | |
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[4bafde5] | 57 | /** |
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[1362b7a] | 58 | * This should be OK until a port to a higher end SPARC processor |
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| 59 | * is made that has more than 8 register windows. If this cannot |
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| 60 | * be determined based on multilib settings (v7/v8/v9), then the |
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| 61 | * cpu_asm.S code that depends on this will have to move to libcpu. |
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[4159370] | 62 | */ |
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[7908ba5b] | 63 | #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 |
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[80f7732] | 64 | |
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[4bafde5] | 65 | /** |
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[1362b7a] | 66 | * This macro indicates whether this multilib variation has hardware |
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| 67 | * floating point or not. We use the gcc cpp predefine _SOFT_FLOAT |
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| 68 | * to determine that. |
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[4159370] | 69 | */ |
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[477e2d19] | 70 | #if defined(_SOFT_FLOAT) |
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[4bafde5] | 71 | #define SPARC_HAS_FPU 0 |
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[477e2d19] | 72 | #else |
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[4bafde5] | 73 | #define SPARC_HAS_FPU 1 |
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[477e2d19] | 74 | #endif |
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[4159370] | 75 | |
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[4bafde5] | 76 | /** |
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[1362b7a] | 77 | * This macro contains a string describing the multilib variant being |
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| 78 | * build. |
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[4bafde5] | 79 | */ |
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[4159370] | 80 | #if SPARC_HAS_FPU |
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[4bafde5] | 81 | #define CPU_MODEL_NAME "w/FPU" |
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[7908ba5b] | 82 | #else |
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[4bafde5] | 83 | #define CPU_MODEL_NAME "w/soft-float" |
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[7908ba5b] | 84 | #endif |
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| 85 | |
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[4bafde5] | 86 | /** |
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[1362b7a] | 87 | * Define the name of the CPU family. |
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[7908ba5b] | 88 | */ |
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| 89 | #define CPU_NAME "SPARC" |
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| 90 | |
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| 91 | /* |
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| 92 | * Miscellaneous constants |
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| 93 | */ |
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| 94 | |
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[4bafde5] | 95 | /** |
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[1362b7a] | 96 | * PSR masks and starting bit positions |
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[7908ba5b] | 97 | * |
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[1362b7a] | 98 | * NOTE: Reserved bits are ignored. |
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[7908ba5b] | 99 | */ |
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| 100 | #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) |
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[4bafde5] | 101 | #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ |
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[7908ba5b] | 102 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) |
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[4bafde5] | 103 | #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ |
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[7908ba5b] | 104 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) |
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[4bafde5] | 105 | #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ |
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[7908ba5b] | 106 | #else |
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[4bafde5] | 107 | #error "Unsupported number of register windows for this cpu" |
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[7908ba5b] | 108 | #endif |
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| 109 | |
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[4bafde5] | 110 | /** This constant is a mask for the ET bits in the PSR. */ |
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[7908ba5b] | 111 | #define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ |
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[4bafde5] | 112 | /** This constant is a mask for the PS bits in the PSR. */ |
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[7908ba5b] | 113 | #define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ |
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[4bafde5] | 114 | /** This constant is a mask for the S bits in the PSR. */ |
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[7908ba5b] | 115 | #define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ |
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[4bafde5] | 116 | /** This constant is a mask for the PIL bits in the PSR. */ |
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[7908ba5b] | 117 | #define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ |
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[4bafde5] | 118 | /** This constant is a mask for the EF bits in the PSR. */ |
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[7908ba5b] | 119 | #define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ |
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[4bafde5] | 120 | /** This constant is a mask for the EC bits in the PSR. */ |
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[7908ba5b] | 121 | #define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ |
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[4bafde5] | 122 | /** This constant is a mask for the ICC bits in the PSR. */ |
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[7908ba5b] | 123 | #define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ |
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[4bafde5] | 124 | /** This constant is a mask for the VER bits in the PSR. */ |
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[7908ba5b] | 125 | #define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ |
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[4bafde5] | 126 | /** This constant is a mask for the IMPL bits in the PSR. */ |
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[7908ba5b] | 127 | #define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ |
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| 128 | |
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[4bafde5] | 129 | /** This constant is the starting bit position of the CWP in the PSR. */ |
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[7908ba5b] | 130 | #define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ |
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[4bafde5] | 131 | /** This constant is the starting bit position of the ET in the PSR. */ |
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[7908ba5b] | 132 | #define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ |
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[4bafde5] | 133 | /** This constant is the starting bit position of the PS in the PSR. */ |
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[7908ba5b] | 134 | #define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ |
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[4bafde5] | 135 | /** This constant is the starting bit position of the S in the PSR. */ |
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[7908ba5b] | 136 | #define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ |
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[4bafde5] | 137 | /** This constant is the starting bit position of the PIL in the PSR. */ |
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[7908ba5b] | 138 | #define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ |
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[4bafde5] | 139 | /** This constant is the starting bit position of the EF in the PSR. */ |
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[7908ba5b] | 140 | #define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ |
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[4bafde5] | 141 | /** This constant is the starting bit position of the EC in the PSR. */ |
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[7908ba5b] | 142 | #define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ |
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[4bafde5] | 143 | /** This constant is the starting bit position of the ICC in the PSR. */ |
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[7908ba5b] | 144 | #define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ |
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[4bafde5] | 145 | /** This constant is the starting bit position of the VER in the PSR. */ |
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[7908ba5b] | 146 | #define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ |
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[4bafde5] | 147 | /** This constant is the starting bit position of the IMPL in the PSR. */ |
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[7908ba5b] | 148 | #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ |
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| 149 | |
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[ad56361] | 150 | #define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28 |
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| 151 | |
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[dff1803] | 152 | /* SPARC Software Trap number definitions */ |
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| 153 | #define SPARC_SWTRAP_SYSCALL 0 |
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| 154 | #define SPARC_SWTRAP_IRQDIS 9 |
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| 155 | #define SPARC_SWTRAP_IRQEN 10 |
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| 156 | |
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[7908ba5b] | 157 | #ifndef ASM |
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| 158 | |
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[4bafde5] | 159 | /** |
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[1362b7a] | 160 | * This macro is a standard nop instruction. |
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[7908ba5b] | 161 | */ |
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| 162 | #define nop() \ |
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| 163 | do { \ |
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[e4a2a21f] | 164 | __asm__ volatile ( "nop" ); \ |
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[7908ba5b] | 165 | } while ( 0 ) |
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| 166 | |
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[4bafde5] | 167 | /** |
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[1362b7a] | 168 | * @brief Macro to obtain the PSR. |
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[4bafde5] | 169 | * |
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[1362b7a] | 170 | * This macro returns the current contents of the PSR register in @a _psr. |
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[7908ba5b] | 171 | */ |
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[8df1f408] | 172 | #if defined(RTEMS_PARAVIRT) |
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| 173 | |
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| 174 | uint32_t _SPARC_Get_PSR( void ); |
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| 175 | |
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| 176 | #define sparc_get_psr( _psr ) \ |
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| 177 | (_psr) = _SPARC_Get_PSR() |
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| 178 | |
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| 179 | #else /* RTEMS_PARAVIRT */ |
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| 180 | |
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[7908ba5b] | 181 | #define sparc_get_psr( _psr ) \ |
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| 182 | do { \ |
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| 183 | (_psr) = 0; \ |
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[e4a2a21f] | 184 | __asm__ volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ |
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[7908ba5b] | 185 | } while ( 0 ) |
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| 186 | |
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[8df1f408] | 187 | #endif /* RTEMS_PARAVIRT */ |
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| 188 | |
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[4bafde5] | 189 | /** |
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[1362b7a] | 190 | * @brief Macro to set the PSR. |
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[4bafde5] | 191 | * |
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[1362b7a] | 192 | * This macro sets the PSR register to the value in @a _psr. |
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[4bafde5] | 193 | */ |
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[8df1f408] | 194 | #if defined(RTEMS_PARAVIRT) |
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| 195 | |
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| 196 | void _SPARC_Set_PSR( uint32_t new_psr ); |
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| 197 | |
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| 198 | #define sparc_set_psr( _psr ) \ |
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| 199 | _SPARC_Set_PSR( _psr ) |
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| 200 | |
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| 201 | #else /* RTEMS_PARAVIRT */ |
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| 202 | |
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[7908ba5b] | 203 | #define sparc_set_psr( _psr ) \ |
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| 204 | do { \ |
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[e4a2a21f] | 205 | __asm__ volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ |
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[7908ba5b] | 206 | nop(); \ |
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| 207 | nop(); \ |
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| 208 | nop(); \ |
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| 209 | } while ( 0 ) |
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| 210 | |
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[8df1f408] | 211 | #endif /* RTEMS_PARAVIRT */ |
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| 212 | |
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[4bafde5] | 213 | /** |
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[1362b7a] | 214 | * @brief Macro to obtain the TBR. |
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[4bafde5] | 215 | * |
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[1362b7a] | 216 | * This macro returns the current contents of the TBR register in @a _tbr. |
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[7908ba5b] | 217 | */ |
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[8df1f408] | 218 | #if defined(RTEMS_PARAVIRT) |
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| 219 | |
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| 220 | uint32_t _SPARC_Get_TBR( void ); |
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| 221 | |
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| 222 | #define sparc_get_tbr( _tbr ) \ |
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| 223 | (_tbr) = _SPARC_Get_TBR() |
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| 224 | |
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| 225 | #else /* RTEMS_PARAVIRT */ |
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| 226 | |
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[7908ba5b] | 227 | #define sparc_get_tbr( _tbr ) \ |
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| 228 | do { \ |
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| 229 | (_tbr) = 0; /* to avoid unitialized warnings */ \ |
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[e4a2a21f] | 230 | __asm__ volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ |
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[7908ba5b] | 231 | } while ( 0 ) |
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| 232 | |
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[8df1f408] | 233 | #endif /* RTEMS_PARAVIRT */ |
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| 234 | |
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[4bafde5] | 235 | /** |
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[1362b7a] | 236 | * @brief Macro to set the TBR. |
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[4bafde5] | 237 | * |
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[1362b7a] | 238 | * This macro sets the TBR register to the value in @a _tbr. |
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[4bafde5] | 239 | */ |
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[8df1f408] | 240 | #if defined(RTEMS_PARAVIRT) |
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| 241 | |
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| 242 | void _SPARC_Set_TBR( uint32_t new_tbr ); |
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| 243 | |
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| 244 | #define sparc_set_tbr( _tbr ) \ |
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| 245 | _SPARC_Set_TBR((_tbr)) |
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| 246 | |
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| 247 | #else /* RTEMS_PARAVIRT */ |
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| 248 | |
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[7908ba5b] | 249 | #define sparc_set_tbr( _tbr ) \ |
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| 250 | do { \ |
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[e4a2a21f] | 251 | __asm__ volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ |
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[7908ba5b] | 252 | } while ( 0 ) |
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| 253 | |
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[8df1f408] | 254 | #endif /* RTEMS_PARAVIRT */ |
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| 255 | |
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[4bafde5] | 256 | /** |
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[1362b7a] | 257 | * @brief Macro to obtain the WIM. |
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[4bafde5] | 258 | * |
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[1362b7a] | 259 | * This macro returns the current contents of the WIM field in @a _wim. |
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[7908ba5b] | 260 | */ |
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| 261 | #define sparc_get_wim( _wim ) \ |
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| 262 | do { \ |
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[e4a2a21f] | 263 | __asm__ volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ |
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[7908ba5b] | 264 | } while ( 0 ) |
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| 265 | |
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[4bafde5] | 266 | /** |
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[1362b7a] | 267 | * @brief Macro to set the WIM. |
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[4bafde5] | 268 | * |
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[1362b7a] | 269 | * This macro sets the WIM field to the value in @a _wim. |
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[4bafde5] | 270 | */ |
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[7908ba5b] | 271 | #define sparc_set_wim( _wim ) \ |
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| 272 | do { \ |
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[e4a2a21f] | 273 | __asm__ volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ |
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[7908ba5b] | 274 | nop(); \ |
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| 275 | nop(); \ |
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| 276 | nop(); \ |
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| 277 | } while ( 0 ) |
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| 278 | |
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[4bafde5] | 279 | /** |
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[1362b7a] | 280 | * @brief Macro to obtain the Y register. |
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[4bafde5] | 281 | * |
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[1362b7a] | 282 | * This macro returns the current contents of the Y register in @a _y. |
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[7908ba5b] | 283 | */ |
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| 284 | #define sparc_get_y( _y ) \ |
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| 285 | do { \ |
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[e4a2a21f] | 286 | __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ |
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[7908ba5b] | 287 | } while ( 0 ) |
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[80f7732] | 288 | |
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[4bafde5] | 289 | /** |
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[1362b7a] | 290 | * @brief Macro to set the Y register. |
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[4bafde5] | 291 | * |
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[1362b7a] | 292 | * This macro sets the Y register to the value in @a _y. |
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[4bafde5] | 293 | */ |
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[7908ba5b] | 294 | #define sparc_set_y( _y ) \ |
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| 295 | do { \ |
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[e4a2a21f] | 296 | __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ |
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[7908ba5b] | 297 | } while ( 0 ) |
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| 298 | |
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[4bafde5] | 299 | /** |
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[1362b7a] | 300 | * @brief SPARC disable processor interrupts. |
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[4bafde5] | 301 | * |
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[1362b7a] | 302 | * This method is invoked to disable all maskable interrupts. |
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[4bafde5] | 303 | * |
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[1362b7a] | 304 | * @return This method returns the entire PSR contents. |
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[7908ba5b] | 305 | */ |
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[dff1803] | 306 | static inline uint32_t sparc_disable_interrupts(void) |
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| 307 | { |
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| 308 | register uint32_t psr __asm__("g1"); /* return value of trap handler */ |
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| 309 | __asm__ volatile ( "ta %1\n\t" : "=r" (psr) : "i" (SPARC_SWTRAP_IRQDIS)); |
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| 310 | return psr; |
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| 311 | } |
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[80f7732] | 312 | |
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[4bafde5] | 313 | /** |
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[1362b7a] | 314 | * @brief SPARC enable processor interrupts. |
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[4bafde5] | 315 | * |
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[1362b7a] | 316 | * This method is invoked to enable all maskable interrupts. |
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[4bafde5] | 317 | * |
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[1362b7a] | 318 | * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. |
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[4bafde5] | 319 | */ |
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[dff1803] | 320 | static inline void sparc_enable_interrupts(uint32_t psr) |
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| 321 | { |
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| 322 | register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ |
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| 323 | __asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); |
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| 324 | } |
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[4bafde5] | 325 | |
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[6a740c2] | 326 | /** |
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| 327 | * @brief SPARC exit through system call 1 |
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| 328 | * |
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| 329 | * This method is invoked to go into system error halt. The optional |
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| 330 | * arguments can be given to hypervisor, hardware debugger, simulator or |
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| 331 | * similar. |
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| 332 | * |
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| 333 | * System error mode is entered when taking a trap when traps have been |
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| 334 | * disabled. What happens when error mode is entered depends on the motherboard. |
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| 335 | * In a typical development systems the CPU relingish control to the debugger, |
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| 336 | * simulator, hypervisor or similar. The following steps are taken: |
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| 337 | * |
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| 338 | * 1. Going into system error mode by Software Trap 0 |
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| 339 | * 2. %g1=1 (syscall 1 - Exit) |
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| 340 | * 3. %g2=Primary exit code |
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| 341 | * 4. %g3=Secondary exit code. Dependends on %g2 exit type. |
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| 342 | * |
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| 343 | * This function never returns. |
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| 344 | * |
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| 345 | * @param[in] exitcode1 Primary exit code stored in CPU g2 register after exit |
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| 346 | * @param[in] exitcode2 Primary exit code stored in CPU g3 register after exit |
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| 347 | */ |
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| 348 | void sparc_syscall_exit(uint32_t exitcode1, uint32_t exitcode2) |
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| 349 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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| 350 | |
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[4bafde5] | 351 | /** |
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[1362b7a] | 352 | * @brief SPARC flash processor interrupts. |
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[4bafde5] | 353 | * |
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[1362b7a] | 354 | * This method is invoked to temporarily enable all maskable interrupts. |
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[4bafde5] | 355 | * |
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[1362b7a] | 356 | * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts. |
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[4bafde5] | 357 | */ |
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| 358 | #define sparc_flash_interrupts( _psr ) \ |
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[7908ba5b] | 359 | do { \ |
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[4bafde5] | 360 | sparc_enable_interrupts( (_psr) ); \ |
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| 361 | _psr = sparc_disable_interrupts(); \ |
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[7908ba5b] | 362 | } while ( 0 ) |
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| 363 | |
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[4bafde5] | 364 | /** |
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[1362b7a] | 365 | * @brief SPARC obtain interrupt level. |
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[4bafde5] | 366 | * |
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[1362b7a] | 367 | * This method is invoked to obtain the current interrupt disable level. |
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[4bafde5] | 368 | * |
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[1362b7a] | 369 | * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts. |
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[4bafde5] | 370 | */ |
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[7908ba5b] | 371 | #define sparc_get_interrupt_level( _level ) \ |
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| 372 | do { \ |
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[2a0a6851] | 373 | register uint32_t _psr_level = 0; \ |
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[7908ba5b] | 374 | \ |
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| 375 | sparc_get_psr( _psr_level ); \ |
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| 376 | (_level) = \ |
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| 377 | (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ |
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| 378 | } while ( 0 ) |
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| 379 | |
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[ad56361] | 380 | static inline uint32_t _LEON3_Get_current_processor( void ) |
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| 381 | { |
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| 382 | uint32_t asr17; |
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| 383 | |
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[47d60134] | 384 | __asm__ volatile ( |
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[ad56361] | 385 | "rd %%asr17, %0" |
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| 386 | : "=&r" (asr17) |
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| 387 | ); |
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| 388 | |
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| 389 | return asr17 >> LEON3_ASR17_PROCESSOR_INDEX_SHIFT; |
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| 390 | } |
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| 391 | |
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[7908ba5b] | 392 | #endif |
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| 393 | |
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| 394 | #ifdef __cplusplus |
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| 395 | } |
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| 396 | #endif |
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| 397 | |
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[f6ed46df] | 398 | #endif /* _RTEMS_SCORE_SPARC_H */ |
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