[7908ba5b] | 1 | /* sparc.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the SPARC |
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| 4 | * processor family. |
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| 5 | * |
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[08311cc3] | 6 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[85ab70f] | 11 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef _INCLUDE_SPARC_h |
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| 17 | #define _INCLUDE_SPARC_h |
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| 18 | |
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| 19 | #ifdef __cplusplus |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |
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| 23 | /* |
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| 24 | * This file contains the information required to build |
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| 25 | * RTEMS for a particular member of the "sparc" family. It does |
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| 26 | * this by setting variables to indicate which implementation |
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| 27 | * dependent features are present in a particular member |
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| 28 | * of the family. |
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| 29 | * |
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| 30 | * Currently recognized feature flags: |
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| 31 | * |
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| 32 | * + SPARC_HAS_FPU |
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| 33 | * 0 - no HW FPU |
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| 34 | * 1 - has HW FPU (assumed to be compatible w/90C602) |
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| 35 | * |
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| 36 | * + SPARC_HAS_BITSCAN |
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| 37 | * 0 - does not have scan instructions |
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| 38 | * 1 - has scan instruction (not currently implemented) |
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| 39 | * |
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| 40 | * + SPARC_NUMBER_OF_REGISTER_WINDOWS |
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| 41 | * 8 is the most common number supported by SPARC implementations. |
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| 42 | * SPARC_PSR_CWP_MASK is derived from this value. |
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| 43 | */ |
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| 44 | |
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[df49c60] | 45 | /* |
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[4159370] | 46 | * Some higher end SPARCs have a bitscan instructions. It would |
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| 47 | * be nice to take advantage of them. Right now, there is no |
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| 48 | * port to a CPU model with this feature and no (untested) code |
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| 49 | * that is based on this feature flag. |
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[df49c60] | 50 | */ |
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| 51 | |
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| 52 | #define SPARC_HAS_BITSCAN 0 |
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| 53 | |
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[4159370] | 54 | /* |
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| 55 | * This should be OK until a port to a higher end SPARC processor |
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| 56 | * is made that has more than 8 register windows. If this cannot |
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| 57 | * be determined based on multilib settings (v7/v8/v9), then the |
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| 58 | * cpu_asm.S code that depends on this will have to move to libcpu. |
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| 59 | */ |
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| 60 | |
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[7908ba5b] | 61 | #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 |
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| 62 | |
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[4159370] | 63 | /* |
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| 64 | * This should be determined based on some soft float derived |
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| 65 | * cpp predefine but gcc does not currently give us that information. |
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| 66 | */ |
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| 67 | |
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[477e2d19] | 68 | |
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| 69 | #if defined(_SOFT_FLOAT) |
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| 70 | #define SPARC_HAS_FPU 0 |
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| 71 | #else |
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| 72 | #define SPARC_HAS_FPU 1 |
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| 73 | #endif |
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[4159370] | 74 | |
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| 75 | #if SPARC_HAS_FPU |
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| 76 | #define CPU_MODEL_NAME "w/FPU" |
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[7908ba5b] | 77 | #else |
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[4159370] | 78 | #define CPU_MODEL_NAME "w/soft-float" |
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[7908ba5b] | 79 | #endif |
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| 80 | |
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| 81 | /* |
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| 82 | * Define the name of the CPU family. |
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| 83 | */ |
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| 84 | |
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| 85 | #define CPU_NAME "SPARC" |
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| 86 | |
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| 87 | /* |
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| 88 | * Miscellaneous constants |
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| 89 | */ |
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| 90 | |
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| 91 | /* |
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| 92 | * PSR masks and starting bit positions |
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| 93 | * |
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| 94 | * NOTE: Reserved bits are ignored. |
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| 95 | */ |
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| 96 | |
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| 97 | #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) |
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| 98 | #define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ |
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| 99 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) |
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| 100 | #define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ |
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| 101 | #elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) |
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| 102 | #define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ |
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| 103 | #else |
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| 104 | #error "Unsupported number of register windows for this cpu" |
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| 105 | #endif |
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| 106 | |
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| 107 | #define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ |
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| 108 | #define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ |
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| 109 | #define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ |
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| 110 | #define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ |
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| 111 | #define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ |
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| 112 | #define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ |
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| 113 | #define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ |
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| 114 | #define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ |
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| 115 | #define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ |
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| 116 | |
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| 117 | #define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ |
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| 118 | #define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ |
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| 119 | #define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ |
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| 120 | #define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ |
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| 121 | #define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ |
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| 122 | #define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ |
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| 123 | #define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ |
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| 124 | #define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ |
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| 125 | #define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ |
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| 126 | #define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ |
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| 127 | |
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| 128 | #ifndef ASM |
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| 129 | |
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| 130 | /* |
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| 131 | * Standard nop |
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| 132 | */ |
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| 133 | |
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| 134 | #define nop() \ |
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| 135 | do { \ |
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| 136 | asm volatile ( "nop" ); \ |
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| 137 | } while ( 0 ) |
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| 138 | |
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| 139 | /* |
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| 140 | * Get and set the PSR |
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| 141 | */ |
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| 142 | |
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| 143 | #define sparc_get_psr( _psr ) \ |
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| 144 | do { \ |
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| 145 | (_psr) = 0; \ |
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| 146 | asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ |
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| 147 | } while ( 0 ) |
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| 148 | |
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| 149 | #define sparc_set_psr( _psr ) \ |
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| 150 | do { \ |
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| 151 | asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ |
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| 152 | nop(); \ |
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| 153 | nop(); \ |
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| 154 | nop(); \ |
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| 155 | } while ( 0 ) |
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| 156 | |
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| 157 | /* |
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| 158 | * Get and set the TBR |
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| 159 | */ |
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| 160 | |
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| 161 | #define sparc_get_tbr( _tbr ) \ |
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| 162 | do { \ |
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| 163 | (_tbr) = 0; /* to avoid unitialized warnings */ \ |
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| 164 | asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ |
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| 165 | } while ( 0 ) |
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| 166 | |
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| 167 | #define sparc_set_tbr( _tbr ) \ |
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| 168 | do { \ |
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| 169 | asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ |
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| 170 | } while ( 0 ) |
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| 171 | |
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| 172 | /* |
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| 173 | * Get and set the WIM |
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| 174 | */ |
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| 175 | |
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| 176 | #define sparc_get_wim( _wim ) \ |
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| 177 | do { \ |
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| 178 | asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ |
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| 179 | } while ( 0 ) |
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| 180 | |
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| 181 | #define sparc_set_wim( _wim ) \ |
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| 182 | do { \ |
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| 183 | asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ |
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| 184 | nop(); \ |
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| 185 | nop(); \ |
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| 186 | nop(); \ |
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| 187 | } while ( 0 ) |
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| 188 | |
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| 189 | /* |
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| 190 | * Get and set the Y |
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| 191 | */ |
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| 192 | |
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| 193 | #define sparc_get_y( _y ) \ |
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| 194 | do { \ |
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| 195 | asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ |
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| 196 | } while ( 0 ) |
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| 197 | |
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| 198 | #define sparc_set_y( _y ) \ |
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| 199 | do { \ |
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| 200 | asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ |
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| 201 | } while ( 0 ) |
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| 202 | |
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| 203 | /* |
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| 204 | * Manipulate the interrupt level in the psr |
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| 205 | * |
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| 206 | */ |
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| 207 | |
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[b73e57b] | 208 | /* |
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[7908ba5b] | 209 | #define sparc_disable_interrupts( _level ) \ |
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| 210 | do { \ |
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| 211 | register unsigned int _newlevel; \ |
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| 212 | \ |
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| 213 | sparc_get_psr( _level ); \ |
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| 214 | (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \ |
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| 215 | sparc_set_psr( _newlevel ); \ |
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| 216 | } while ( 0 ) |
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[b73e57b] | 217 | |
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[7908ba5b] | 218 | #define sparc_enable_interrupts( _level ) \ |
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| 219 | do { \ |
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| 220 | unsigned int _tmp; \ |
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| 221 | \ |
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| 222 | sparc_get_psr( _tmp ); \ |
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| 223 | _tmp &= ~SPARC_PSR_PIL_MASK; \ |
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| 224 | _tmp |= (_level) & SPARC_PSR_PIL_MASK; \ |
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| 225 | sparc_set_psr( _tmp ); \ |
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| 226 | } while ( 0 ) |
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[b73e57b] | 227 | */ |
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[7908ba5b] | 228 | |
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| 229 | #define sparc_flash_interrupts( _level ) \ |
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| 230 | do { \ |
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| 231 | register unsigned32 _ignored = 0; \ |
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| 232 | \ |
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| 233 | sparc_enable_interrupts( (_level) ); \ |
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| 234 | sparc_disable_interrupts( _ignored ); \ |
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| 235 | } while ( 0 ) |
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| 236 | |
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[b73e57b] | 237 | /* |
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[7908ba5b] | 238 | #define sparc_set_interrupt_level( _new_level ) \ |
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| 239 | do { \ |
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| 240 | register unsigned32 _new_psr_level = 0; \ |
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| 241 | \ |
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| 242 | sparc_get_psr( _new_psr_level ); \ |
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| 243 | _new_psr_level &= ~SPARC_PSR_PIL_MASK; \ |
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| 244 | _new_psr_level |= \ |
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| 245 | (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \ |
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| 246 | sparc_set_psr( _new_psr_level ); \ |
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| 247 | } while ( 0 ) |
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[b73e57b] | 248 | */ |
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[7908ba5b] | 249 | |
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| 250 | #define sparc_get_interrupt_level( _level ) \ |
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| 251 | do { \ |
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| 252 | register unsigned32 _psr_level = 0; \ |
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| 253 | \ |
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| 254 | sparc_get_psr( _psr_level ); \ |
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| 255 | (_level) = \ |
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| 256 | (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ |
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| 257 | } while ( 0 ) |
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| 258 | |
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| 259 | #endif |
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| 260 | |
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| 261 | #ifdef __cplusplus |
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| 262 | } |
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| 263 | #endif |
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| 264 | |
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| 265 | #endif /* ! _INCLUDE_SPARC_h */ |
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| 266 | /* end of include file */ |
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