1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief CPU Port Implementation API |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR) |
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9 | * Copyright (c) 2013, 2016 embedded brains GmbH |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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17 | #define _RTEMS_SCORE_CPUIMPL_H |
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18 | |
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19 | #include <rtems/score/cpu.h> |
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20 | |
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21 | /** This defines the size of the minimum stack frame. */ |
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22 | #define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60 |
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23 | |
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24 | /* |
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25 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
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26 | */ |
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27 | |
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28 | /** This macro defines an offset into the ISF for use in assembly. */ |
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29 | #define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00 |
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30 | /** This macro defines an offset into the ISF for use in assembly. */ |
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31 | #define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04 |
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32 | /** This macro defines an offset into the ISF for use in assembly. */ |
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33 | #define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08 |
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34 | /** This macro defines an offset into the ISF for use in assembly. */ |
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35 | #define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c |
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36 | /** This macro defines an offset into the ISF for use in assembly. */ |
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37 | #define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10 |
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38 | /** This macro defines an offset into the ISF for use in assembly. */ |
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39 | #define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14 |
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40 | /** This macro defines an offset into the ISF for use in assembly. */ |
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41 | #define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18 |
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42 | /** This macro defines an offset into the ISF for use in assembly. */ |
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43 | #define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c |
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44 | /** This macro defines an offset into the ISF for use in assembly. */ |
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45 | #define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24 |
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46 | /** This macro defines an offset into the ISF for use in assembly. */ |
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47 | #define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28 |
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48 | /** This macro defines an offset into the ISF for use in assembly. */ |
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49 | #define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c |
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50 | /** This macro defines an offset into the ISF for use in assembly. */ |
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51 | #define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30 |
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52 | /** This macro defines an offset into the ISF for use in assembly. */ |
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53 | #define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34 |
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54 | /** This macro defines an offset into the ISF for use in assembly. */ |
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55 | #define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38 |
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56 | /** This macro defines an offset into the ISF for use in assembly. */ |
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57 | #define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c |
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58 | /** This macro defines an offset into the ISF for use in assembly. */ |
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59 | #define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40 |
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60 | /** This macro defines an offset into the ISF for use in assembly. */ |
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61 | #define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44 |
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62 | /** This macro defines an offset into the ISF for use in assembly. */ |
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63 | #define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48 |
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64 | /** This macro defines an offset into the ISF for use in assembly. */ |
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65 | #define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c |
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66 | |
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67 | /** This defines the size of the ISF area for use in assembly. */ |
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68 | #define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50 |
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69 | |
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70 | #if ( SPARC_HAS_FPU == 1 ) |
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71 | #define CPU_PER_CPU_CONTROL_SIZE 8 |
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72 | #else |
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73 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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74 | #endif |
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75 | |
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76 | #if ( SPARC_HAS_FPU == 1 ) |
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77 | /** |
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78 | * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the |
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79 | * Per_CPU_Control begin. |
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80 | */ |
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81 | #define SPARC_PER_CPU_FSR_OFFSET 0 |
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82 | #endif |
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83 | |
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84 | #ifndef ASM |
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85 | |
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86 | #ifdef __cplusplus |
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87 | extern "C" { |
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88 | #endif |
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89 | |
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90 | typedef struct { |
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91 | #if ( SPARC_HAS_FPU == 1 ) |
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92 | /** |
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93 | * @brief Memory location to store the FSR register during interrupt |
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94 | * processing. |
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95 | * |
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96 | * This is a write-only field. The FSR is written to force a completion of |
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97 | * floating point operations in progress. |
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98 | */ |
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99 | uint32_t fsr; |
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100 | |
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101 | /* See Per_CPU_Control::Interrupt_frame */ |
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102 | uint32_t reserved_for_alignment_of_interrupt_frame; |
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103 | #endif |
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104 | } CPU_Per_CPU_control; |
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105 | |
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106 | /** |
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107 | * @brief The pointer to the current per-CPU control is available via register |
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108 | * g6. |
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109 | */ |
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110 | register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); |
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111 | |
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112 | #define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current |
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113 | |
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114 | #define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing ) |
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115 | |
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116 | #ifdef __cplusplus |
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117 | } |
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118 | #endif |
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119 | |
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120 | #endif /* ASM */ |
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121 | |
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122 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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