source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ e9dba243

4.104.114.9
Last change on this file since e9dba243 was e9dba243, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 4, 2008 at 7:51:27 PM

2008-08-04 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Spacing.
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File size: 28.9 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the port of
7 *  the executive to the SPARC processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/sparc.h>               /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33/*
34 *  Should the calls to _Thread_Enable_dispatch be inlined?
35 *
36 *  If TRUE, then they are inlined.
37 *  If FALSE, then a subroutine call is made.
38 */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41
42/*
43 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
44 *  be unrolled one time?  In unrolled each iteration of the loop examines
45 *  two "nodes" on the chain being searched.  Otherwise, only one node
46 *  is examined per iteration.
47 *
48 *  If TRUE, then the loops are unrolled.
49 *  If FALSE, then the loops are not unrolled.
50 *
51 *  This parameter could go either way on the SPARC.  The interrupt flash
52 *  code is relatively lengthy given the requirements for nops following
53 *  writes to the psr.  But if the clock speed were high enough, this would
54 *  not represent a great deal of time.
55 */
56
57#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
58
59/*
60 *  Does the executive manage a dedicated interrupt stack in software?
61 *
62 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
63 *  If FALSE, nothing is done.
64 *
65 *  The SPARC does not have a dedicated HW interrupt stack and one has
66 *  been implemented in SW.
67 */
68
69#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
70
71/*
72 *  Does the CPU follow the simple vectored interrupt model?
73 *
74 *  If TRUE, then RTEMS allocates the vector table it internally manages.
75 *  If FALSE, then the BSP is assumed to allocate and manage the vector
76 *  table
77 *
78 *  SPARC Specific Information:
79 *
80 *  XXX document implementation including references if appropriate
81 */
82#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
83
84/*
85 *  Does this CPU have hardware support for a dedicated interrupt stack?
86 *
87 *  If TRUE, then it must be installed during initialization.
88 *  If FALSE, then no installation is performed.
89 *
90 *  The SPARC does not have a dedicated HW interrupt stack.
91 */
92
93#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
94
95/*
96 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
97 *
98 *  If TRUE, then the memory is allocated during initialization.
99 *  If FALSE, then the memory is allocated during initialization.
100 */
101
102#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
103
104/*
105 *  Does the RTEMS invoke the user's ISR with the vector number and
106 *  a pointer to the saved interrupt frame (1) or just the vector
107 *  number (0)?
108 */
109
110#define CPU_ISR_PASSES_FRAME_POINTER 0
111
112/*
113 *  Does the CPU have hardware floating point?
114 *
115 *  If TRUE, then the FLOATING_POINT task attribute is supported.
116 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
117 */
118
119#if ( SPARC_HAS_FPU == 1 )
120#define CPU_HARDWARE_FP     TRUE
121#else
122#define CPU_HARDWARE_FP     FALSE
123#endif
124#define CPU_SOFTWARE_FP     FALSE
125
126/*
127 *  Are all tasks FLOATING_POINT tasks implicitly?
128 *
129 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
130 *  If FALSE, then the FLOATING_POINT task attribute is followed.
131 */
132
133#define CPU_ALL_TASKS_ARE_FP     FALSE
134
135/*
136 *  Should the IDLE task have a floating point context?
137 *
138 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
139 *  and it has a floating point context which is switched in and out.
140 *  If FALSE, then the IDLE task does not have a floating point context.
141 */
142
143#define CPU_IDLE_TASK_IS_FP      FALSE
144
145/*
146 *  Should the saving of the floating point registers be deferred
147 *  until a context switch is made to another different floating point
148 *  task?
149 *
150 *  If TRUE, then the floating point context will not be stored until
151 *  necessary.  It will remain in the floating point registers and not
152 *  disturned until another floating point task is switched to.
153 *
154 *  If FALSE, then the floating point context is saved when a floating
155 *  point task is switched out and restored when the next floating point
156 *  task is restored.  The state of the floating point registers between
157 *  those two operations is not specified.
158 */
159
160#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
161
162/*
163 *  Does this port provide a CPU dependent IDLE task implementation?
164 *
165 *  If TRUE, then the routine _CPU_Thread_Idle_body
166 *  must be provided and is the default IDLE thread body instead of
167 *  _CPU_Thread_Idle_body.
168 *
169 *  If FALSE, then use the generic IDLE thread body if the BSP does
170 *  not provide one.
171 */
172
173#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
174
175/*
176 *  Does the stack grow up (toward higher addresses) or down
177 *  (toward lower addresses)?
178 *
179 *  If TRUE, then the grows upward.
180 *  If FALSE, then the grows toward smaller addresses.
181 *
182 *  The stack grows to lower addresses on the SPARC.
183 */
184
185#define CPU_STACK_GROWS_UP               FALSE
186
187/*
188 *  The following is the variable attribute used to force alignment
189 *  of critical data structures.  On some processors it may make
190 *  sense to have these aligned on tighter boundaries than
191 *  the minimum requirements of the compiler in order to have as
192 *  much of the critical data area as possible in a cache line.
193 *
194 *  The SPARC does not appear to have particularly strict alignment
195 *  requirements.  This value was chosen to take advantages of caches.
196 */
197
198#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
199
200/*
201 *  Define what is required to specify how the network to host conversion
202 *  routines are handled.
203 */
204
205#define CPU_BIG_ENDIAN                           TRUE
206#define CPU_LITTLE_ENDIAN                        FALSE
207
208/*
209 *  The following defines the number of bits actually used in the
210 *  interrupt field of the task mode.  How those bits map to the
211 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
212 *
213 *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
214 */
215
216#define CPU_MODES_INTERRUPT_MASK   0x0000000F
217
218/*
219 *  This structure represents the organization of the minimum stack frame
220 *  for the SPARC.  More framing information is required in certain situaions
221 *  such as when there are a large number of out parameters or when the callee
222 *  must save floating point registers.
223 */
224
225#ifndef ASM
226
227typedef struct {
228  uint32_t    l0;
229  uint32_t    l1;
230  uint32_t    l2;
231  uint32_t    l3;
232  uint32_t    l4;
233  uint32_t    l5;
234  uint32_t    l6;
235  uint32_t    l7;
236  uint32_t    i0;
237  uint32_t    i1;
238  uint32_t    i2;
239  uint32_t    i3;
240  uint32_t    i4;
241  uint32_t    i5;
242  uint32_t    i6_fp;
243  uint32_t    i7;
244  void       *structure_return_address;
245  /*
246   *  The following are for the callee to save the register arguments in
247   *  should this be necessary.
248   */
249  uint32_t    saved_arg0;
250  uint32_t    saved_arg1;
251  uint32_t    saved_arg2;
252  uint32_t    saved_arg3;
253  uint32_t    saved_arg4;
254  uint32_t    saved_arg5;
255  uint32_t    pad0;
256}  CPU_Minimum_stack_frame;
257
258#endif /* ASM */
259
260#define CPU_STACK_FRAME_L0_OFFSET             0x00
261#define CPU_STACK_FRAME_L1_OFFSET             0x04
262#define CPU_STACK_FRAME_L2_OFFSET             0x08
263#define CPU_STACK_FRAME_L3_OFFSET             0x0c
264#define CPU_STACK_FRAME_L4_OFFSET             0x10
265#define CPU_STACK_FRAME_L5_OFFSET             0x14
266#define CPU_STACK_FRAME_L6_OFFSET             0x18
267#define CPU_STACK_FRAME_L7_OFFSET             0x1c
268#define CPU_STACK_FRAME_I0_OFFSET             0x20
269#define CPU_STACK_FRAME_I1_OFFSET             0x24
270#define CPU_STACK_FRAME_I2_OFFSET             0x28
271#define CPU_STACK_FRAME_I3_OFFSET             0x2c
272#define CPU_STACK_FRAME_I4_OFFSET             0x30
273#define CPU_STACK_FRAME_I5_OFFSET             0x34
274#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
275#define CPU_STACK_FRAME_I7_OFFSET             0x3c
276#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
277#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
278#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
279#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
280#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
281#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
282#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
283#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
284
285#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
286
287/*
288 * Contexts
289 *
290 *  Generally there are 2 types of context to save.
291 *     1. Interrupt registers to save
292 *     2. Task level registers to save
293 *
294 *  This means we have the following 3 context items:
295 *     1. task level context stuff::  Context_Control
296 *     2. floating point task stuff:: Context_Control_fp
297 *     3. special interrupt level context :: Context_Control_interrupt
298 *
299 *  On the SPARC, we are relatively conservative in that we save most
300 *  of the CPU state in the context area.  The ET (enable trap) bit and
301 *  the CWP (current window pointer) fields of the PSR are considered
302 *  system wide resources and are not maintained on a per-thread basis.
303 */
304
305#ifndef ASM
306
307typedef struct {
308    /*
309     *  Using a double g0_g1 will put everything in this structure on a
310     *  double word boundary which allows us to use double word loads
311     *  and stores safely in the context switch.
312     */
313    double     g0_g1;
314    uint32_t   g2;
315    uint32_t   g3;
316    uint32_t   g4;
317    uint32_t   g5;
318    uint32_t   g6;
319    uint32_t   g7;
320
321    uint32_t   l0;
322    uint32_t   l1;
323    uint32_t   l2;
324    uint32_t   l3;
325    uint32_t   l4;
326    uint32_t   l5;
327    uint32_t   l6;
328    uint32_t   l7;
329
330    uint32_t   i0;
331    uint32_t   i1;
332    uint32_t   i2;
333    uint32_t   i3;
334    uint32_t   i4;
335    uint32_t   i5;
336    uint32_t   i6_fp;
337    uint32_t   i7;
338
339    uint32_t   o0;
340    uint32_t   o1;
341    uint32_t   o2;
342    uint32_t   o3;
343    uint32_t   o4;
344    uint32_t   o5;
345    uint32_t   o6_sp;
346    uint32_t   o7;
347
348    uint32_t   psr;
349    uint32_t   isr_dispatch_disable;
350} Context_Control;
351
352#define _CPU_Context_Get_SP( _context ) \
353  (_context)->o6_sp
354
355#endif /* ASM */
356
357/*
358 *  Offsets of fields with Context_Control for assembly routines.
359 */
360
361#define G0_OFFSET    0x00
362#define G1_OFFSET    0x04
363#define G2_OFFSET    0x08
364#define G3_OFFSET    0x0C
365#define G4_OFFSET    0x10
366#define G5_OFFSET    0x14
367#define G6_OFFSET    0x18
368#define G7_OFFSET    0x1C
369
370#define L0_OFFSET    0x20
371#define L1_OFFSET    0x24
372#define L2_OFFSET    0x28
373#define L3_OFFSET    0x2C
374#define L4_OFFSET    0x30
375#define L5_OFFSET    0x34
376#define L6_OFFSET    0x38
377#define L7_OFFSET    0x3C
378
379#define I0_OFFSET    0x40
380#define I1_OFFSET    0x44
381#define I2_OFFSET    0x48
382#define I3_OFFSET    0x4C
383#define I4_OFFSET    0x50
384#define I5_OFFSET    0x54
385#define I6_FP_OFFSET 0x58
386#define I7_OFFSET    0x5C
387
388#define O0_OFFSET    0x60
389#define O1_OFFSET    0x64
390#define O2_OFFSET    0x68
391#define O3_OFFSET    0x6C
392#define O4_OFFSET    0x70
393#define O5_OFFSET    0x74
394#define O6_SP_OFFSET 0x78
395#define O7_OFFSET    0x7C
396
397#define PSR_OFFSET   0x80
398#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
399
400#define CONTEXT_CONTROL_SIZE 0x88
401
402/*
403 *  The floating point context area.
404 */
405
406#ifndef ASM
407
408typedef struct {
409    double      f0_f1;
410    double      f2_f3;
411    double      f4_f5;
412    double      f6_f7;
413    double      f8_f9;
414    double      f10_f11;
415    double      f12_f13;
416    double      f14_f15;
417    double      f16_f17;
418    double      f18_f19;
419    double      f20_f21;
420    double      f22_f23;
421    double      f24_f25;
422    double      f26_f27;
423    double      f28_f29;
424    double      f30_f31;
425    uint32_t    fsr;
426} Context_Control_fp;
427
428#endif /* ASM */
429
430/*
431 *  Offsets of fields with Context_Control_fp for assembly routines.
432 */
433
434#define FO_F1_OFFSET     0x00
435#define F2_F3_OFFSET     0x08
436#define F4_F5_OFFSET     0x10
437#define F6_F7_OFFSET     0x18
438#define F8_F9_OFFSET     0x20
439#define F1O_F11_OFFSET   0x28
440#define F12_F13_OFFSET   0x30
441#define F14_F15_OFFSET   0x38
442#define F16_F17_OFFSET   0x40
443#define F18_F19_OFFSET   0x48
444#define F2O_F21_OFFSET   0x50
445#define F22_F23_OFFSET   0x58
446#define F24_F25_OFFSET   0x60
447#define F26_F27_OFFSET   0x68
448#define F28_F29_OFFSET   0x70
449#define F3O_F31_OFFSET   0x78
450#define FSR_OFFSET       0x80
451
452#define CONTEXT_CONTROL_FP_SIZE 0x84
453
454#ifndef ASM
455
456/*
457 *  Context saved on stack for an interrupt.
458 *
459 *  NOTE:  The PSR, PC, and NPC are only saved in this structure for the
460 *         benefit of the user's handler.
461 */
462
463typedef struct {
464  CPU_Minimum_stack_frame  Stack_frame;
465  uint32_t                 psr;
466  uint32_t                 pc;
467  uint32_t                 npc;
468  uint32_t                 g1;
469  uint32_t                 g2;
470  uint32_t                 g3;
471  uint32_t                 g4;
472  uint32_t                 g5;
473  uint32_t                 g6;
474  uint32_t                 g7;
475  uint32_t                 i0;
476  uint32_t                 i1;
477  uint32_t                 i2;
478  uint32_t                 i3;
479  uint32_t                 i4;
480  uint32_t                 i5;
481  uint32_t                 i6_fp;
482  uint32_t                 i7;
483  uint32_t                 y;
484  uint32_t                 tpc;
485} CPU_Interrupt_frame;
486
487#endif /* ASM */
488
489/*
490 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
491 */
492
493#define ISF_STACK_FRAME_OFFSET 0x00
494#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
495#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
496#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
497#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
498#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
499#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
500#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
501#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
502#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
503#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
504#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
505#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
506#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
507#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
508#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
509#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
510#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
511#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
512#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
513#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
514
515#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
516#ifndef ASM
517/*
518 *  This variable is contains the initialize context for the FP unit.
519 *  It is filled in by _CPU_Initialize and copied into the task's FP
520 *  context area during _CPU_Context_Initialize.
521 */
522
523SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
524
525/*
526 *  This stack is allocated by the Interrupt Manager and the switch
527 *  is performed in _ISR_Handler.  These variables contain pointers
528 *  to the lowest and highest addresses in the chunk of memory allocated
529 *  for the interrupt stack.  Since it is unknown whether the stack
530 *  grows up or down (in general), this give the CPU dependent
531 *  code the option of picking the version it wants to use.  Thus
532 *  both must be present if either is.
533 *
534 *  The SPARC supports a software based interrupt stack and these
535 *  are required.
536 */
537
538SCORE_EXTERN void *_CPU_Interrupt_stack_low;
539SCORE_EXTERN void *_CPU_Interrupt_stack_high;
540
541/*
542 *  This flag is context switched with each thread.  It indicates
543 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
544 *  By using this flag, we can avoid nesting more interrupt dispatching
545 *  attempts on a previously interrupted thread's stack.
546 */
547
548SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
549
550/*
551 *  The following type defines an entry in the SPARC's trap table.
552 *
553 *  NOTE: The instructions chosen are RTEMS dependent although one is
554 *        obligated to use two of the four instructions to perform a
555 *        long jump.  The other instructions load one register with the
556 *        trap type (a.k.a. vector) and another with the psr.
557 */
558 
559typedef struct {
560  uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
561  uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
562  uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
563  uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
564} CPU_Trap_table_entry;
565 
566/*
567 *  This is the set of opcodes for the instructions loaded into a trap
568 *  table entry.  The routine which installs a handler is responsible
569 *  for filling in the fields for the _handler address and the _vector
570 *  trap type.
571 *
572 *  The constants following this structure are masks for the fields which
573 *  must be filled in when the handler is installed.
574 */
575 
576extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
577
578/*
579 *  The size of the floating point context area. 
580 */
581
582#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
583
584#endif
585
586/*
587 *  Amount of extra stack (above minimum stack size) required by
588 *  MPCI receive server thread.  Remember that in a multiprocessor
589 *  system this thread must exist and be able to process all directives.
590 */
591
592#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
593
594/*
595 *  This defines the number of entries in the ISR_Vector_table managed
596 *  by the executive.
597 *
598 *  On the SPARC, there are really only 256 vectors.  However, the executive
599 *  has no easy, fast, reliable way to determine which traps are synchronous
600 *  and which are asynchronous.  By default, synchronous traps return to the
601 *  instruction which caused the interrupt.  So if you install a software
602 *  trap handler as an executive interrupt handler (which is desirable since
603 *  RTEMS takes care of window and register issues), then the executive needs
604 *  to know that the return address is to the trap rather than the instruction
605 *  following the trap.
606 *
607 *  So vectors 0 through 255 are treated as regular asynchronous traps which
608 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
609 *  by the executive to be synchronous and to require that the return address
610 *  be fudged.
611 *
612 *  If you use this mechanism to install a trap handler which must reexecute
613 *  the instruction which caused the trap, then it should be installed as
614 *  an asynchronous trap.  This will avoid the executive changing the return
615 *  address.
616 */
617
618#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
619#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
620
621#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
622#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
623#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
624
625#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
626
627/*
628 *  This is defined if the port has a special way to report the ISR nesting
629 *  level.  Most ports maintain the variable _ISR_Nest_level.
630 */
631
632#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
633
634/*
635 *  Should be large enough to run all tests.  This ensures
636 *  that a "reasonable" small application should not have any problems.
637 *
638 *  This appears to be a fairly generous number for the SPARC since
639 *  represents a call depth of about 20 routines based on the minimum
640 *  stack frame.
641 */
642
643#define CPU_STACK_MINIMUM_SIZE  (1024*4)
644
645/*
646 *  CPU's worst alignment requirement for data types on a byte boundary.  This
647 *  alignment does not take into account the requirements for the stack.
648 *
649 *  On the SPARC, this is required for double word loads and stores.
650 */
651
652#define CPU_ALIGNMENT      8
653
654/*
655 *  This number corresponds to the byte alignment requirement for the
656 *  heap handler.  This alignment requirement may be stricter than that
657 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
658 *  common for the heap to follow the same alignment requirement as
659 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
660 *  then this should be set to CPU_ALIGNMENT.
661 *
662 *  NOTE:  This does not have to be a power of 2.  It does have to
663 *         be greater or equal to than CPU_ALIGNMENT.
664 */
665
666#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
667
668/*
669 *  This number corresponds to the byte alignment requirement for memory
670 *  buffers allocated by the partition manager.  This alignment requirement
671 *  may be stricter than that for the data types alignment specified by
672 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
673 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
674 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
675 *
676 *  NOTE:  This does not have to be a power of 2.  It does have to
677 *         be greater or equal to than CPU_ALIGNMENT.
678 */
679
680#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
681
682/*
683 *  This number corresponds to the byte alignment requirement for the
684 *  stack.  This alignment requirement may be stricter than that for the
685 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
686 *  is strict enough for the stack, then this should be set to 0.
687 *
688 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
689 *
690 *  The alignment restrictions for the SPARC are not that strict but this
691 *  should unsure that the stack is always sufficiently alignment that the
692 *  window overflow, underflow, and flush routines can use double word loads
693 *  and stores.
694 */
695
696#define CPU_STACK_ALIGNMENT        16
697
698#ifndef ASM
699
700extern unsigned int sparc_disable_interrupts();
701extern void sparc_enable_interrupts();
702
703/*
704 *  ISR handler macros
705 */
706
707/*
708 *  Support routine to initialize the RTEMS vector table after it is allocated.
709 */
710
711#define _CPU_Initialize_vectors()
712
713/*
714 *  Disable all interrupts for a critical section.  The previous
715 *  level is returned in _level.
716 */
717
718#define _CPU_ISR_Disable( _level ) \
719  (_level) = sparc_disable_interrupts()
720 
721/*
722 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
723 *  This indicates the end of a critical section.  The parameter
724 *  _level is not modified.
725 */
726
727#define _CPU_ISR_Enable( _level ) \
728  sparc_enable_interrupts( _level )
729
730/*
731 *  This temporarily restores the interrupt to _level before immediately
732 *  disabling them again.  This is used to divide long critical
733 *  sections into two or more parts.  The parameter _level is not
734 *  modified.
735 */
736
737#define _CPU_ISR_Flash( _level ) \
738  sparc_flash_interrupts( _level )
739 
740/*
741 *  Map interrupt level in task mode onto the hardware that the CPU
742 *  actually provides.  Currently, interrupt levels which do not
743 *  map onto the CPU in a straight fashion are undefined. 
744 */
745
746#define _CPU_ISR_Set_level( _newlevel ) \
747   sparc_enable_interrupts( _newlevel << 8)
748 
749uint32_t   _CPU_ISR_Get_level( void );
750 
751/* end of ISR handler macros */
752
753/* Context handler macros */
754
755/*
756 *  Initialize the context to a state suitable for starting a
757 *  task after a context restore operation.  Generally, this
758 *  involves:
759 *
760 *     - setting a starting address
761 *     - preparing the stack
762 *     - preparing the stack and frame pointers
763 *     - setting the proper interrupt level in the context
764 *     - initializing the floating point context
765 *
766 *  NOTE:  Implemented as a subroutine for the SPARC port.
767 */
768
769void _CPU_Context_Initialize(
770  Context_Control  *the_context,
771  uint32_t         *stack_base,
772  uint32_t          size,
773  uint32_t          new_level,
774  void             *entry_point,
775  boolean           is_fp
776);
777
778/*
779 *  This macro is invoked from _Thread_Handler to do whatever CPU
780 *  specific magic is required that must be done in the context of
781 *  the thread when it starts.
782 *
783 *  On the SPARC, this is setting the frame pointer so GDB is happy.
784 *  Make GDB stop unwinding at _Thread_Handler, previous register window
785 *  Frame pointer is 0 and calling address must be a function with starting
786 *  with a SAVE instruction. If return address is leaf-function (no SAVE)
787 *  GDB will not look at prev reg window fp.
788 *
789 *  _Thread_Handler is known to start with SAVE.
790 */
791
792#define _CPU_Context_Initialization_at_thread_begin() \
793  do { \
794    asm volatile ("set _Thread_Handler,%%i7\n"::); \
795  } while (0)
796
797/*
798 *  This routine is responsible for somehow restarting the currently
799 *  executing task. 
800 *
801 *  On the SPARC, this is is relatively painless but requires a small
802 *  amount of wrapper code before using the regular restore code in
803 *  of the context switch.
804 */
805
806#define _CPU_Context_Restart_self( _the_context ) \
807   _CPU_Context_restore( (_the_context) );
808
809/*
810 *  The FP context area for the SPARC is a simple structure and nothing
811 *  special is required to find the "starting load point"
812 */
813
814#define _CPU_Context_Fp_start( _base, _offset ) \
815   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
816
817/*
818 *  This routine initializes the FP context area passed to it to.
819 *
820 *  The SPARC allows us to use the simple initialization model
821 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
822 *  at CPU initialization and it is simply copied into the destination
823 *  context.
824 */
825
826#define _CPU_Context_Initialize_fp( _destination ) \
827  do { \
828   *(*(_destination)) = _CPU_Null_fp_context; \
829  } while (0)
830
831/* end of Context handler macros */
832
833/* Fatal Error manager macros */
834
835/*
836 *  This routine copies _error into a known place -- typically a stack
837 *  location or a register, optionally disables interrupts, and
838 *  halts/stops the CPU.
839 */
840
841#define _CPU_Fatal_halt( _error ) \
842  do { \
843    uint32_t   level; \
844    \
845    level = sparc_disable_interrupts(); \
846    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
847    while (1); /* loop forever */ \
848  } while (0)
849
850/* end of Fatal Error manager macros */
851
852/* Bitfield handler macros */
853
854/*
855 *  The SPARC port uses the generic C algorithm for bitfield scan if the
856 *  CPU model does not have a scan instruction.
857 */
858
859#if ( SPARC_HAS_BITSCAN == 0 )
860#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
861#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
862#else
863#error "scan instruction not currently supported by RTEMS!!"
864#endif
865
866/* end of Bitfield handler macros */
867
868/* Priority handler handler macros */
869
870/*
871 *  The SPARC port uses the generic C algorithm for bitfield scan if the
872 *  CPU model does not have a scan instruction.
873 */
874
875#if ( SPARC_HAS_BITSCAN == 1 )
876#error "scan instruction not currently supported by RTEMS!!"
877#endif
878
879/* end of Priority handler macros */
880
881/* functions */
882
883/*
884 *  _CPU_Initialize
885 *
886 *  This routine performs CPU dependent initialization.
887 */
888
889void _CPU_Initialize(
890  void            (*thread_dispatch)
891);
892
893/*
894 *  _CPU_ISR_install_raw_handler
895 *
896 *  This routine installs new_handler to be directly called from the trap
897 *  table.
898 */
899 
900void _CPU_ISR_install_raw_handler(
901  uint32_t    vector,
902  proc_ptr    new_handler,
903  proc_ptr   *old_handler
904);
905
906/*
907 *  _CPU_ISR_install_vector
908 *
909 *  This routine installs an interrupt vector.
910 */
911
912void _CPU_ISR_install_vector(
913  uint32_t    vector,
914  proc_ptr    new_handler,
915  proc_ptr   *old_handler
916);
917
918#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
919 
920/*
921 *  _CPU_Thread_Idle_body
922 *
923 *  Some SPARC implementations have low power, sleep, or idle modes.  This
924 *  tries to take advantage of those models.
925 */
926 
927void *_CPU_Thread_Idle_body( uint32_t );
928 
929#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
930
931/*
932 *  _CPU_Context_switch
933 *
934 *  This routine switches from the run context to the heir context.
935 */
936
937void _CPU_Context_switch(
938  Context_Control  *run,
939  Context_Control  *heir
940);
941
942/*
943 *  _CPU_Context_restore
944 *
945 *  This routine is generally used only to restart self in an
946 *  efficient manner.
947 */
948
949void _CPU_Context_restore(
950  Context_Control *new_context
951);
952
953/*
954 *  _CPU_Context_save_fp
955 *
956 *  This routine saves the floating point context passed to it.
957 */
958
959void _CPU_Context_save_fp(
960  Context_Control_fp **fp_context_ptr
961);
962
963/*
964 *  _CPU_Context_restore_fp
965 *
966 *  This routine restores the floating point context passed to it.
967 */
968
969void _CPU_Context_restore_fp(
970  Context_Control_fp **fp_context_ptr
971);
972
973/*
974 *  CPU_swap_u32
975 *
976 *  The following routine swaps the endian format of an unsigned int.
977 *  It must be static because it is referenced indirectly.
978 *
979 *  This version will work on any processor, but if you come across a better
980 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
981 *  entity as shown below is not any more efficient on the SPARC.
982 *
983 *     swap least significant two bytes with 16-bit rotate
984 *     swap upper and lower 16-bits
985 *     swap most significant two bytes with 16-bit rotate
986 *
987 *  It is not obvious how the SPARC can do significantly better than the
988 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
989 *  following code at optimization level four (i.e. -O4).
990 */
991 
992static inline uint32_t CPU_swap_u32(
993  uint32_t value
994)
995{
996  uint32_t   byte1, byte2, byte3, byte4, swapped;
997 
998  byte4 = (value >> 24) & 0xff;
999  byte3 = (value >> 16) & 0xff;
1000  byte2 = (value >> 8)  & 0xff;
1001  byte1 =  value        & 0xff;
1002 
1003  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1004  return( swapped );
1005}
1006
1007#define CPU_swap_u16( value ) \
1008  (((value&0xff) << 8) | ((value >> 8)&0xff))
1009
1010#endif /* ASM */
1011
1012#ifdef __cplusplus
1013}
1014#endif
1015
1016#endif
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