source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ b72e847b

4.8
Last change on this file since b72e847b was b72e847b, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 4, 2008 at 8:35:25 PM

2008-08-04 Joel Sherrill <joel.sherrill@…>

PR 1294/bsps

  • rtems/score/cpu.h, rtems/score/sparc.h: Correct prototype and usage of sparc_disable_interrupts.
  • Property mode set to 100644
File size: 29.2 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the port of
7 *  the executive to the SPARC processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/sparc.h>               /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33/*
34 *  Should the calls to _Thread_Enable_dispatch be inlined?
35 *
36 *  If TRUE, then they are inlined.
37 *  If FALSE, then a subroutine call is made.
38 */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41
42/*
43 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
44 *  be unrolled one time?  In unrolled each iteration of the loop examines
45 *  two "nodes" on the chain being searched.  Otherwise, only one node
46 *  is examined per iteration.
47 *
48 *  If TRUE, then the loops are unrolled.
49 *  If FALSE, then the loops are not unrolled.
50 *
51 *  This parameter could go either way on the SPARC.  The interrupt flash
52 *  code is relatively lengthy given the requirements for nops following
53 *  writes to the psr.  But if the clock speed were high enough, this would
54 *  not represent a great deal of time.
55 */
56
57#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
58
59/*
60 *  Does the executive manage a dedicated interrupt stack in software?
61 *
62 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
63 *  If FALSE, nothing is done.
64 *
65 *  The SPARC does not have a dedicated HW interrupt stack and one has
66 *  been implemented in SW.
67 */
68
69#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
70
71/*
72 *  Does this CPU have hardware support for a dedicated interrupt stack?
73 *
74 *  If TRUE, then it must be installed during initialization.
75 *  If FALSE, then no installation is performed.
76 *
77 *  The SPARC does not have a dedicated HW interrupt stack.
78 */
79
80#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
81
82/*
83 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
84 *
85 *  If TRUE, then the memory is allocated during initialization.
86 *  If FALSE, then the memory is allocated during initialization.
87 */
88
89#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
90
91/*
92 *  Does the RTEMS invoke the user's ISR with the vector number and
93 *  a pointer to the saved interrupt frame (1) or just the vector
94 *  number (0)?
95 */
96
97#define CPU_ISR_PASSES_FRAME_POINTER 0
98
99/*
100 *  Does the CPU have hardware floating point?
101 *
102 *  If TRUE, then the FLOATING_POINT task attribute is supported.
103 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
104 */
105
106#if ( SPARC_HAS_FPU == 1 )
107#define CPU_HARDWARE_FP     TRUE
108#else
109#define CPU_HARDWARE_FP     FALSE
110#endif
111#define CPU_SOFTWARE_FP     FALSE
112
113/*
114 *  Are all tasks FLOATING_POINT tasks implicitly?
115 *
116 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
117 *  If FALSE, then the FLOATING_POINT task attribute is followed.
118 */
119
120#define CPU_ALL_TASKS_ARE_FP     FALSE
121
122/*
123 *  Should the IDLE task have a floating point context?
124 *
125 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
126 *  and it has a floating point context which is switched in and out.
127 *  If FALSE, then the IDLE task does not have a floating point context.
128 */
129
130#define CPU_IDLE_TASK_IS_FP      FALSE
131
132/*
133 *  Should the saving of the floating point registers be deferred
134 *  until a context switch is made to another different floating point
135 *  task?
136 *
137 *  If TRUE, then the floating point context will not be stored until
138 *  necessary.  It will remain in the floating point registers and not
139 *  disturned until another floating point task is switched to.
140 *
141 *  If FALSE, then the floating point context is saved when a floating
142 *  point task is switched out and restored when the next floating point
143 *  task is restored.  The state of the floating point registers between
144 *  those two operations is not specified.
145 */
146
147#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
148
149/*
150 *  Does this port provide a CPU dependent IDLE task implementation?
151 *
152 *  If TRUE, then the routine _CPU_Thread_Idle_body
153 *  must be provided and is the default IDLE thread body instead of
154 *  _CPU_Thread_Idle_body.
155 *
156 *  If FALSE, then use the generic IDLE thread body if the BSP does
157 *  not provide one.
158 */
159
160#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
161
162/*
163 *  Does the stack grow up (toward higher addresses) or down
164 *  (toward lower addresses)?
165 *
166 *  If TRUE, then the grows upward.
167 *  If FALSE, then the grows toward smaller addresses.
168 *
169 *  The stack grows to lower addresses on the SPARC.
170 */
171
172#define CPU_STACK_GROWS_UP               FALSE
173
174/*
175 *  The following is the variable attribute used to force alignment
176 *  of critical data structures.  On some processors it may make
177 *  sense to have these aligned on tighter boundaries than
178 *  the minimum requirements of the compiler in order to have as
179 *  much of the critical data area as possible in a cache line.
180 *
181 *  The SPARC does not appear to have particularly strict alignment
182 *  requirements.  This value was chosen to take advantages of caches.
183 */
184
185#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
186
187/*
188 *  Define what is required to specify how the network to host conversion
189 *  routines are handled.
190 */
191
192#define CPU_BIG_ENDIAN                           TRUE
193#define CPU_LITTLE_ENDIAN                        FALSE
194
195/*
196 *  The following defines the number of bits actually used in the
197 *  interrupt field of the task mode.  How those bits map to the
198 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
199 *
200 *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
201 */
202
203#define CPU_MODES_INTERRUPT_MASK   0x0000000F
204
205/*
206 *  This structure represents the organization of the minimum stack frame
207 *  for the SPARC.  More framing information is required in certain situaions
208 *  such as when there are a large number of out parameters or when the callee
209 *  must save floating point registers.
210 */
211
212#ifndef ASM
213
214typedef struct {
215  uint32_t    l0;
216  uint32_t    l1;
217  uint32_t    l2;
218  uint32_t    l3;
219  uint32_t    l4;
220  uint32_t    l5;
221  uint32_t    l6;
222  uint32_t    l7;
223  uint32_t    i0;
224  uint32_t    i1;
225  uint32_t    i2;
226  uint32_t    i3;
227  uint32_t    i4;
228  uint32_t    i5;
229  uint32_t    i6_fp;
230  uint32_t    i7;
231  void       *structure_return_address;
232  /*
233   *  The following are for the callee to save the register arguments in
234   *  should this be necessary.
235   */
236  uint32_t    saved_arg0;
237  uint32_t    saved_arg1;
238  uint32_t    saved_arg2;
239  uint32_t    saved_arg3;
240  uint32_t    saved_arg4;
241  uint32_t    saved_arg5;
242  uint32_t    pad0;
243}  CPU_Minimum_stack_frame;
244
245#endif /* ASM */
246
247#define CPU_STACK_FRAME_L0_OFFSET             0x00
248#define CPU_STACK_FRAME_L1_OFFSET             0x04
249#define CPU_STACK_FRAME_L2_OFFSET             0x08
250#define CPU_STACK_FRAME_L3_OFFSET             0x0c
251#define CPU_STACK_FRAME_L4_OFFSET             0x10
252#define CPU_STACK_FRAME_L5_OFFSET             0x14
253#define CPU_STACK_FRAME_L6_OFFSET             0x18
254#define CPU_STACK_FRAME_L7_OFFSET             0x1c
255#define CPU_STACK_FRAME_I0_OFFSET             0x20
256#define CPU_STACK_FRAME_I1_OFFSET             0x24
257#define CPU_STACK_FRAME_I2_OFFSET             0x28
258#define CPU_STACK_FRAME_I3_OFFSET             0x2c
259#define CPU_STACK_FRAME_I4_OFFSET             0x30
260#define CPU_STACK_FRAME_I5_OFFSET             0x34
261#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
262#define CPU_STACK_FRAME_I7_OFFSET             0x3c
263#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
264#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
265#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
266#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
267#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
268#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
269#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
270#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
271
272#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
273
274/*
275 * Contexts
276 *
277 *  Generally there are 2 types of context to save.
278 *     1. Interrupt registers to save
279 *     2. Task level registers to save
280 *
281 *  This means we have the following 3 context items:
282 *     1. task level context stuff::  Context_Control
283 *     2. floating point task stuff:: Context_Control_fp
284 *     3. special interrupt level context :: Context_Control_interrupt
285 *
286 *  On the SPARC, we are relatively conservative in that we save most
287 *  of the CPU state in the context area.  The ET (enable trap) bit and
288 *  the CWP (current window pointer) fields of the PSR are considered
289 *  system wide resources and are not maintained on a per-thread basis.
290 */
291
292#ifndef ASM
293
294typedef struct {
295    /*
296     *  Using a double g0_g1 will put everything in this structure on a
297     *  double word boundary which allows us to use double word loads
298     *  and stores safely in the context switch.
299     */
300    double     g0_g1;
301    uint32_t   g2;
302    uint32_t   g3;
303    uint32_t   g4;
304    uint32_t   g5;
305    uint32_t   g6;
306    uint32_t   g7;
307
308    uint32_t   l0;
309    uint32_t   l1;
310    uint32_t   l2;
311    uint32_t   l3;
312    uint32_t   l4;
313    uint32_t   l5;
314    uint32_t   l6;
315    uint32_t   l7;
316
317    uint32_t   i0;
318    uint32_t   i1;
319    uint32_t   i2;
320    uint32_t   i3;
321    uint32_t   i4;
322    uint32_t   i5;
323    uint32_t   i6_fp;
324    uint32_t   i7;
325
326    uint32_t   o0;
327    uint32_t   o1;
328    uint32_t   o2;
329    uint32_t   o3;
330    uint32_t   o4;
331    uint32_t   o5;
332    uint32_t   o6_sp;
333    uint32_t   o7;
334
335    uint32_t   psr;
336    uint32_t   isr_dispatch_disable;
337} Context_Control;
338
339#endif /* ASM */
340
341/*
342 *  Offsets of fields with Context_Control for assembly routines.
343 */
344
345#define G0_OFFSET    0x00
346#define G1_OFFSET    0x04
347#define G2_OFFSET    0x08
348#define G3_OFFSET    0x0C
349#define G4_OFFSET    0x10
350#define G5_OFFSET    0x14
351#define G6_OFFSET    0x18
352#define G7_OFFSET    0x1C
353
354#define L0_OFFSET    0x20
355#define L1_OFFSET    0x24
356#define L2_OFFSET    0x28
357#define L3_OFFSET    0x2C
358#define L4_OFFSET    0x30
359#define L5_OFFSET    0x34
360#define L6_OFFSET    0x38
361#define L7_OFFSET    0x3C
362
363#define I0_OFFSET    0x40
364#define I1_OFFSET    0x44
365#define I2_OFFSET    0x48
366#define I3_OFFSET    0x4C
367#define I4_OFFSET    0x50
368#define I5_OFFSET    0x54
369#define I6_FP_OFFSET 0x58
370#define I7_OFFSET    0x5C
371
372#define O0_OFFSET    0x60
373#define O1_OFFSET    0x64
374#define O2_OFFSET    0x68
375#define O3_OFFSET    0x6C
376#define O4_OFFSET    0x70
377#define O5_OFFSET    0x74
378#define O6_SP_OFFSET 0x78
379#define O7_OFFSET    0x7C
380
381#define PSR_OFFSET   0x80
382#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
383
384#define CONTEXT_CONTROL_SIZE 0x88
385
386/*
387 *  The floating point context area.
388 */
389
390#ifndef ASM
391
392typedef struct {
393    double      f0_f1;
394    double      f2_f3;
395    double      f4_f5;
396    double      f6_f7;
397    double      f8_f9;
398    double      f10_f11;
399    double      f12_f13;
400    double      f14_f15;
401    double      f16_f17;
402    double      f18_f19;
403    double      f20_f21;
404    double      f22_f23;
405    double      f24_f25;
406    double      f26_f27;
407    double      f28_f29;
408    double      f30_f31;
409    uint32_t    fsr;
410} Context_Control_fp;
411
412#endif /* ASM */
413
414/*
415 *  Offsets of fields with Context_Control_fp for assembly routines.
416 */
417
418#define FO_F1_OFFSET     0x00
419#define F2_F3_OFFSET     0x08
420#define F4_F5_OFFSET     0x10
421#define F6_F7_OFFSET     0x18
422#define F8_F9_OFFSET     0x20
423#define F1O_F11_OFFSET   0x28
424#define F12_F13_OFFSET   0x30
425#define F14_F15_OFFSET   0x38
426#define F16_F17_OFFSET   0x40
427#define F18_F19_OFFSET   0x48
428#define F2O_F21_OFFSET   0x50
429#define F22_F23_OFFSET   0x58
430#define F24_F25_OFFSET   0x60
431#define F26_F27_OFFSET   0x68
432#define F28_F29_OFFSET   0x70
433#define F3O_F31_OFFSET   0x78
434#define FSR_OFFSET       0x80
435
436#define CONTEXT_CONTROL_FP_SIZE 0x84
437
438#ifndef ASM
439
440/*
441 *  Context saved on stack for an interrupt.
442 *
443 *  NOTE:  The PSR, PC, and NPC are only saved in this structure for the
444 *         benefit of the user's handler.
445 */
446
447typedef struct {
448  CPU_Minimum_stack_frame  Stack_frame;
449  uint32_t                 psr;
450  uint32_t                 pc;
451  uint32_t                 npc;
452  uint32_t                 g1;
453  uint32_t                 g2;
454  uint32_t                 g3;
455  uint32_t                 g4;
456  uint32_t                 g5;
457  uint32_t                 g6;
458  uint32_t                 g7;
459  uint32_t                 i0;
460  uint32_t                 i1;
461  uint32_t                 i2;
462  uint32_t                 i3;
463  uint32_t                 i4;
464  uint32_t                 i5;
465  uint32_t                 i6_fp;
466  uint32_t                 i7;
467  uint32_t                 y;
468  uint32_t                 tpc;
469} CPU_Interrupt_frame;
470
471#endif /* ASM */
472
473/*
474 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
475 */
476
477#define ISF_STACK_FRAME_OFFSET 0x00
478#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
479#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
480#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
481#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
482#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
483#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
484#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
485#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
486#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
487#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
488#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
489#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
490#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
491#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
492#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
493#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
494#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
495#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
496#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
497#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
498
499#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
500#ifndef ASM
501
502/*
503 *  The following table contains the information required to configure
504 *  the processor specific parameters.
505 */
506
507typedef struct {
508  void       (*pretasking_hook)( void );
509  void       (*predriver_hook)( void );
510  void       (*postdriver_hook)( void );
511  void       (*idle_task)( void );
512  boolean      do_zero_of_workspace;
513  uint32_t     idle_task_stack_size;
514  uint32_t     interrupt_stack_size;
515  uint32_t     extra_mpci_receive_server_stack;
516  void *     (*stack_allocate_hook)( uint32_t   );
517  void       (*stack_free_hook)( void* );
518  /* end of fields required on all CPUs */
519
520}   rtems_cpu_table;
521
522/*
523 *  Macros to access required entires in the CPU Table are in
524 *  the file rtems/system.h.
525 */
526
527/*
528 *  Macros to access SPARC specific additions to the CPU Table
529 */
530
531/* There are no CPU specific additions to the CPU Table for this port. */
532
533/*
534 *  This variable is contains the initialize context for the FP unit.
535 *  It is filled in by _CPU_Initialize and copied into the task's FP
536 *  context area during _CPU_Context_Initialize.
537 */
538
539SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
540
541/*
542 *  This stack is allocated by the Interrupt Manager and the switch
543 *  is performed in _ISR_Handler.  These variables contain pointers
544 *  to the lowest and highest addresses in the chunk of memory allocated
545 *  for the interrupt stack.  Since it is unknown whether the stack
546 *  grows up or down (in general), this give the CPU dependent
547 *  code the option of picking the version it wants to use.  Thus
548 *  both must be present if either is.
549 *
550 *  The SPARC supports a software based interrupt stack and these
551 *  are required.
552 */
553
554SCORE_EXTERN void *_CPU_Interrupt_stack_low;
555SCORE_EXTERN void *_CPU_Interrupt_stack_high;
556
557/*
558 *  This flag is context switched with each thread.  It indicates
559 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
560 *  By using this flag, we can avoid nesting more interrupt dispatching
561 *  attempts on a previously interrupted thread's stack.
562 */
563
564SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
565
566/*
567 *  The following type defines an entry in the SPARC's trap table.
568 *
569 *  NOTE: The instructions chosen are RTEMS dependent although one is
570 *        obligated to use two of the four instructions to perform a
571 *        long jump.  The other instructions load one register with the
572 *        trap type (a.k.a. vector) and another with the psr.
573 */
574 
575typedef struct {
576  uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
577  uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
578  uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
579  uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
580} CPU_Trap_table_entry;
581 
582/*
583 *  This is the set of opcodes for the instructions loaded into a trap
584 *  table entry.  The routine which installs a handler is responsible
585 *  for filling in the fields for the _handler address and the _vector
586 *  trap type.
587 *
588 *  The constants following this structure are masks for the fields which
589 *  must be filled in when the handler is installed.
590 */
591 
592extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
593
594/*
595 *  The size of the floating point context area. 
596 */
597
598#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
599
600#endif
601
602/*
603 *  Amount of extra stack (above minimum stack size) required by
604 *  MPCI receive server thread.  Remember that in a multiprocessor
605 *  system this thread must exist and be able to process all directives.
606 */
607
608#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
609
610/*
611 *  This defines the number of entries in the ISR_Vector_table managed
612 *  by the executive.
613 *
614 *  On the SPARC, there are really only 256 vectors.  However, the executive
615 *  has no easy, fast, reliable way to determine which traps are synchronous
616 *  and which are asynchronous.  By default, synchronous traps return to the
617 *  instruction which caused the interrupt.  So if you install a software
618 *  trap handler as an executive interrupt handler (which is desirable since
619 *  RTEMS takes care of window and register issues), then the executive needs
620 *  to know that the return address is to the trap rather than the instruction
621 *  following the trap.
622 *
623 *  So vectors 0 through 255 are treated as regular asynchronous traps which
624 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
625 *  by the executive to be synchronous and to require that the return address
626 *  be fudged.
627 *
628 *  If you use this mechanism to install a trap handler which must reexecute
629 *  the instruction which caused the trap, then it should be installed as
630 *  an asynchronous trap.  This will avoid the executive changing the return
631 *  address.
632 */
633
634#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
635#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
636
637#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
638#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
639#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
640
641#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
642
643/*
644 *  This is defined if the port has a special way to report the ISR nesting
645 *  level.  Most ports maintain the variable _ISR_Nest_level.
646 */
647
648#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
649
650/*
651 *  Should be large enough to run all tests.  This ensures
652 *  that a "reasonable" small application should not have any problems.
653 *
654 *  This appears to be a fairly generous number for the SPARC since
655 *  represents a call depth of about 20 routines based on the minimum
656 *  stack frame.
657 */
658
659#define CPU_STACK_MINIMUM_SIZE  (1024*4)
660
661/*
662 *  CPU's worst alignment requirement for data types on a byte boundary.  This
663 *  alignment does not take into account the requirements for the stack.
664 *
665 *  On the SPARC, this is required for double word loads and stores.
666 */
667
668#define CPU_ALIGNMENT      8
669
670/*
671 *  This number corresponds to the byte alignment requirement for the
672 *  heap handler.  This alignment requirement may be stricter than that
673 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
674 *  common for the heap to follow the same alignment requirement as
675 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
676 *  then this should be set to CPU_ALIGNMENT.
677 *
678 *  NOTE:  This does not have to be a power of 2.  It does have to
679 *         be greater or equal to than CPU_ALIGNMENT.
680 */
681
682#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
683
684/*
685 *  This number corresponds to the byte alignment requirement for memory
686 *  buffers allocated by the partition manager.  This alignment requirement
687 *  may be stricter than that for the data types alignment specified by
688 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
689 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
690 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
691 *
692 *  NOTE:  This does not have to be a power of 2.  It does have to
693 *         be greater or equal to than CPU_ALIGNMENT.
694 */
695
696#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
697
698/*
699 *  This number corresponds to the byte alignment requirement for the
700 *  stack.  This alignment requirement may be stricter than that for the
701 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
702 *  is strict enough for the stack, then this should be set to 0.
703 *
704 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
705 *
706 *  The alignment restrictions for the SPARC are not that strict but this
707 *  should unsure that the stack is always sufficiently alignment that the
708 *  window overflow, underflow, and flush routines can use double word loads
709 *  and stores.
710 */
711
712#define CPU_STACK_ALIGNMENT        16
713
714#ifndef ASM
715
716/*
717 *  ISR handler macros
718 */
719
720/*
721 *  Support routine to initialize the RTEMS vector table after it is allocated.
722 */
723
724#define _CPU_Initialize_vectors()
725
726/*
727 *  Disable all interrupts for a critical section.  The previous
728 *  level is returned in _level.
729 */
730
731#define _CPU_ISR_Disable( _level ) \
732  (_level) = sparc_disable_interrupts()
733 
734/*
735 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
736 *  This indicates the end of a critical section.  The parameter
737 *  _level is not modified.
738 */
739
740#define _CPU_ISR_Enable( _level ) \
741  sparc_enable_interrupts( _level )
742/*
743 *  This temporarily restores the interrupt to _level before immediately
744 *  disabling them again.  This is used to divide long critical
745 *  sections into two or more parts.  The parameter _level is not
746 *  modified.
747 */
748
749#define _CPU_ISR_Flash( _level ) \
750  sparc_flash_interrupts( _level )
751 
752/*
753 *  Map interrupt level in task mode onto the hardware that the CPU
754 *  actually provides.  Currently, interrupt levels which do not
755 *  map onto the CPU in a straight fashion are undefined. 
756 */
757
758#define _CPU_ISR_Set_level( _newlevel ) \
759   sparc_enable_interrupts( _newlevel << 8)
760 
761uint32_t   _CPU_ISR_Get_level( void );
762 
763/* end of ISR handler macros */
764
765/* Context handler macros */
766
767/*
768 *  Initialize the context to a state suitable for starting a
769 *  task after a context restore operation.  Generally, this
770 *  involves:
771 *
772 *     - setting a starting address
773 *     - preparing the stack
774 *     - preparing the stack and frame pointers
775 *     - setting the proper interrupt level in the context
776 *     - initializing the floating point context
777 *
778 *  NOTE:  Implemented as a subroutine for the SPARC port.
779 */
780
781void _CPU_Context_Initialize(
782  Context_Control  *the_context,
783  uint32_t         *stack_base,
784  uint32_t          size,
785  uint32_t          new_level,
786  void             *entry_point,
787  boolean           is_fp
788);
789
790/*
791 *  This macro is invoked from _Thread_Handler to do whatever CPU
792 *  specific magic is required that must be done in the context of
793 *  the thread when it starts.
794 *
795 *  On the SPARC, this is setting the frame pointer so GDB is happy.
796 *  Make GDB stop unwinding at _Thread_Handler, previous register window
797 *  Frame pointer is 0 and calling address must be a function with starting
798 *  with a SAVE instruction. If return address is leaf-function (no SAVE)
799 *  GDB will not look at prev reg window fp.
800 *
801 *  _Thread_Handler is known to start with SAVE.
802 */
803
804#define _CPU_Context_Initialization_at_thread_begin() \
805  do { \
806    asm volatile ("set _Thread_Handler,%%i7\n"::); \
807  } while (0)
808
809/*
810 *  This routine is responsible for somehow restarting the currently
811 *  executing task. 
812 *
813 *  On the SPARC, this is is relatively painless but requires a small
814 *  amount of wrapper code before using the regular restore code in
815 *  of the context switch.
816 */
817
818#define _CPU_Context_Restart_self( _the_context ) \
819   _CPU_Context_restore( (_the_context) );
820
821/*
822 *  The FP context area for the SPARC is a simple structure and nothing
823 *  special is required to find the "starting load point"
824 */
825
826#define _CPU_Context_Fp_start( _base, _offset ) \
827   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
828
829/*
830 *  This routine initializes the FP context area passed to it to.
831 *
832 *  The SPARC allows us to use the simple initialization model
833 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
834 *  at CPU initialization and it is simply copied into the destination
835 *  context.
836 */
837
838#define _CPU_Context_Initialize_fp( _destination ) \
839  do { \
840   *(*(_destination)) = _CPU_Null_fp_context; \
841  } while (0)
842
843/* end of Context handler macros */
844
845/* Fatal Error manager macros */
846
847/*
848 *  This routine copies _error into a known place -- typically a stack
849 *  location or a register, optionally disables interrupts, and
850 *  halts/stops the CPU.
851 */
852
853#define _CPU_Fatal_halt( _error ) \
854  do { \
855    uint32_t   level; \
856    \
857    level = sparc_disable_interrupts(); \
858    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
859    while (1); /* loop forever */ \
860  } while (0)
861
862/* end of Fatal Error manager macros */
863
864/* Bitfield handler macros */
865
866/*
867 *  The SPARC port uses the generic C algorithm for bitfield scan if the
868 *  CPU model does not have a scan instruction.
869 */
870
871#if ( SPARC_HAS_BITSCAN == 0 )
872#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
873#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
874#else
875#error "scan instruction not currently supported by RTEMS!!"
876#endif
877
878/* end of Bitfield handler macros */
879
880/* Priority handler handler macros */
881
882/*
883 *  The SPARC port uses the generic C algorithm for bitfield scan if the
884 *  CPU model does not have a scan instruction.
885 */
886
887#if ( SPARC_HAS_BITSCAN == 1 )
888#error "scan instruction not currently supported by RTEMS!!"
889#endif
890
891/* end of Priority handler macros */
892
893/* functions */
894
895/*
896 *  _CPU_Initialize
897 *
898 *  This routine performs CPU dependent initialization.
899 */
900
901void _CPU_Initialize(
902  rtems_cpu_table  *cpu_table,
903  void            (*thread_dispatch)
904);
905
906/*
907 *  _CPU_ISR_install_raw_handler
908 *
909 *  This routine installs new_handler to be directly called from the trap
910 *  table.
911 */
912 
913void _CPU_ISR_install_raw_handler(
914  uint32_t    vector,
915  proc_ptr    new_handler,
916  proc_ptr   *old_handler
917);
918
919/*
920 *  _CPU_ISR_install_vector
921 *
922 *  This routine installs an interrupt vector.
923 */
924
925void _CPU_ISR_install_vector(
926  uint32_t    vector,
927  proc_ptr    new_handler,
928  proc_ptr   *old_handler
929);
930
931#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
932 
933/*
934 *  _CPU_Thread_Idle_body
935 *
936 *  Some SPARC implementations have low power, sleep, or idle modes.  This
937 *  tries to take advantage of those models.
938 */
939 
940void _CPU_Thread_Idle_body( void );
941 
942#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
943
944/*
945 *  _CPU_Context_switch
946 *
947 *  This routine switches from the run context to the heir context.
948 */
949
950void _CPU_Context_switch(
951  Context_Control  *run,
952  Context_Control  *heir
953);
954
955/*
956 *  _CPU_Context_restore
957 *
958 *  This routine is generally used only to restart self in an
959 *  efficient manner.
960 */
961
962void _CPU_Context_restore(
963  Context_Control *new_context
964);
965
966/*
967 *  _CPU_Context_save_fp
968 *
969 *  This routine saves the floating point context passed to it.
970 */
971
972void _CPU_Context_save_fp(
973  Context_Control_fp **fp_context_ptr
974);
975
976/*
977 *  _CPU_Context_restore_fp
978 *
979 *  This routine restores the floating point context passed to it.
980 */
981
982void _CPU_Context_restore_fp(
983  Context_Control_fp **fp_context_ptr
984);
985
986/*
987 *  CPU_swap_u32
988 *
989 *  The following routine swaps the endian format of an unsigned int.
990 *  It must be static because it is referenced indirectly.
991 *
992 *  This version will work on any processor, but if you come across a better
993 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
994 *  entity as shown below is not any more efficient on the SPARC.
995 *
996 *     swap least significant two bytes with 16-bit rotate
997 *     swap upper and lower 16-bits
998 *     swap most significant two bytes with 16-bit rotate
999 *
1000 *  It is not obvious how the SPARC can do significantly better than the
1001 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
1002 *  following code at optimization level four (i.e. -O4).
1003 */
1004 
1005static inline uint32_t CPU_swap_u32(
1006  uint32_t value
1007)
1008{
1009  uint32_t   byte1, byte2, byte3, byte4, swapped;
1010 
1011  byte4 = (value >> 24) & 0xff;
1012  byte3 = (value >> 16) & 0xff;
1013  byte2 = (value >> 8)  & 0xff;
1014  byte1 =  value        & 0xff;
1015 
1016  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1017  return( swapped );
1018}
1019
1020#define CPU_swap_u16( value ) \
1021  (((value&0xff) << 8) | ((value >> 8)&0xff))
1022
1023#endif /* ASM */
1024
1025#ifdef __cplusplus
1026}
1027#endif
1028
1029#endif
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