1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @brief SPARC CPU Department Source |
---|
5 | * |
---|
6 | * This include file contains information pertaining to the port of |
---|
7 | * the executive to the SPARC processor. |
---|
8 | */ |
---|
9 | |
---|
10 | /* |
---|
11 | * COPYRIGHT (c) 1989-2011. |
---|
12 | * On-Line Applications Research Corporation (OAR). |
---|
13 | * |
---|
14 | * The license and distribution terms for this file may be |
---|
15 | * found in the file LICENSE in this distribution or at |
---|
16 | * http://www.rtems.org/license/LICENSE. |
---|
17 | */ |
---|
18 | |
---|
19 | #ifndef _RTEMS_SCORE_CPU_H |
---|
20 | #define _RTEMS_SCORE_CPU_H |
---|
21 | |
---|
22 | #ifdef __cplusplus |
---|
23 | extern "C" { |
---|
24 | #endif |
---|
25 | |
---|
26 | #include <rtems/score/types.h> |
---|
27 | #include <rtems/score/sparc.h> |
---|
28 | |
---|
29 | /* conditional compilation parameters */ |
---|
30 | |
---|
31 | #if defined(RTEMS_SMP) |
---|
32 | /* |
---|
33 | * The SPARC ABI is a bit special with respect to the floating point context. |
---|
34 | * The complete floating point context is volatile. Thus from an ABI point |
---|
35 | * of view nothing needs to be saved and restored during a context switch. |
---|
36 | * Instead the floating point context must be saved and restored during |
---|
37 | * interrupt processing. Historically the deferred floating point switch is |
---|
38 | * used for SPARC and the complete floating point context is saved and |
---|
39 | * restored during a context switch to the new floating point unit owner. |
---|
40 | * This is a bit dangerous since post-switch actions (e.g. signal handlers) |
---|
41 | * and context switch extensions may silently corrupt the floating point |
---|
42 | * context. The floating point unit is disabled for interrupt handlers. |
---|
43 | * Thus in case an interrupt handler uses the floating point unit then this |
---|
44 | * will result in a trap. |
---|
45 | * |
---|
46 | * On SMP configurations the deferred floating point switch is not |
---|
47 | * supported in principle. So use here a safe floating point support. Safe |
---|
48 | * means that the volatile floating point context is saved and restored |
---|
49 | * around a thread dispatch issued during interrupt processing. Thus |
---|
50 | * post-switch actions and context switch extensions may safely use the |
---|
51 | * floating point unit. |
---|
52 | */ |
---|
53 | #define SPARC_USE_SAFE_FP_SUPPORT |
---|
54 | #endif |
---|
55 | |
---|
56 | /** |
---|
57 | * Should the calls to _Thread_Enable_dispatch be inlined? |
---|
58 | * |
---|
59 | * - If TRUE, then they are inlined. |
---|
60 | * - If FALSE, then a subroutine call is made. |
---|
61 | * |
---|
62 | * On this port, it is faster to inline _Thread_Enable_dispatch. |
---|
63 | */ |
---|
64 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
---|
65 | |
---|
66 | /** |
---|
67 | * Does the executive manage a dedicated interrupt stack in software? |
---|
68 | * |
---|
69 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
---|
70 | * If FALSE, nothing is done. |
---|
71 | * |
---|
72 | * The SPARC does not have a dedicated HW interrupt stack and one has |
---|
73 | * been implemented in SW. |
---|
74 | */ |
---|
75 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
---|
76 | |
---|
77 | /** |
---|
78 | * Does the CPU follow the simple vectored interrupt model? |
---|
79 | * |
---|
80 | * - If TRUE, then RTEMS allocates the vector table it internally manages. |
---|
81 | * - If FALSE, then the BSP is assumed to allocate and manage the vector |
---|
82 | * table |
---|
83 | * |
---|
84 | * THe SPARC is a simple vectored architecture. Usually there is no |
---|
85 | * PIC and the CPU directly vectors the interrupts. |
---|
86 | */ |
---|
87 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
---|
88 | |
---|
89 | /** |
---|
90 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
91 | * |
---|
92 | * - If TRUE, then it must be installed during initialization. |
---|
93 | * - If FALSE, then no installation is performed. |
---|
94 | * |
---|
95 | * The SPARC does not have a dedicated HW interrupt stack. |
---|
96 | */ |
---|
97 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
98 | |
---|
99 | /** |
---|
100 | * Do we allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
101 | * |
---|
102 | * - If TRUE, then the memory is allocated during initialization. |
---|
103 | * - If FALSE, then the memory is allocated during initialization. |
---|
104 | * |
---|
105 | * The SPARC does not have hardware support for switching to a |
---|
106 | * dedicated interrupt stack. The port includes support for doing this |
---|
107 | * in software. |
---|
108 | * |
---|
109 | */ |
---|
110 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
111 | |
---|
112 | /** |
---|
113 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
114 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
115 | * number (0)? |
---|
116 | * |
---|
117 | * The SPARC port does not pass an Interrupt Stack Frame pointer to |
---|
118 | * interrupt handlers. |
---|
119 | */ |
---|
120 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
---|
121 | |
---|
122 | /** |
---|
123 | * Does the CPU have hardware floating point? |
---|
124 | * |
---|
125 | * - If TRUE, then the FLOATING_POINT task attribute is supported. |
---|
126 | * - If FALSE, then the FLOATING_POINT task attribute is ignored. |
---|
127 | * |
---|
128 | * This is set based upon the multilib settings. |
---|
129 | */ |
---|
130 | #if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SAFE_FP_SUPPORT) |
---|
131 | #define CPU_HARDWARE_FP TRUE |
---|
132 | #else |
---|
133 | #define CPU_HARDWARE_FP FALSE |
---|
134 | #endif |
---|
135 | |
---|
136 | /** |
---|
137 | * The SPARC GCC port does not have a software floating point library |
---|
138 | * that requires RTEMS assistance. |
---|
139 | */ |
---|
140 | #define CPU_SOFTWARE_FP FALSE |
---|
141 | |
---|
142 | /** |
---|
143 | * Are all tasks FLOATING_POINT tasks implicitly? |
---|
144 | * |
---|
145 | * - If TRUE, then the FLOATING_POINT task attribute is assumed. |
---|
146 | * - If FALSE, then the FLOATING_POINT task attribute is followed. |
---|
147 | * |
---|
148 | * The SPARC GCC port does not implicitly use floating point registers. |
---|
149 | */ |
---|
150 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
151 | |
---|
152 | /** |
---|
153 | * Should the IDLE task have a floating point context? |
---|
154 | * |
---|
155 | * - If TRUE, then the IDLE task is created as a FLOATING_POINT task |
---|
156 | * and it has a floating point context which is switched in and out. |
---|
157 | * - If FALSE, then the IDLE task does not have a floating point context. |
---|
158 | * |
---|
159 | * The IDLE task does not have to be floating point on the SPARC. |
---|
160 | */ |
---|
161 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
162 | |
---|
163 | /** |
---|
164 | * Should the saving of the floating point registers be deferred |
---|
165 | * until a context switch is made to another different floating point |
---|
166 | * task? |
---|
167 | * |
---|
168 | * - If TRUE, then the floating point context will not be stored until |
---|
169 | * necessary. It will remain in the floating point registers and not |
---|
170 | * disturned until another floating point task is switched to. |
---|
171 | * |
---|
172 | * - If FALSE, then the floating point context is saved when a floating |
---|
173 | * point task is switched out and restored when the next floating point |
---|
174 | * task is restored. The state of the floating point registers between |
---|
175 | * those two operations is not specified. |
---|
176 | * |
---|
177 | * On the SPARC, we can disable the FPU for integer only tasks so |
---|
178 | * it is safe to defer floating point context switches. |
---|
179 | */ |
---|
180 | #if defined(SPARC_USE_SAFE_FP_SUPPORT) |
---|
181 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
---|
182 | #else |
---|
183 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
184 | #endif |
---|
185 | |
---|
186 | /** |
---|
187 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
188 | * |
---|
189 | * - If TRUE, then the routine _CPU_Thread_Idle_body |
---|
190 | * must be provided and is the default IDLE thread body instead of |
---|
191 | * _CPU_Thread_Idle_body. |
---|
192 | * |
---|
193 | * - If FALSE, then use the generic IDLE thread body if the BSP does |
---|
194 | * not provide one. |
---|
195 | * |
---|
196 | * The SPARC architecture does not have a low power or halt instruction. |
---|
197 | * It is left to the BSP and/or CPU specific code to provide an IDLE |
---|
198 | * thread body which is aware of low power modes. |
---|
199 | */ |
---|
200 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
---|
201 | |
---|
202 | /** |
---|
203 | * Does the stack grow up (toward higher addresses) or down |
---|
204 | * (toward lower addresses)? |
---|
205 | * |
---|
206 | * - If TRUE, then the grows upward. |
---|
207 | * - If FALSE, then the grows toward smaller addresses. |
---|
208 | * |
---|
209 | * The stack grows to lower addresses on the SPARC. |
---|
210 | */ |
---|
211 | #define CPU_STACK_GROWS_UP FALSE |
---|
212 | |
---|
213 | /* FIXME: Is this the right value? */ |
---|
214 | #define CPU_CACHE_LINE_BYTES 32 |
---|
215 | |
---|
216 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
---|
217 | |
---|
218 | /** |
---|
219 | * Define what is required to specify how the network to host conversion |
---|
220 | * routines are handled. |
---|
221 | * |
---|
222 | * The SPARC is big endian. |
---|
223 | */ |
---|
224 | #define CPU_BIG_ENDIAN TRUE |
---|
225 | |
---|
226 | /** |
---|
227 | * Define what is required to specify how the network to host conversion |
---|
228 | * routines are handled. |
---|
229 | * |
---|
230 | * The SPARC is NOT little endian. |
---|
231 | */ |
---|
232 | #define CPU_LITTLE_ENDIAN FALSE |
---|
233 | |
---|
234 | /** |
---|
235 | * The following defines the number of bits actually used in the |
---|
236 | * interrupt field of the task mode. How those bits map to the |
---|
237 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
---|
238 | * |
---|
239 | * The SPARC has 16 interrupt levels in the PIL field of the PSR. |
---|
240 | */ |
---|
241 | #define CPU_MODES_INTERRUPT_MASK 0x0000000F |
---|
242 | |
---|
243 | #ifndef ASM |
---|
244 | /** |
---|
245 | * This structure represents the organization of the minimum stack frame |
---|
246 | * for the SPARC. More framing information is required in certain situaions |
---|
247 | * such as when there are a large number of out parameters or when the callee |
---|
248 | * must save floating point registers. |
---|
249 | */ |
---|
250 | typedef struct { |
---|
251 | /** This is the offset of the l0 register. */ |
---|
252 | uint32_t l0; |
---|
253 | /** This is the offset of the l1 register. */ |
---|
254 | uint32_t l1; |
---|
255 | /** This is the offset of the l2 register. */ |
---|
256 | uint32_t l2; |
---|
257 | /** This is the offset of the l3 register. */ |
---|
258 | uint32_t l3; |
---|
259 | /** This is the offset of the l4 register. */ |
---|
260 | uint32_t l4; |
---|
261 | /** This is the offset of the l5 register. */ |
---|
262 | uint32_t l5; |
---|
263 | /** This is the offset of the l6 register. */ |
---|
264 | uint32_t l6; |
---|
265 | /** This is the offset of the l7 register. */ |
---|
266 | uint32_t l7; |
---|
267 | /** This is the offset of the l0 register. */ |
---|
268 | uint32_t i0; |
---|
269 | /** This is the offset of the i1 register. */ |
---|
270 | uint32_t i1; |
---|
271 | /** This is the offset of the i2 register. */ |
---|
272 | uint32_t i2; |
---|
273 | /** This is the offset of the i3 register. */ |
---|
274 | uint32_t i3; |
---|
275 | /** This is the offset of the i4 register. */ |
---|
276 | uint32_t i4; |
---|
277 | /** This is the offset of the i5 register. */ |
---|
278 | uint32_t i5; |
---|
279 | /** This is the offset of the i6 register. */ |
---|
280 | uint32_t i6_fp; |
---|
281 | /** This is the offset of the i7 register. */ |
---|
282 | uint32_t i7; |
---|
283 | /** This is the offset of the register used to return structures. */ |
---|
284 | void *structure_return_address; |
---|
285 | |
---|
286 | /* |
---|
287 | * The following are for the callee to save the register arguments in |
---|
288 | * should this be necessary. |
---|
289 | */ |
---|
290 | /** This is the offset of the register for saved argument 0. */ |
---|
291 | uint32_t saved_arg0; |
---|
292 | /** This is the offset of the register for saved argument 1. */ |
---|
293 | uint32_t saved_arg1; |
---|
294 | /** This is the offset of the register for saved argument 2. */ |
---|
295 | uint32_t saved_arg2; |
---|
296 | /** This is the offset of the register for saved argument 3. */ |
---|
297 | uint32_t saved_arg3; |
---|
298 | /** This is the offset of the register for saved argument 4. */ |
---|
299 | uint32_t saved_arg4; |
---|
300 | /** This is the offset of the register for saved argument 5. */ |
---|
301 | uint32_t saved_arg5; |
---|
302 | /** This field pads the structure so ldd and std instructions can be used. */ |
---|
303 | uint32_t pad0; |
---|
304 | } CPU_Minimum_stack_frame; |
---|
305 | |
---|
306 | #endif /* ASM */ |
---|
307 | |
---|
308 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
309 | #define CPU_STACK_FRAME_L0_OFFSET 0x00 |
---|
310 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
311 | #define CPU_STACK_FRAME_L1_OFFSET 0x04 |
---|
312 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
313 | #define CPU_STACK_FRAME_L2_OFFSET 0x08 |
---|
314 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
315 | #define CPU_STACK_FRAME_L3_OFFSET 0x0c |
---|
316 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
317 | #define CPU_STACK_FRAME_L4_OFFSET 0x10 |
---|
318 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
319 | #define CPU_STACK_FRAME_L5_OFFSET 0x14 |
---|
320 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
321 | #define CPU_STACK_FRAME_L6_OFFSET 0x18 |
---|
322 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
323 | #define CPU_STACK_FRAME_L7_OFFSET 0x1c |
---|
324 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
325 | #define CPU_STACK_FRAME_I0_OFFSET 0x20 |
---|
326 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
327 | #define CPU_STACK_FRAME_I1_OFFSET 0x24 |
---|
328 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
329 | #define CPU_STACK_FRAME_I2_OFFSET 0x28 |
---|
330 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
331 | #define CPU_STACK_FRAME_I3_OFFSET 0x2c |
---|
332 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
333 | #define CPU_STACK_FRAME_I4_OFFSET 0x30 |
---|
334 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
335 | #define CPU_STACK_FRAME_I5_OFFSET 0x34 |
---|
336 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
337 | #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 |
---|
338 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
339 | #define CPU_STACK_FRAME_I7_OFFSET 0x3c |
---|
340 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
341 | #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 |
---|
342 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
343 | #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 |
---|
344 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
345 | #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 |
---|
346 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
347 | #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c |
---|
348 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
349 | #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 |
---|
350 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
351 | #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 |
---|
352 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
353 | #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 |
---|
354 | /** This macro defines an offset into the stack frame for use in assembly. */ |
---|
355 | #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c |
---|
356 | |
---|
357 | /** This defines the size of the minimum stack frame. */ |
---|
358 | #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 |
---|
359 | |
---|
360 | #if ( SPARC_HAS_FPU == 1 ) |
---|
361 | #define CPU_PER_CPU_CONTROL_SIZE 8 |
---|
362 | #else |
---|
363 | #define CPU_PER_CPU_CONTROL_SIZE 4 |
---|
364 | #endif |
---|
365 | |
---|
366 | /** |
---|
367 | * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field |
---|
368 | * relative to the Per_CPU_Control begin. |
---|
369 | */ |
---|
370 | #define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 |
---|
371 | |
---|
372 | #if ( SPARC_HAS_FPU == 1 ) |
---|
373 | /** |
---|
374 | * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the |
---|
375 | * Per_CPU_Control begin. |
---|
376 | */ |
---|
377 | #define SPARC_PER_CPU_FSR_OFFSET 4 |
---|
378 | #endif |
---|
379 | |
---|
380 | /** |
---|
381 | * @defgroup Contexts SPARC Context Structures |
---|
382 | * |
---|
383 | * @ingroup Score |
---|
384 | * |
---|
385 | * Generally there are 2 types of context to save. |
---|
386 | * + Interrupt registers to save |
---|
387 | * + Task level registers to save |
---|
388 | * |
---|
389 | * This means we have the following 3 context items: |
---|
390 | * + task level context stuff:: Context_Control |
---|
391 | * + floating point task stuff:: Context_Control_fp |
---|
392 | * + special interrupt level context :: Context_Control_interrupt |
---|
393 | * |
---|
394 | * On the SPARC, we are relatively conservative in that we save most |
---|
395 | * of the CPU state in the context area. The ET (enable trap) bit and |
---|
396 | * the CWP (current window pointer) fields of the PSR are considered |
---|
397 | * system wide resources and are not maintained on a per-thread basis. |
---|
398 | */ |
---|
399 | /**@{**/ |
---|
400 | |
---|
401 | #ifndef ASM |
---|
402 | |
---|
403 | typedef struct { |
---|
404 | /** |
---|
405 | * This flag is context switched with each thread. It indicates |
---|
406 | * that THIS thread has an _ISR_Dispatch stack frame on its stack. |
---|
407 | * By using this flag, we can avoid nesting more interrupt dispatching |
---|
408 | * attempts on a previously interrupted thread's stack. |
---|
409 | */ |
---|
410 | uint32_t isr_dispatch_disable; |
---|
411 | |
---|
412 | #if ( SPARC_HAS_FPU == 1 ) |
---|
413 | /** |
---|
414 | * @brief Memory location to store the FSR register during interrupt |
---|
415 | * processing. |
---|
416 | * |
---|
417 | * This is a write-only field. The FSR is written to force a completion of |
---|
418 | * floating point operations in progress. |
---|
419 | */ |
---|
420 | uint32_t fsr; |
---|
421 | #endif |
---|
422 | } CPU_Per_CPU_control; |
---|
423 | |
---|
424 | /** |
---|
425 | * @brief SPARC basic context. |
---|
426 | * |
---|
427 | * This structure defines the non-volatile integer and processor state context |
---|
428 | * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY |
---|
429 | * INTERFACE - SPARC Processor Supplement", Third Edition. |
---|
430 | * |
---|
431 | * The registers g2 through g4 are reserved for applications. GCC uses them as |
---|
432 | * volatile registers by default. So they are treated like volatile registers |
---|
433 | * in RTEMS as well. |
---|
434 | * |
---|
435 | * The register g6 contains the per-CPU control of the current processor. It |
---|
436 | * is an invariant of the processor context. This register must not be saved |
---|
437 | * and restored during context switches or interrupt services. |
---|
438 | */ |
---|
439 | typedef struct { |
---|
440 | /** This will contain the contents of the g5 register. */ |
---|
441 | uint32_t g5; |
---|
442 | /** This will contain the contents of the g7 register. */ |
---|
443 | uint32_t g7; |
---|
444 | |
---|
445 | /** |
---|
446 | * This will contain the contents of the l0 and l1 registers. |
---|
447 | * |
---|
448 | * Using a double l0_and_l1 will put everything in this structure on a double |
---|
449 | * word boundary which allows us to use double word loads and stores safely |
---|
450 | * in the context switch. |
---|
451 | */ |
---|
452 | double l0_and_l1; |
---|
453 | /** This will contain the contents of the l2 register. */ |
---|
454 | uint32_t l2; |
---|
455 | /** This will contain the contents of the l3 register. */ |
---|
456 | uint32_t l3; |
---|
457 | /** This will contain the contents of the l4 register. */ |
---|
458 | uint32_t l4; |
---|
459 | /** This will contain the contents of the l5 registeer.*/ |
---|
460 | uint32_t l5; |
---|
461 | /** This will contain the contents of the l6 register. */ |
---|
462 | uint32_t l6; |
---|
463 | /** This will contain the contents of the l7 register. */ |
---|
464 | uint32_t l7; |
---|
465 | |
---|
466 | /** This will contain the contents of the i0 register. */ |
---|
467 | uint32_t i0; |
---|
468 | /** This will contain the contents of the i1 register. */ |
---|
469 | uint32_t i1; |
---|
470 | /** This will contain the contents of the i2 register. */ |
---|
471 | uint32_t i2; |
---|
472 | /** This will contain the contents of the i3 register. */ |
---|
473 | uint32_t i3; |
---|
474 | /** This will contain the contents of the i4 register. */ |
---|
475 | uint32_t i4; |
---|
476 | /** This will contain the contents of the i5 register. */ |
---|
477 | uint32_t i5; |
---|
478 | /** This will contain the contents of the i6 (e.g. frame pointer) register. */ |
---|
479 | uint32_t i6_fp; |
---|
480 | /** This will contain the contents of the i7 register. */ |
---|
481 | uint32_t i7; |
---|
482 | |
---|
483 | /** This will contain the contents of the o6 (e.g. frame pointer) register. */ |
---|
484 | uint32_t o6_sp; |
---|
485 | /** |
---|
486 | * This will contain the contents of the o7 (e.g. address of CALL |
---|
487 | * instruction) register. |
---|
488 | */ |
---|
489 | uint32_t o7; |
---|
490 | |
---|
491 | /** This will contain the contents of the processor status register. */ |
---|
492 | uint32_t psr; |
---|
493 | /** |
---|
494 | * This field is used to prevent heavy nesting of calls to _Thread_Dispatch |
---|
495 | * on an interrupted task's stack. This is problematic on the slower |
---|
496 | * SPARC CPU models at high interrupt rates. |
---|
497 | */ |
---|
498 | uint32_t isr_dispatch_disable; |
---|
499 | |
---|
500 | #if defined(RTEMS_SMP) |
---|
501 | volatile uint32_t is_executing; |
---|
502 | #endif |
---|
503 | } Context_Control; |
---|
504 | |
---|
505 | /** |
---|
506 | * This macro provides a CPU independent way for RTEMS to access the |
---|
507 | * stack pointer in a context structure. The actual name and offset is |
---|
508 | * CPU architecture dependent. |
---|
509 | */ |
---|
510 | #define _CPU_Context_Get_SP( _context ) \ |
---|
511 | (_context)->o6_sp |
---|
512 | |
---|
513 | #ifdef RTEMS_SMP |
---|
514 | static inline bool _CPU_Context_Get_is_executing( |
---|
515 | const Context_Control *context |
---|
516 | ) |
---|
517 | { |
---|
518 | return context->is_executing; |
---|
519 | } |
---|
520 | |
---|
521 | static inline void _CPU_Context_Set_is_executing( |
---|
522 | Context_Control *context, |
---|
523 | bool is_executing |
---|
524 | ) |
---|
525 | { |
---|
526 | context->is_executing = is_executing; |
---|
527 | } |
---|
528 | #endif |
---|
529 | |
---|
530 | #endif /* ASM */ |
---|
531 | |
---|
532 | /* |
---|
533 | * Offsets of fields with Context_Control for assembly routines. |
---|
534 | */ |
---|
535 | |
---|
536 | /** This macro defines an offset into the context for use in assembly. */ |
---|
537 | #define G5_OFFSET 0x00 |
---|
538 | /** This macro defines an offset into the context for use in assembly. */ |
---|
539 | #define G7_OFFSET 0x04 |
---|
540 | |
---|
541 | /** This macro defines an offset into the context for use in assembly. */ |
---|
542 | #define L0_OFFSET 0x08 |
---|
543 | /** This macro defines an offset into the context for use in assembly. */ |
---|
544 | #define L1_OFFSET 0x0C |
---|
545 | /** This macro defines an offset into the context for use in assembly. */ |
---|
546 | #define L2_OFFSET 0x10 |
---|
547 | /** This macro defines an offset into the context for use in assembly. */ |
---|
548 | #define L3_OFFSET 0x14 |
---|
549 | /** This macro defines an offset into the context for use in assembly. */ |
---|
550 | #define L4_OFFSET 0x18 |
---|
551 | /** This macro defines an offset into the context for use in assembly. */ |
---|
552 | #define L5_OFFSET 0x1C |
---|
553 | /** This macro defines an offset into the context for use in assembly. */ |
---|
554 | #define L6_OFFSET 0x20 |
---|
555 | /** This macro defines an offset into the context for use in assembly. */ |
---|
556 | #define L7_OFFSET 0x24 |
---|
557 | |
---|
558 | /** This macro defines an offset into the context for use in assembly. */ |
---|
559 | #define I0_OFFSET 0x28 |
---|
560 | /** This macro defines an offset into the context for use in assembly. */ |
---|
561 | #define I1_OFFSET 0x2C |
---|
562 | /** This macro defines an offset into the context for use in assembly. */ |
---|
563 | #define I2_OFFSET 0x30 |
---|
564 | /** This macro defines an offset into the context for use in assembly. */ |
---|
565 | #define I3_OFFSET 0x34 |
---|
566 | /** This macro defines an offset into the context for use in assembly. */ |
---|
567 | #define I4_OFFSET 0x38 |
---|
568 | /** This macro defines an offset into the context for use in assembly. */ |
---|
569 | #define I5_OFFSET 0x3C |
---|
570 | /** This macro defines an offset into the context for use in assembly. */ |
---|
571 | #define I6_FP_OFFSET 0x40 |
---|
572 | /** This macro defines an offset into the context for use in assembly. */ |
---|
573 | #define I7_OFFSET 0x44 |
---|
574 | |
---|
575 | /** This macro defines an offset into the context for use in assembly. */ |
---|
576 | #define O6_SP_OFFSET 0x48 |
---|
577 | /** This macro defines an offset into the context for use in assembly. */ |
---|
578 | #define O7_OFFSET 0x4C |
---|
579 | |
---|
580 | /** This macro defines an offset into the context for use in assembly. */ |
---|
581 | #define PSR_OFFSET 0x50 |
---|
582 | /** This macro defines an offset into the context for use in assembly. */ |
---|
583 | #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 |
---|
584 | |
---|
585 | #if defined(RTEMS_SMP) |
---|
586 | #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 |
---|
587 | #endif |
---|
588 | |
---|
589 | #ifndef ASM |
---|
590 | /** |
---|
591 | * @brief SPARC basic context. |
---|
592 | * |
---|
593 | * This structure defines floating point context area. |
---|
594 | */ |
---|
595 | typedef struct { |
---|
596 | /** This will contain the contents of the f0 and f1 register. */ |
---|
597 | double f0_f1; |
---|
598 | /** This will contain the contents of the f2 and f3 register. */ |
---|
599 | double f2_f3; |
---|
600 | /** This will contain the contents of the f4 and f5 register. */ |
---|
601 | double f4_f5; |
---|
602 | /** This will contain the contents of the f6 and f7 register. */ |
---|
603 | double f6_f7; |
---|
604 | /** This will contain the contents of the f8 and f9 register. */ |
---|
605 | double f8_f9; |
---|
606 | /** This will contain the contents of the f10 and f11 register. */ |
---|
607 | double f10_f11; |
---|
608 | /** This will contain the contents of the f12 and f13 register. */ |
---|
609 | double f12_f13; |
---|
610 | /** This will contain the contents of the f14 and f15 register. */ |
---|
611 | double f14_f15; |
---|
612 | /** This will contain the contents of the f16 and f17 register. */ |
---|
613 | double f16_f17; |
---|
614 | /** This will contain the contents of the f18 and f19 register. */ |
---|
615 | double f18_f19; |
---|
616 | /** This will contain the contents of the f20 and f21 register. */ |
---|
617 | double f20_f21; |
---|
618 | /** This will contain the contents of the f22 and f23 register. */ |
---|
619 | double f22_f23; |
---|
620 | /** This will contain the contents of the f24 and f25 register. */ |
---|
621 | double f24_f25; |
---|
622 | /** This will contain the contents of the f26 and f27 register. */ |
---|
623 | double f26_f27; |
---|
624 | /** This will contain the contents of the f28 and f29 register. */ |
---|
625 | double f28_f29; |
---|
626 | /** This will contain the contents of the f30 and f31 register. */ |
---|
627 | double f30_f31; |
---|
628 | /** This will contain the contents of the floating point status register. */ |
---|
629 | uint32_t fsr; |
---|
630 | } Context_Control_fp; |
---|
631 | |
---|
632 | #endif /* ASM */ |
---|
633 | |
---|
634 | /* |
---|
635 | * Offsets of fields with Context_Control_fp for assembly routines. |
---|
636 | */ |
---|
637 | |
---|
638 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
639 | #define FO_F1_OFFSET 0x00 |
---|
640 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
641 | #define F2_F3_OFFSET 0x08 |
---|
642 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
643 | #define F4_F5_OFFSET 0x10 |
---|
644 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
645 | #define F6_F7_OFFSET 0x18 |
---|
646 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
647 | #define F8_F9_OFFSET 0x20 |
---|
648 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
649 | #define F1O_F11_OFFSET 0x28 |
---|
650 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
651 | #define F12_F13_OFFSET 0x30 |
---|
652 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
653 | #define F14_F15_OFFSET 0x38 |
---|
654 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
655 | #define F16_F17_OFFSET 0x40 |
---|
656 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
657 | #define F18_F19_OFFSET 0x48 |
---|
658 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
659 | #define F2O_F21_OFFSET 0x50 |
---|
660 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
661 | #define F22_F23_OFFSET 0x58 |
---|
662 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
663 | #define F24_F25_OFFSET 0x60 |
---|
664 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
665 | #define F26_F27_OFFSET 0x68 |
---|
666 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
667 | #define F28_F29_OFFSET 0x70 |
---|
668 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
669 | #define F3O_F31_OFFSET 0x78 |
---|
670 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
671 | #define FSR_OFFSET 0x80 |
---|
672 | |
---|
673 | /** This defines the size of the FPU context area for use in assembly. */ |
---|
674 | #define CONTEXT_CONTROL_FP_SIZE 0x84 |
---|
675 | |
---|
676 | #ifndef ASM |
---|
677 | |
---|
678 | /** @} */ |
---|
679 | |
---|
680 | /** |
---|
681 | * @brief Interrupt stack frame (ISF). |
---|
682 | * |
---|
683 | * Context saved on stack for an interrupt. |
---|
684 | * |
---|
685 | * NOTE: The PSR, PC, and NPC are only saved in this structure for the |
---|
686 | * benefit of the user's handler. |
---|
687 | */ |
---|
688 | typedef struct { |
---|
689 | /** On an interrupt, we must save the minimum stack frame. */ |
---|
690 | CPU_Minimum_stack_frame Stack_frame; |
---|
691 | /** This is the offset of the PSR on an ISF. */ |
---|
692 | uint32_t psr; |
---|
693 | /** This is the offset of the XXX on an ISF. */ |
---|
694 | uint32_t pc; |
---|
695 | /** This is the offset of the XXX on an ISF. */ |
---|
696 | uint32_t npc; |
---|
697 | /** This is the offset of the g1 register on an ISF. */ |
---|
698 | uint32_t g1; |
---|
699 | /** This is the offset of the g2 register on an ISF. */ |
---|
700 | uint32_t g2; |
---|
701 | /** This is the offset of the g3 register on an ISF. */ |
---|
702 | uint32_t g3; |
---|
703 | /** This is the offset of the g4 register on an ISF. */ |
---|
704 | uint32_t g4; |
---|
705 | /** This is the offset of the g5 register on an ISF. */ |
---|
706 | uint32_t g5; |
---|
707 | /** This is the offset is reserved for alignment on an ISF. */ |
---|
708 | uint32_t reserved_for_alignment; |
---|
709 | /** This is the offset of the g7 register on an ISF. */ |
---|
710 | uint32_t g7; |
---|
711 | /** This is the offset of the i0 register on an ISF. */ |
---|
712 | uint32_t i0; |
---|
713 | /** This is the offset of the i1 register on an ISF. */ |
---|
714 | uint32_t i1; |
---|
715 | /** This is the offset of the i2 register on an ISF. */ |
---|
716 | uint32_t i2; |
---|
717 | /** This is the offset of the i3 register on an ISF. */ |
---|
718 | uint32_t i3; |
---|
719 | /** This is the offset of the i4 register on an ISF. */ |
---|
720 | uint32_t i4; |
---|
721 | /** This is the offset of the i5 register on an ISF. */ |
---|
722 | uint32_t i5; |
---|
723 | /** This is the offset of the i6 register on an ISF. */ |
---|
724 | uint32_t i6_fp; |
---|
725 | /** This is the offset of the i7 register on an ISF. */ |
---|
726 | uint32_t i7; |
---|
727 | /** This is the offset of the y register on an ISF. */ |
---|
728 | uint32_t y; |
---|
729 | /** This is the offset of the tpc register on an ISF. */ |
---|
730 | uint32_t tpc; |
---|
731 | } CPU_Interrupt_frame; |
---|
732 | |
---|
733 | #endif /* ASM */ |
---|
734 | |
---|
735 | /* |
---|
736 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
---|
737 | */ |
---|
738 | |
---|
739 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
740 | #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 |
---|
741 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
742 | #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 |
---|
743 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
744 | #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 |
---|
745 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
746 | #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c |
---|
747 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
748 | #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 |
---|
749 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
750 | #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 |
---|
751 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
752 | #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 |
---|
753 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
754 | #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c |
---|
755 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
756 | #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 |
---|
757 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
758 | #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 |
---|
759 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
760 | #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c |
---|
761 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
762 | #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 |
---|
763 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
764 | #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 |
---|
765 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
766 | #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 |
---|
767 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
768 | #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c |
---|
769 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
770 | #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 |
---|
771 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
772 | #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 |
---|
773 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
774 | #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 |
---|
775 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
776 | #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c |
---|
777 | |
---|
778 | /** This defines the size of the ISF area for use in assembly. */ |
---|
779 | #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ |
---|
780 | CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 |
---|
781 | |
---|
782 | #ifndef ASM |
---|
783 | /** |
---|
784 | * This variable is contains the initialize context for the FP unit. |
---|
785 | * It is filled in by _CPU_Initialize and copied into the task's FP |
---|
786 | * context area during _CPU_Context_Initialize. |
---|
787 | */ |
---|
788 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
789 | |
---|
790 | /** |
---|
791 | * The following type defines an entry in the SPARC's trap table. |
---|
792 | * |
---|
793 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
794 | * obligated to use two of the four instructions to perform a |
---|
795 | * long jump. The other instructions load one register with the |
---|
796 | * trap type (a.k.a. vector) and another with the psr. |
---|
797 | */ |
---|
798 | typedef struct { |
---|
799 | /** This will contain a "mov %psr, %l0" instruction. */ |
---|
800 | uint32_t mov_psr_l0; |
---|
801 | /** This will contain a "sethi %hi(_handler), %l4" instruction. */ |
---|
802 | uint32_t sethi_of_handler_to_l4; |
---|
803 | /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ |
---|
804 | uint32_t jmp_to_low_of_handler_plus_l4; |
---|
805 | /** This will contain a " mov _vector, %l3" instruction. */ |
---|
806 | uint32_t mov_vector_l3; |
---|
807 | } CPU_Trap_table_entry; |
---|
808 | |
---|
809 | /** |
---|
810 | * This is the set of opcodes for the instructions loaded into a trap |
---|
811 | * table entry. The routine which installs a handler is responsible |
---|
812 | * for filling in the fields for the _handler address and the _vector |
---|
813 | * trap type. |
---|
814 | * |
---|
815 | * The constants following this structure are masks for the fields which |
---|
816 | * must be filled in when the handler is installed. |
---|
817 | */ |
---|
818 | extern const CPU_Trap_table_entry _CPU_Trap_slot_template; |
---|
819 | |
---|
820 | /** |
---|
821 | * The size of the floating point context area. |
---|
822 | */ |
---|
823 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
824 | |
---|
825 | #endif |
---|
826 | |
---|
827 | /** |
---|
828 | * Amount of extra stack (above minimum stack size) required by |
---|
829 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
830 | * system this thread must exist and be able to process all directives. |
---|
831 | */ |
---|
832 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
---|
833 | |
---|
834 | /** |
---|
835 | * This defines the number of entries in the ISR_Vector_table managed |
---|
836 | * by the executive. |
---|
837 | * |
---|
838 | * On the SPARC, there are really only 256 vectors. However, the executive |
---|
839 | * has no easy, fast, reliable way to determine which traps are synchronous |
---|
840 | * and which are asynchronous. By default, synchronous traps return to the |
---|
841 | * instruction which caused the interrupt. So if you install a software |
---|
842 | * trap handler as an executive interrupt handler (which is desirable since |
---|
843 | * RTEMS takes care of window and register issues), then the executive needs |
---|
844 | * to know that the return address is to the trap rather than the instruction |
---|
845 | * following the trap. |
---|
846 | * |
---|
847 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
---|
848 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
---|
849 | * by the executive to be synchronous and to require that the return address |
---|
850 | * be fudged. |
---|
851 | * |
---|
852 | * If you use this mechanism to install a trap handler which must reexecute |
---|
853 | * the instruction which caused the trap, then it should be installed as |
---|
854 | * an asynchronous trap. This will avoid the executive changing the return |
---|
855 | * address. |
---|
856 | */ |
---|
857 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
858 | |
---|
859 | /** |
---|
860 | * The SPARC has 256 vectors but the port treats 256-512 as synchronous |
---|
861 | * traps. |
---|
862 | */ |
---|
863 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 |
---|
864 | |
---|
865 | /** |
---|
866 | * This is the bit step in a vector number to indicate it is being installed |
---|
867 | * as a synchronous trap. |
---|
868 | */ |
---|
869 | #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
---|
870 | |
---|
871 | /** |
---|
872 | * This macro indicates that @a _trap as an asynchronous trap. |
---|
873 | */ |
---|
874 | #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
---|
875 | |
---|
876 | /** |
---|
877 | * This macro indicates that @a _trap as a synchronous trap. |
---|
878 | */ |
---|
879 | #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) |
---|
880 | |
---|
881 | /** |
---|
882 | * This macro returns the real hardware vector number associated with @a _trap. |
---|
883 | */ |
---|
884 | #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) |
---|
885 | |
---|
886 | /** |
---|
887 | * This is defined if the port has a special way to report the ISR nesting |
---|
888 | * level. Most ports maintain the variable _ISR_Nest_level. |
---|
889 | */ |
---|
890 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
891 | |
---|
892 | /** |
---|
893 | * Should be large enough to run all tests. This ensures |
---|
894 | * that a "reasonable" small application should not have any problems. |
---|
895 | * |
---|
896 | * This appears to be a fairly generous number for the SPARC since |
---|
897 | * represents a call depth of about 20 routines based on the minimum |
---|
898 | * stack frame. |
---|
899 | */ |
---|
900 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
901 | |
---|
902 | /** |
---|
903 | * What is the size of a pointer on this architecture? |
---|
904 | */ |
---|
905 | #define CPU_SIZEOF_POINTER 4 |
---|
906 | |
---|
907 | /** |
---|
908 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
909 | * alignment does not take into account the requirements for the stack. |
---|
910 | * |
---|
911 | * On the SPARC, this is required for double word loads and stores. |
---|
912 | */ |
---|
913 | #define CPU_ALIGNMENT 8 |
---|
914 | |
---|
915 | /** |
---|
916 | * This number corresponds to the byte alignment requirement for the |
---|
917 | * heap handler. This alignment requirement may be stricter than that |
---|
918 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
919 | * common for the heap to follow the same alignment requirement as |
---|
920 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
921 | * then this should be set to CPU_ALIGNMENT. |
---|
922 | * |
---|
923 | * NOTE: This does not have to be a power of 2. It does have to |
---|
924 | * be greater or equal to than CPU_ALIGNMENT. |
---|
925 | */ |
---|
926 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
927 | |
---|
928 | /** |
---|
929 | * This number corresponds to the byte alignment requirement for memory |
---|
930 | * buffers allocated by the partition manager. This alignment requirement |
---|
931 | * may be stricter than that for the data types alignment specified by |
---|
932 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
933 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
934 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
935 | * |
---|
936 | * NOTE: This does not have to be a power of 2. It does have to |
---|
937 | * be greater or equal to than CPU_ALIGNMENT. |
---|
938 | */ |
---|
939 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
940 | |
---|
941 | /** |
---|
942 | * This number corresponds to the byte alignment requirement for the |
---|
943 | * stack. This alignment requirement may be stricter than that for the |
---|
944 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
945 | * is strict enough for the stack, then this should be set to 0. |
---|
946 | * |
---|
947 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
948 | * |
---|
949 | * The alignment restrictions for the SPARC are not that strict but this |
---|
950 | * should unsure that the stack is always sufficiently alignment that the |
---|
951 | * window overflow, underflow, and flush routines can use double word loads |
---|
952 | * and stores. |
---|
953 | */ |
---|
954 | #define CPU_STACK_ALIGNMENT 16 |
---|
955 | |
---|
956 | #ifndef ASM |
---|
957 | |
---|
958 | /* |
---|
959 | * ISR handler macros |
---|
960 | */ |
---|
961 | |
---|
962 | /** |
---|
963 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
964 | */ |
---|
965 | #define _CPU_Initialize_vectors() |
---|
966 | |
---|
967 | /** |
---|
968 | * Disable all interrupts for a critical section. The previous |
---|
969 | * level is returned in _level. |
---|
970 | */ |
---|
971 | #define _CPU_ISR_Disable( _level ) \ |
---|
972 | (_level) = sparc_disable_interrupts() |
---|
973 | |
---|
974 | /** |
---|
975 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
976 | * This indicates the end of a critical section. The parameter |
---|
977 | * _level is not modified. |
---|
978 | */ |
---|
979 | #define _CPU_ISR_Enable( _level ) \ |
---|
980 | sparc_enable_interrupts( _level ) |
---|
981 | |
---|
982 | /** |
---|
983 | * This temporarily restores the interrupt to _level before immediately |
---|
984 | * disabling them again. This is used to divide long critical |
---|
985 | * sections into two or more parts. The parameter _level is not |
---|
986 | * modified. |
---|
987 | */ |
---|
988 | #define _CPU_ISR_Flash( _level ) \ |
---|
989 | sparc_flash_interrupts( _level ) |
---|
990 | |
---|
991 | /** |
---|
992 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
993 | * actually provides. Currently, interrupt levels which do not |
---|
994 | * map onto the CPU in a straight fashion are undefined. |
---|
995 | */ |
---|
996 | #define _CPU_ISR_Set_level( _newlevel ) \ |
---|
997 | sparc_enable_interrupts( _newlevel << 8) |
---|
998 | |
---|
999 | /** |
---|
1000 | * @brief Obtain the current interrupt disable level. |
---|
1001 | * |
---|
1002 | * This method is invoked to return the current interrupt disable level. |
---|
1003 | * |
---|
1004 | * @return This method returns the current interrupt disable level. |
---|
1005 | */ |
---|
1006 | uint32_t _CPU_ISR_Get_level( void ); |
---|
1007 | |
---|
1008 | /* end of ISR handler macros */ |
---|
1009 | |
---|
1010 | /* Context handler macros */ |
---|
1011 | |
---|
1012 | /** |
---|
1013 | * Initialize the context to a state suitable for starting a |
---|
1014 | * task after a context restore operation. Generally, this |
---|
1015 | * involves: |
---|
1016 | * |
---|
1017 | * - setting a starting address |
---|
1018 | * - preparing the stack |
---|
1019 | * - preparing the stack and frame pointers |
---|
1020 | * - setting the proper interrupt level in the context |
---|
1021 | * - initializing the floating point context |
---|
1022 | * |
---|
1023 | * @param[in] the_context points to the context area |
---|
1024 | * @param[in] stack_base is the low address of the allocated stack area |
---|
1025 | * @param[in] size is the size of the stack area in bytes |
---|
1026 | * @param[in] new_level is the interrupt level for the task |
---|
1027 | * @param[in] entry_point is the task's entry point |
---|
1028 | * @param[in] is_fp is set to TRUE if the task is a floating point task |
---|
1029 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
1030 | * |
---|
1031 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
1032 | */ |
---|
1033 | void _CPU_Context_Initialize( |
---|
1034 | Context_Control *the_context, |
---|
1035 | uint32_t *stack_base, |
---|
1036 | uint32_t size, |
---|
1037 | uint32_t new_level, |
---|
1038 | void *entry_point, |
---|
1039 | bool is_fp, |
---|
1040 | void *tls_area |
---|
1041 | ); |
---|
1042 | |
---|
1043 | /** |
---|
1044 | * This macro is invoked from _Thread_Handler to do whatever CPU |
---|
1045 | * specific magic is required that must be done in the context of |
---|
1046 | * the thread when it starts. |
---|
1047 | * |
---|
1048 | * On the SPARC, this is setting the frame pointer so GDB is happy. |
---|
1049 | * Make GDB stop unwinding at _Thread_Handler, previous register window |
---|
1050 | * Frame pointer is 0 and calling address must be a function with starting |
---|
1051 | * with a SAVE instruction. If return address is leaf-function (no SAVE) |
---|
1052 | * GDB will not look at prev reg window fp. |
---|
1053 | * |
---|
1054 | * _Thread_Handler is known to start with SAVE. |
---|
1055 | */ |
---|
1056 | #define _CPU_Context_Initialization_at_thread_begin() \ |
---|
1057 | do { \ |
---|
1058 | __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ |
---|
1059 | } while (0) |
---|
1060 | |
---|
1061 | /** |
---|
1062 | * This routine is responsible for somehow restarting the currently |
---|
1063 | * executing task. |
---|
1064 | * |
---|
1065 | * On the SPARC, this is is relatively painless but requires a small |
---|
1066 | * amount of wrapper code before using the regular restore code in |
---|
1067 | * of the context switch. |
---|
1068 | */ |
---|
1069 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
1070 | _CPU_Context_restore( (_the_context) ); |
---|
1071 | |
---|
1072 | /** |
---|
1073 | * The FP context area for the SPARC is a simple structure and nothing |
---|
1074 | * special is required to find the "starting load point" |
---|
1075 | */ |
---|
1076 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
1077 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
1078 | |
---|
1079 | /** |
---|
1080 | * This routine initializes the FP context area passed to it to. |
---|
1081 | * |
---|
1082 | * The SPARC allows us to use the simple initialization model |
---|
1083 | * in which an "initial" FP context was saved into _CPU_Null_fp_context |
---|
1084 | * at CPU initialization and it is simply copied into the destination |
---|
1085 | * context. |
---|
1086 | */ |
---|
1087 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
1088 | do { \ |
---|
1089 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
1090 | } while (0) |
---|
1091 | |
---|
1092 | /* end of Context handler macros */ |
---|
1093 | |
---|
1094 | /* Fatal Error manager macros */ |
---|
1095 | |
---|
1096 | /** |
---|
1097 | * This routine copies _error into a known place -- typically a stack |
---|
1098 | * location or a register, optionally disables interrupts, and |
---|
1099 | * halts/stops the CPU. |
---|
1100 | */ |
---|
1101 | extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) |
---|
1102 | RTEMS_NO_RETURN; |
---|
1103 | |
---|
1104 | /* end of Fatal Error manager macros */ |
---|
1105 | |
---|
1106 | /* Bitfield handler macros */ |
---|
1107 | |
---|
1108 | #if ( SPARC_HAS_BITSCAN == 0 ) |
---|
1109 | /** |
---|
1110 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
1111 | * CPU model does not have a scan instruction. |
---|
1112 | */ |
---|
1113 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
1114 | /** |
---|
1115 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
1116 | * CPU model does not have a scan instruction. Thus is needs the generic |
---|
1117 | * data table used by that algorithm. |
---|
1118 | */ |
---|
1119 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
1120 | #else |
---|
1121 | #error "scan instruction not currently supported by RTEMS!!" |
---|
1122 | #endif |
---|
1123 | |
---|
1124 | /* end of Bitfield handler macros */ |
---|
1125 | |
---|
1126 | /* functions */ |
---|
1127 | |
---|
1128 | /** |
---|
1129 | * @brief SPARC specific initialization. |
---|
1130 | * |
---|
1131 | * This routine performs CPU dependent initialization. |
---|
1132 | */ |
---|
1133 | void _CPU_Initialize(void); |
---|
1134 | |
---|
1135 | /** |
---|
1136 | * @brief SPARC specific raw ISR installer. |
---|
1137 | * |
---|
1138 | * This routine installs @a new_handler to be directly called from the trap |
---|
1139 | * table. |
---|
1140 | * |
---|
1141 | * @param[in] vector is the vector number |
---|
1142 | * @param[in] new_handler is the new ISR handler |
---|
1143 | * @param[in] old_handler will contain the old ISR handler |
---|
1144 | */ |
---|
1145 | void _CPU_ISR_install_raw_handler( |
---|
1146 | uint32_t vector, |
---|
1147 | proc_ptr new_handler, |
---|
1148 | proc_ptr *old_handler |
---|
1149 | ); |
---|
1150 | |
---|
1151 | /** |
---|
1152 | * @brief SPARC specific RTEMS ISR installer. |
---|
1153 | * |
---|
1154 | * This routine installs an interrupt vector. |
---|
1155 | * |
---|
1156 | * @param[in] vector is the vector number |
---|
1157 | * @param[in] new_handler is the new ISR handler |
---|
1158 | * @param[in] old_handler will contain the old ISR handler |
---|
1159 | */ |
---|
1160 | |
---|
1161 | void _CPU_ISR_install_vector( |
---|
1162 | uint32_t vector, |
---|
1163 | proc_ptr new_handler, |
---|
1164 | proc_ptr *old_handler |
---|
1165 | ); |
---|
1166 | |
---|
1167 | /** |
---|
1168 | * @brief SPARC specific context switch. |
---|
1169 | * |
---|
1170 | * This routine switches from the run context to the heir context. |
---|
1171 | * |
---|
1172 | * @param[in] run is the currently executing thread |
---|
1173 | * @param[in] heir will become the currently executing thread |
---|
1174 | */ |
---|
1175 | void _CPU_Context_switch( |
---|
1176 | Context_Control *run, |
---|
1177 | Context_Control *heir |
---|
1178 | ); |
---|
1179 | |
---|
1180 | /** |
---|
1181 | * @brief SPARC specific context restore. |
---|
1182 | * |
---|
1183 | * This routine is generally used only to restart self in an |
---|
1184 | * efficient manner. |
---|
1185 | * |
---|
1186 | * @param[in] new_context is the context to restore |
---|
1187 | */ |
---|
1188 | void _CPU_Context_restore( |
---|
1189 | Context_Control *new_context |
---|
1190 | ) RTEMS_NO_RETURN; |
---|
1191 | |
---|
1192 | /** |
---|
1193 | * @brief The pointer to the current per-CPU control is available via register |
---|
1194 | * g6. |
---|
1195 | */ |
---|
1196 | register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); |
---|
1197 | |
---|
1198 | #define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current |
---|
1199 | |
---|
1200 | #if defined(RTEMS_SMP) |
---|
1201 | uint32_t _CPU_SMP_Initialize( void ); |
---|
1202 | |
---|
1203 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
1204 | |
---|
1205 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
1206 | |
---|
1207 | void _CPU_SMP_Prepare_start_multitasking( void ); |
---|
1208 | |
---|
1209 | #if defined(__leon__) && !defined(RTEMS_PARAVIRT) |
---|
1210 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
1211 | { |
---|
1212 | return _LEON3_Get_current_processor(); |
---|
1213 | } |
---|
1214 | #else |
---|
1215 | uint32_t _CPU_SMP_Get_current_processor( void ); |
---|
1216 | #endif |
---|
1217 | |
---|
1218 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
1219 | |
---|
1220 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
1221 | { |
---|
1222 | __asm__ volatile ( "" : : : "memory" ); |
---|
1223 | } |
---|
1224 | |
---|
1225 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
1226 | { |
---|
1227 | __asm__ volatile ( "" : : : "memory" ); |
---|
1228 | } |
---|
1229 | #endif |
---|
1230 | |
---|
1231 | /** |
---|
1232 | * @brief SPARC specific save FPU method. |
---|
1233 | * |
---|
1234 | * This routine saves the floating point context passed to it. |
---|
1235 | * |
---|
1236 | * @param[in] fp_context_ptr is the area to save into |
---|
1237 | */ |
---|
1238 | void _CPU_Context_save_fp( |
---|
1239 | Context_Control_fp **fp_context_ptr |
---|
1240 | ); |
---|
1241 | |
---|
1242 | /** |
---|
1243 | * @brief SPARC specific restore FPU method. |
---|
1244 | * |
---|
1245 | * This routine restores the floating point context passed to it. |
---|
1246 | * |
---|
1247 | * @param[in] fp_context_ptr is the area to restore from |
---|
1248 | */ |
---|
1249 | void _CPU_Context_restore_fp( |
---|
1250 | Context_Control_fp **fp_context_ptr |
---|
1251 | ); |
---|
1252 | |
---|
1253 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
1254 | |
---|
1255 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
1256 | |
---|
1257 | typedef struct { |
---|
1258 | uint32_t trap; |
---|
1259 | CPU_Interrupt_frame *isf; |
---|
1260 | } CPU_Exception_frame; |
---|
1261 | |
---|
1262 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
1263 | |
---|
1264 | /** |
---|
1265 | * @brief SPARC specific method to endian swap an uint32_t. |
---|
1266 | * |
---|
1267 | * The following routine swaps the endian format of an unsigned int. |
---|
1268 | * It must be static because it is referenced indirectly. |
---|
1269 | * |
---|
1270 | * @param[in] value is the value to endian swap |
---|
1271 | * |
---|
1272 | * This version will work on any processor, but if you come across a better |
---|
1273 | * way for the SPARC PLEASE use it. The most common way to swap a 32-bit |
---|
1274 | * entity as shown below is not any more efficient on the SPARC. |
---|
1275 | * |
---|
1276 | * - swap least significant two bytes with 16-bit rotate |
---|
1277 | * - swap upper and lower 16-bits |
---|
1278 | * - swap most significant two bytes with 16-bit rotate |
---|
1279 | * |
---|
1280 | * It is not obvious how the SPARC can do significantly better than the |
---|
1281 | * generic code. gcc 2.7.0 only generates about 12 instructions for the |
---|
1282 | * following code at optimization level four (i.e. -O4). |
---|
1283 | */ |
---|
1284 | static inline uint32_t CPU_swap_u32( |
---|
1285 | uint32_t value |
---|
1286 | ) |
---|
1287 | { |
---|
1288 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
1289 | |
---|
1290 | byte4 = (value >> 24) & 0xff; |
---|
1291 | byte3 = (value >> 16) & 0xff; |
---|
1292 | byte2 = (value >> 8) & 0xff; |
---|
1293 | byte1 = value & 0xff; |
---|
1294 | |
---|
1295 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
1296 | return( swapped ); |
---|
1297 | } |
---|
1298 | |
---|
1299 | /** |
---|
1300 | * @brief SPARC specific method to endian swap an uint16_t. |
---|
1301 | * |
---|
1302 | * The following routine swaps the endian format of a uint16_t. |
---|
1303 | * |
---|
1304 | * @param[in] value is the value to endian swap |
---|
1305 | */ |
---|
1306 | #define CPU_swap_u16( value ) \ |
---|
1307 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
1308 | |
---|
1309 | typedef uint32_t CPU_Counter_ticks; |
---|
1310 | |
---|
1311 | typedef CPU_Counter_ticks (*SPARC_Counter_difference)( |
---|
1312 | CPU_Counter_ticks second, |
---|
1313 | CPU_Counter_ticks first |
---|
1314 | ); |
---|
1315 | |
---|
1316 | /* |
---|
1317 | * The SPARC processors supported by RTEMS have no built-in CPU counter |
---|
1318 | * support. We have to use some hardware counter module for this purpose. The |
---|
1319 | * BSP must provide a 32-bit register which contains the current CPU counter |
---|
1320 | * value and a function for the difference calculation. It can use for example |
---|
1321 | * the GPTIMER instance used for the clock driver. |
---|
1322 | */ |
---|
1323 | typedef struct { |
---|
1324 | volatile const CPU_Counter_ticks *counter_register; |
---|
1325 | SPARC_Counter_difference counter_difference; |
---|
1326 | } SPARC_Counter; |
---|
1327 | |
---|
1328 | extern SPARC_Counter _SPARC_Counter; |
---|
1329 | |
---|
1330 | /* |
---|
1331 | * Returns always a value of one regardless of the parameters. This prevents |
---|
1332 | * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe |
---|
1333 | * default. |
---|
1334 | */ |
---|
1335 | CPU_Counter_ticks _SPARC_Counter_difference_default( |
---|
1336 | CPU_Counter_ticks second, |
---|
1337 | CPU_Counter_ticks first |
---|
1338 | ); |
---|
1339 | |
---|
1340 | static inline bool _SPARC_Counter_is_default( void ) |
---|
1341 | { |
---|
1342 | return _SPARC_Counter.counter_difference |
---|
1343 | == _SPARC_Counter_difference_default; |
---|
1344 | } |
---|
1345 | |
---|
1346 | static inline void _SPARC_Counter_initialize( |
---|
1347 | volatile const CPU_Counter_ticks *counter_register, |
---|
1348 | SPARC_Counter_difference counter_difference |
---|
1349 | ) |
---|
1350 | { |
---|
1351 | _SPARC_Counter.counter_register = counter_register; |
---|
1352 | _SPARC_Counter.counter_difference = counter_difference; |
---|
1353 | } |
---|
1354 | |
---|
1355 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
1356 | { |
---|
1357 | return *_SPARC_Counter.counter_register; |
---|
1358 | } |
---|
1359 | |
---|
1360 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
1361 | CPU_Counter_ticks second, |
---|
1362 | CPU_Counter_ticks first |
---|
1363 | ) |
---|
1364 | { |
---|
1365 | return (*_SPARC_Counter.counter_difference)( second, first ); |
---|
1366 | } |
---|
1367 | |
---|
1368 | #endif /* ASM */ |
---|
1369 | |
---|
1370 | #ifdef __cplusplus |
---|
1371 | } |
---|
1372 | #endif |
---|
1373 | |
---|
1374 | #endif |
---|