source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ a400d06f

5
Last change on this file since a400d06f was a400d06f, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 18, 2017 at 1:11:41 PM

sparc: Rename SPARC_USE_SAFE_FP_SUPPORT

Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH.
Update comment.

Update #3077.

  • Property mode set to 100644
File size: 40.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief SPARC CPU Department Source
5 *
6 * This include file contains information pertaining to the port of
7 * the executive to the SPARC processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/sparc.h>
28
29/* conditional compilation parameters */
30
31/*
32 * The SPARC ABI is a bit special with respect to the floating point context.
33 * The complete floating point context is volatile.  Thus from an ABI point
34 * of view nothing needs to be saved and restored during a context switch.
35 * Instead the floating point context must be saved and restored during
36 * interrupt processing.  Historically, the deferred floating point switch is
37 * used for SPARC and the complete floating point context is saved and
38 * restored during a context switch to the new floating point unit owner.
39 * This is a bit dangerous since post-switch actions (e.g. signal handlers)
40 * and context switch extensions may silently corrupt the floating point
41 * context.  The floating point unit is disabled for interrupt handlers.
42 * Thus in case an interrupt handler uses the floating point unit then this
43 * will result in a trap.
44 *
45 * In SMP configurations, the deferred floating point switch is not supported
46 * in principle.  So, use here a synchronous floating point switching.
47 * Synchronous means that the volatile floating point context is saved and
48 * restored around a thread dispatch issued during interrupt processing.  Thus
49 * post-switch actions and context switch extensions may safely use the
50 * floating point unit.
51 */
52#if SPARC_HAS_FPU == 1
53  #if defined(RTEMS_SMP)
54    #define SPARC_USE_SYNCHRONOUS_FP_SWITCH
55  #endif
56#endif
57
58/**
59 * Does the executive manage a dedicated interrupt stack in software?
60 *
61 * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
62 * If FALSE, nothing is done.
63 *
64 * The SPARC does not have a dedicated HW interrupt stack and one has
65 * been implemented in SW.
66 */
67#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
68
69/**
70 * Does the CPU follow the simple vectored interrupt model?
71 *
72 * - If TRUE, then RTEMS allocates the vector table it internally manages.
73 * - If FALSE, then the BSP is assumed to allocate and manage the vector
74 *   table
75 *
76 * THe SPARC is a simple vectored architecture.  Usually there is no
77 * PIC and the CPU directly vectors the interrupts.
78 */
79#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
80
81/**
82 * Does this CPU have hardware support for a dedicated interrupt stack?
83 *
84 * - If TRUE, then it must be installed during initialization.
85 * - If FALSE, then no installation is performed.
86 *
87 * The SPARC does not have a dedicated HW interrupt stack.
88 */
89#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
90
91/**
92 * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
93 *
94 * - If TRUE, then the memory is allocated during initialization.
95 * - If FALSE, then the memory is allocated during initialization.
96 *
97 * The SPARC does not have hardware support for switching to a
98 * dedicated interrupt stack.  The port includes support for doing this
99 * in software.
100 *
101 */
102#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
103
104/**
105 * Does the RTEMS invoke the user's ISR with the vector number and
106 * a pointer to the saved interrupt frame (1) or just the vector
107 * number (0)?
108 *
109 * The SPARC port does not pass an Interrupt Stack Frame pointer to
110 * interrupt handlers.
111 */
112#define CPU_ISR_PASSES_FRAME_POINTER FALSE
113
114/**
115 * Does the CPU have hardware floating point?
116 *
117 * - If TRUE, then the FLOATING_POINT task attribute is supported.
118 * - If FALSE, then the FLOATING_POINT task attribute is ignored.
119 *
120 * This is set based upon the multilib settings.
121 */
122#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
123  #define CPU_HARDWARE_FP     TRUE
124#else
125  #define CPU_HARDWARE_FP     FALSE
126#endif
127
128/**
129 * The SPARC GCC port does not have a software floating point library
130 * that requires RTEMS assistance.
131 */
132#define CPU_SOFTWARE_FP     FALSE
133
134/**
135 * Are all tasks FLOATING_POINT tasks implicitly?
136 *
137 * - If TRUE, then the FLOATING_POINT task attribute is assumed.
138 * - If FALSE, then the FLOATING_POINT task attribute is followed.
139 *
140 * The SPARC GCC port does not implicitly use floating point registers.
141 */
142#define CPU_ALL_TASKS_ARE_FP     FALSE
143
144/**
145 * Should the IDLE task have a floating point context?
146 *
147 * - If TRUE, then the IDLE task is created as a FLOATING_POINT task
148 *   and it has a floating point context which is switched in and out.
149 * - If FALSE, then the IDLE task does not have a floating point context.
150 *
151 * The IDLE task does not have to be floating point on the SPARC.
152 */
153#define CPU_IDLE_TASK_IS_FP      FALSE
154
155/**
156 * Should the saving of the floating point registers be deferred
157 * until a context switch is made to another different floating point
158 * task?
159 *
160 * - If TRUE, then the floating point context will not be stored until
161 * necessary.  It will remain in the floating point registers and not
162 * disturned until another floating point task is switched to.
163 *
164 * - If FALSE, then the floating point context is saved when a floating
165 * point task is switched out and restored when the next floating point
166 * task is restored.  The state of the floating point registers between
167 * those two operations is not specified.
168 *
169 * On the SPARC, we can disable the FPU for integer only tasks so
170 * it is safe to defer floating point context switches.
171 */
172#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
173  #define CPU_USE_DEFERRED_FP_SWITCH FALSE
174#else
175  #define CPU_USE_DEFERRED_FP_SWITCH TRUE
176#endif
177
178#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
179
180/**
181 * Does this port provide a CPU dependent IDLE task implementation?
182 *
183 * - If TRUE, then the routine _CPU_Thread_Idle_body
184 * must be provided and is the default IDLE thread body instead of
185 * _CPU_Thread_Idle_body.
186 *
187 * - If FALSE, then use the generic IDLE thread body if the BSP does
188 * not provide one.
189 *
190 * The SPARC architecture does not have a low power or halt instruction.
191 * It is left to the BSP and/or CPU specific code to provide an IDLE
192 * thread body which is aware of low power modes.
193 */
194#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
195
196/**
197 * Does the stack grow up (toward higher addresses) or down
198 * (toward lower addresses)?
199 *
200 * - If TRUE, then the grows upward.
201 * - If FALSE, then the grows toward smaller addresses.
202 *
203 * The stack grows to lower addresses on the SPARC.
204 */
205#define CPU_STACK_GROWS_UP               FALSE
206
207/* LEON3 systems may use a cache line size of 64 */
208#define CPU_CACHE_LINE_BYTES 64
209
210#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
211
212/**
213 * The following defines the number of bits actually used in the
214 * interrupt field of the task mode.  How those bits map to the
215 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
216 *
217 * The SPARC has 16 interrupt levels in the PIL field of the PSR.
218 */
219#define CPU_MODES_INTERRUPT_MASK   0x0000000F
220
221#ifndef ASM
222/**
223 * This structure represents the organization of the minimum stack frame
224 * for the SPARC.  More framing information is required in certain situaions
225 * such as when there are a large number of out parameters or when the callee
226 * must save floating point registers.
227 */
228typedef struct {
229  /** This is the offset of the l0 register. */
230  uint32_t    l0;
231  /** This is the offset of the l1 register. */
232  uint32_t    l1;
233  /** This is the offset of the l2 register. */
234  uint32_t    l2;
235  /** This is the offset of the l3 register. */
236  uint32_t    l3;
237  /** This is the offset of the l4 register. */
238  uint32_t    l4;
239  /** This is the offset of the l5 register. */
240  uint32_t    l5;
241  /** This is the offset of the l6 register. */
242  uint32_t    l6;
243  /** This is the offset of the l7 register. */
244  uint32_t    l7;
245  /** This is the offset of the l0 register. */
246  uint32_t    i0;
247  /** This is the offset of the i1 register. */
248  uint32_t    i1;
249  /** This is the offset of the i2 register. */
250  uint32_t    i2;
251  /** This is the offset of the i3 register. */
252  uint32_t    i3;
253  /** This is the offset of the i4 register. */
254  uint32_t    i4;
255  /** This is the offset of the i5 register. */
256  uint32_t    i5;
257  /** This is the offset of the i6 register. */
258  uint32_t    i6_fp;
259  /** This is the offset of the i7 register. */
260  uint32_t    i7;
261  /** This is the offset of the register used to return structures. */
262  void       *structure_return_address;
263
264  /*
265   * The following are for the callee to save the register arguments in
266   * should this be necessary.
267   */
268  /** This is the offset of the register for saved argument 0. */
269  uint32_t    saved_arg0;
270  /** This is the offset of the register for saved argument 1. */
271  uint32_t    saved_arg1;
272  /** This is the offset of the register for saved argument 2. */
273  uint32_t    saved_arg2;
274  /** This is the offset of the register for saved argument 3. */
275  uint32_t    saved_arg3;
276  /** This is the offset of the register for saved argument 4. */
277  uint32_t    saved_arg4;
278  /** This is the offset of the register for saved argument 5. */
279  uint32_t    saved_arg5;
280  /** This field pads the structure so ldd and std instructions can be used. */
281  uint32_t    pad0;
282} SPARC_Minimum_stack_frame;
283
284#endif /* ASM */
285
286/** This macro defines an offset into the stack frame for use in assembly. */
287#define CPU_STACK_FRAME_L0_OFFSET             0x00
288/** This macro defines an offset into the stack frame for use in assembly. */
289#define CPU_STACK_FRAME_L1_OFFSET             0x04
290/** This macro defines an offset into the stack frame for use in assembly. */
291#define CPU_STACK_FRAME_L2_OFFSET             0x08
292/** This macro defines an offset into the stack frame for use in assembly. */
293#define CPU_STACK_FRAME_L3_OFFSET             0x0c
294/** This macro defines an offset into the stack frame for use in assembly. */
295#define CPU_STACK_FRAME_L4_OFFSET             0x10
296/** This macro defines an offset into the stack frame for use in assembly. */
297#define CPU_STACK_FRAME_L5_OFFSET             0x14
298/** This macro defines an offset into the stack frame for use in assembly. */
299#define CPU_STACK_FRAME_L6_OFFSET             0x18
300/** This macro defines an offset into the stack frame for use in assembly. */
301#define CPU_STACK_FRAME_L7_OFFSET             0x1c
302/** This macro defines an offset into the stack frame for use in assembly. */
303#define CPU_STACK_FRAME_I0_OFFSET             0x20
304/** This macro defines an offset into the stack frame for use in assembly. */
305#define CPU_STACK_FRAME_I1_OFFSET             0x24
306/** This macro defines an offset into the stack frame for use in assembly. */
307#define CPU_STACK_FRAME_I2_OFFSET             0x28
308/** This macro defines an offset into the stack frame for use in assembly. */
309#define CPU_STACK_FRAME_I3_OFFSET             0x2c
310/** This macro defines an offset into the stack frame for use in assembly. */
311#define CPU_STACK_FRAME_I4_OFFSET             0x30
312/** This macro defines an offset into the stack frame for use in assembly. */
313#define CPU_STACK_FRAME_I5_OFFSET             0x34
314/** This macro defines an offset into the stack frame for use in assembly. */
315#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
316/** This macro defines an offset into the stack frame for use in assembly. */
317#define CPU_STACK_FRAME_I7_OFFSET             0x3c
318/** This macro defines an offset into the stack frame for use in assembly. */
319#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
320/** This macro defines an offset into the stack frame for use in assembly. */
321#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
322/** This macro defines an offset into the stack frame for use in assembly. */
323#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
324/** This macro defines an offset into the stack frame for use in assembly. */
325#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
326/** This macro defines an offset into the stack frame for use in assembly. */
327#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
328/** This macro defines an offset into the stack frame for use in assembly. */
329#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
330/** This macro defines an offset into the stack frame for use in assembly. */
331#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
332/** This macro defines an offset into the stack frame for use in assembly. */
333#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
334
335#define CPU_MAXIMUM_PROCESSORS 32
336
337/**
338 * @defgroup Contexts SPARC Context Structures
339 *
340 * @ingroup Score
341 *
342 * Generally there are 2 types of context to save.
343 *    + Interrupt registers to save
344 *    + Task level registers to save
345 *
346 * This means we have the following 3 context items:
347 *    + task level context stuff::  Context_Control
348 *    + floating point task stuff:: Context_Control_fp
349 *    + special interrupt level context :: Context_Control_interrupt
350 *
351 * On the SPARC, we are relatively conservative in that we save most
352 * of the CPU state in the context area.  The ET (enable trap) bit and
353 * the CWP (current window pointer) fields of the PSR are considered
354 * system wide resources and are not maintained on a per-thread basis.
355 */
356/**@{**/
357
358#ifndef ASM
359
360/**
361 * @brief SPARC basic context.
362 *
363 * This structure defines the non-volatile integer and processor state context
364 * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY
365 * INTERFACE - SPARC Processor Supplement", Third Edition.
366 *
367 * The registers g2 through g4 are reserved for applications.  GCC uses them as
368 * volatile registers by default.  So they are treated like volatile registers
369 * in RTEMS as well.
370 *
371 * The register g6 contains the per-CPU control of the current processor.  It
372 * is an invariant of the processor context.  This register must not be saved
373 * and restored during context switches or interrupt services.
374 */
375typedef struct {
376  /** This will contain the contents of the g5 register. */
377  uint32_t   g5;
378  /** This will contain the contents of the g7 register. */
379  uint32_t   g7;
380
381  /**
382   * This will contain the contents of the l0 and l1 registers.
383   *
384   * Using a double l0_and_l1 will put everything in this structure on a double
385   * word boundary which allows us to use double word loads and stores safely
386   * in the context switch.
387   */
388  double     l0_and_l1;
389  /** This will contain the contents of the l2 register. */
390  uint32_t   l2;
391  /** This will contain the contents of the l3 register. */
392  uint32_t   l3;
393  /** This will contain the contents of the l4 register. */
394  uint32_t   l4;
395  /** This will contain the contents of the l5 registeer.*/
396  uint32_t   l5;
397  /** This will contain the contents of the l6 register. */
398  uint32_t   l6;
399  /** This will contain the contents of the l7 register. */
400  uint32_t   l7;
401
402  /** This will contain the contents of the i0 register. */
403  uint32_t   i0;
404  /** This will contain the contents of the i1 register. */
405  uint32_t   i1;
406  /** This will contain the contents of the i2 register. */
407  uint32_t   i2;
408  /** This will contain the contents of the i3 register. */
409  uint32_t   i3;
410  /** This will contain the contents of the i4 register. */
411  uint32_t   i4;
412  /** This will contain the contents of the i5 register. */
413  uint32_t   i5;
414  /** This will contain the contents of the i6 (e.g. frame pointer) register. */
415  uint32_t   i6_fp;
416  /** This will contain the contents of the i7 register. */
417  uint32_t   i7;
418
419  /** This will contain the contents of the o6 (e.g. frame pointer) register. */
420  uint32_t   o6_sp;
421  /**
422   * This will contain the contents of the o7 (e.g. address of CALL
423   * instruction) register.
424   */
425  uint32_t   o7;
426
427  /** This will contain the contents of the processor status register. */
428  uint32_t   psr;
429  /**
430   * This field is used to prevent heavy nesting of calls to _Thread_Dispatch
431   * on an interrupted  task's stack.  This is problematic on the slower
432   * SPARC CPU models at high interrupt rates.
433   */
434  uint32_t   isr_dispatch_disable;
435
436#if defined(RTEMS_SMP)
437  volatile uint32_t is_executing;
438#endif
439} Context_Control;
440
441/**
442 * This macro provides a CPU independent way for RTEMS to access the
443 * stack pointer in a context structure. The actual name and offset is
444 * CPU architecture dependent.
445 */
446#define _CPU_Context_Get_SP( _context ) \
447  (_context)->o6_sp
448
449#ifdef RTEMS_SMP
450  static inline bool _CPU_Context_Get_is_executing(
451    const Context_Control *context
452  )
453  {
454    return context->is_executing;
455  }
456
457  static inline void _CPU_Context_Set_is_executing(
458    Context_Control *context,
459    bool is_executing
460  )
461  {
462    context->is_executing = is_executing;
463  }
464#endif
465
466#endif /* ASM */
467
468/*
469 *  Offsets of fields with Context_Control for assembly routines.
470 */
471
472/** This macro defines an offset into the context for use in assembly. */
473#define G5_OFFSET    0x00
474/** This macro defines an offset into the context for use in assembly. */
475#define G7_OFFSET    0x04
476
477/** This macro defines an offset into the context for use in assembly. */
478#define L0_OFFSET    0x08
479/** This macro defines an offset into the context for use in assembly. */
480#define L1_OFFSET    0x0C
481/** This macro defines an offset into the context for use in assembly. */
482#define L2_OFFSET    0x10
483/** This macro defines an offset into the context for use in assembly. */
484#define L3_OFFSET    0x14
485/** This macro defines an offset into the context for use in assembly. */
486#define L4_OFFSET    0x18
487/** This macro defines an offset into the context for use in assembly. */
488#define L5_OFFSET    0x1C
489/** This macro defines an offset into the context for use in assembly. */
490#define L6_OFFSET    0x20
491/** This macro defines an offset into the context for use in assembly. */
492#define L7_OFFSET    0x24
493
494/** This macro defines an offset into the context for use in assembly. */
495#define I0_OFFSET    0x28
496/** This macro defines an offset into the context for use in assembly. */
497#define I1_OFFSET    0x2C
498/** This macro defines an offset into the context for use in assembly. */
499#define I2_OFFSET    0x30
500/** This macro defines an offset into the context for use in assembly. */
501#define I3_OFFSET    0x34
502/** This macro defines an offset into the context for use in assembly. */
503#define I4_OFFSET    0x38
504/** This macro defines an offset into the context for use in assembly. */
505#define I5_OFFSET    0x3C
506/** This macro defines an offset into the context for use in assembly. */
507#define I6_FP_OFFSET 0x40
508/** This macro defines an offset into the context for use in assembly. */
509#define I7_OFFSET    0x44
510
511/** This macro defines an offset into the context for use in assembly. */
512#define O6_SP_OFFSET 0x48
513/** This macro defines an offset into the context for use in assembly. */
514#define O7_OFFSET    0x4C
515
516/** This macro defines an offset into the context for use in assembly. */
517#define PSR_OFFSET   0x50
518/** This macro defines an offset into the context for use in assembly. */
519#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54
520
521#if defined(RTEMS_SMP)
522  #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
523#endif
524
525#ifndef ASM
526/**
527 * @brief SPARC basic context.
528 *
529 * This structure defines floating point context area.
530 */
531typedef struct {
532  /** This will contain the contents of the f0 and f1 register. */
533  double      f0_f1;
534  /** This will contain the contents of the f2 and f3 register. */
535  double      f2_f3;
536  /** This will contain the contents of the f4 and f5 register. */
537  double      f4_f5;
538  /** This will contain the contents of the f6 and f7 register. */
539  double      f6_f7;
540  /** This will contain the contents of the f8 and f9 register. */
541  double      f8_f9;
542  /** This will contain the contents of the f10 and f11 register. */
543  double      f10_f11;
544  /** This will contain the contents of the f12 and f13 register. */
545  double      f12_f13;
546  /** This will contain the contents of the f14 and f15 register. */
547  double      f14_f15;
548  /** This will contain the contents of the f16 and f17 register. */
549  double      f16_f17;
550  /** This will contain the contents of the f18 and f19 register. */
551  double      f18_f19;
552  /** This will contain the contents of the f20 and f21 register. */
553  double      f20_f21;
554  /** This will contain the contents of the f22 and f23 register. */
555  double      f22_f23;
556  /** This will contain the contents of the f24 and f25 register. */
557  double      f24_f25;
558  /** This will contain the contents of the f26 and f27 register. */
559  double      f26_f27;
560  /** This will contain the contents of the f28 and f29 register. */
561  double      f28_f29;
562  /** This will contain the contents of the f30 and f31 register. */
563  double      f30_f31;
564  /** This will contain the contents of the floating point status register. */
565  uint32_t    fsr;
566} Context_Control_fp;
567
568#endif /* ASM */
569
570/*
571 *  Offsets of fields with Context_Control_fp for assembly routines.
572 */
573
574/** This macro defines an offset into the FPU context for use in assembly. */
575#define FO_F1_OFFSET     0x00
576/** This macro defines an offset into the FPU context for use in assembly. */
577#define F2_F3_OFFSET     0x08
578/** This macro defines an offset into the FPU context for use in assembly. */
579#define F4_F5_OFFSET     0x10
580/** This macro defines an offset into the FPU context for use in assembly. */
581#define F6_F7_OFFSET     0x18
582/** This macro defines an offset into the FPU context for use in assembly. */
583#define F8_F9_OFFSET     0x20
584/** This macro defines an offset into the FPU context for use in assembly. */
585#define F1O_F11_OFFSET   0x28
586/** This macro defines an offset into the FPU context for use in assembly. */
587#define F12_F13_OFFSET   0x30
588/** This macro defines an offset into the FPU context for use in assembly. */
589#define F14_F15_OFFSET   0x38
590/** This macro defines an offset into the FPU context for use in assembly. */
591#define F16_F17_OFFSET   0x40
592/** This macro defines an offset into the FPU context for use in assembly. */
593#define F18_F19_OFFSET   0x48
594/** This macro defines an offset into the FPU context for use in assembly. */
595#define F2O_F21_OFFSET   0x50
596/** This macro defines an offset into the FPU context for use in assembly. */
597#define F22_F23_OFFSET   0x58
598/** This macro defines an offset into the FPU context for use in assembly. */
599#define F24_F25_OFFSET   0x60
600/** This macro defines an offset into the FPU context for use in assembly. */
601#define F26_F27_OFFSET   0x68
602/** This macro defines an offset into the FPU context for use in assembly. */
603#define F28_F29_OFFSET   0x70
604/** This macro defines an offset into the FPU context for use in assembly. */
605#define F3O_F31_OFFSET   0x78
606/** This macro defines an offset into the FPU context for use in assembly. */
607#define FSR_OFFSET       0x80
608
609/** This defines the size of the FPU context area for use in assembly. */
610#define CONTEXT_CONTROL_FP_SIZE 0x84
611
612#ifndef ASM
613
614/** @} */
615
616/**
617 * @brief Interrupt stack frame (ISF).
618 *
619 * Context saved on stack for an interrupt.
620 *
621 * NOTE: The PSR, PC, and NPC are only saved in this structure for the
622 *       benefit of the user's handler.
623 */
624typedef struct {
625  /** On an interrupt, we must save the minimum stack frame. */
626  SPARC_Minimum_stack_frame Stack_frame;
627  /** This is the offset of the PSR on an ISF. */
628  uint32_t                 psr;
629  /** This is the offset of the XXX on an ISF. */
630  uint32_t                 pc;
631  /** This is the offset of the XXX on an ISF. */
632  uint32_t                 npc;
633  /** This is the offset of the g1 register on an ISF. */
634  uint32_t                 g1;
635  /** This is the offset of the g2 register on an ISF. */
636  uint32_t                 g2;
637  /** This is the offset of the g3 register on an ISF. */
638  uint32_t                 g3;
639  /** This is the offset of the g4 register on an ISF. */
640  uint32_t                 g4;
641  /** This is the offset of the g5 register on an ISF. */
642  uint32_t                 g5;
643  /** This is the offset is reserved for alignment on an ISF. */
644  uint32_t                 reserved_for_alignment;
645  /** This is the offset of the g7 register on an ISF. */
646  uint32_t                 g7;
647  /** This is the offset of the i0 register on an ISF. */
648  uint32_t                 i0;
649  /** This is the offset of the i1 register on an ISF. */
650  uint32_t                 i1;
651  /** This is the offset of the i2 register on an ISF. */
652  uint32_t                 i2;
653  /** This is the offset of the i3 register on an ISF. */
654  uint32_t                 i3;
655  /** This is the offset of the i4 register on an ISF. */
656  uint32_t                 i4;
657  /** This is the offset of the i5 register on an ISF. */
658  uint32_t                 i5;
659  /** This is the offset of the i6 register on an ISF. */
660  uint32_t                 i6_fp;
661  /** This is the offset of the i7 register on an ISF. */
662  uint32_t                 i7;
663  /** This is the offset of the y register on an ISF. */
664  uint32_t                 y;
665  /** This is the offset of the tpc register on an ISF. */
666  uint32_t                 tpc;
667} CPU_Interrupt_frame;
668
669#endif /* ASM */
670
671#ifndef ASM
672/**
673 * This variable is contains the initialize context for the FP unit.
674 * It is filled in by _CPU_Initialize and copied into the task's FP
675 * context area during _CPU_Context_Initialize.
676 */
677extern Context_Control_fp _CPU_Null_fp_context;
678
679/**
680 * The following type defines an entry in the SPARC's trap table.
681 *
682 * NOTE: The instructions chosen are RTEMS dependent although one is
683 *       obligated to use two of the four instructions to perform a
684 *       long jump.  The other instructions load one register with the
685 *       trap type (a.k.a. vector) and another with the psr.
686 */
687typedef struct {
688  /** This will contain a "mov %psr, %l0" instruction. */
689  uint32_t     mov_psr_l0;
690  /** This will contain a "sethi %hi(_handler), %l4" instruction. */
691  uint32_t     sethi_of_handler_to_l4;
692  /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */
693  uint32_t     jmp_to_low_of_handler_plus_l4;
694  /** This will contain a " mov _vector, %l3" instruction. */
695  uint32_t     mov_vector_l3;
696} CPU_Trap_table_entry;
697
698/**
699 * This is the set of opcodes for the instructions loaded into a trap
700 * table entry.  The routine which installs a handler is responsible
701 * for filling in the fields for the _handler address and the _vector
702 * trap type.
703 *
704 * The constants following this structure are masks for the fields which
705 * must be filled in when the handler is installed.
706 */
707extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
708
709/**
710 * The size of the floating point context area.
711 */
712#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
713
714#endif
715
716/**
717 * Amount of extra stack (above minimum stack size) required by
718 * MPCI receive server thread.  Remember that in a multiprocessor
719 * system this thread must exist and be able to process all directives.
720 */
721#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
722
723/**
724 * This defines the number of entries in the ISR_Vector_table managed
725 * by the executive.
726 *
727 * On the SPARC, there are really only 256 vectors.  However, the executive
728 * has no easy, fast, reliable way to determine which traps are synchronous
729 * and which are asynchronous.  By default, synchronous traps return to the
730 * instruction which caused the interrupt.  So if you install a software
731 * trap handler as an executive interrupt handler (which is desirable since
732 * RTEMS takes care of window and register issues), then the executive needs
733 * to know that the return address is to the trap rather than the instruction
734 * following the trap.
735 *
736 * So vectors 0 through 255 are treated as regular asynchronous traps which
737 * provide the "correct" return address.  Vectors 256 through 512 are assumed
738 * by the executive to be synchronous and to require that the return address
739 * be fudged.
740 *
741 * If you use this mechanism to install a trap handler which must reexecute
742 * the instruction which caused the trap, then it should be installed as
743 * an asynchronous trap.  This will avoid the executive changing the return
744 * address.
745 */
746#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
747
748/**
749 * The SPARC has 256 vectors but the port treats 256-512 as synchronous
750 * traps.
751 */
752#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
753
754/**
755 * This is the bit step in a vector number to indicate it is being installed
756 * as a synchronous trap.
757 */
758#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
759
760/**
761 * This macro indicates that @a _trap as an asynchronous trap.
762 */
763#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
764
765/**
766 * This macro indicates that @a _trap as a synchronous trap.
767 */
768#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
769
770/**
771 * This macro returns the real hardware vector number associated with @a _trap.
772 */
773#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
774
775/**
776 * This is defined if the port has a special way to report the ISR nesting
777 * level.  Most ports maintain the variable _ISR_Nest_level.
778 */
779#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
780
781/**
782 * Should be large enough to run all tests.  This ensures
783 * that a "reasonable" small application should not have any problems.
784 *
785 * This appears to be a fairly generous number for the SPARC since
786 * represents a call depth of about 20 routines based on the minimum
787 * stack frame.
788 */
789#define CPU_STACK_MINIMUM_SIZE  (1024*4)
790
791/**
792 * What is the size of a pointer on this architecture?
793 */
794#define CPU_SIZEOF_POINTER 4
795
796/**
797 * CPU's worst alignment requirement for data types on a byte boundary.  This
798 * alignment does not take into account the requirements for the stack.
799 *
800 * On the SPARC, this is required for double word loads and stores.
801 */
802#define CPU_ALIGNMENT      8
803
804/**
805 * This number corresponds to the byte alignment requirement for the
806 * heap handler.  This alignment requirement may be stricter than that
807 * for the data types alignment specified by CPU_ALIGNMENT.  It is
808 * common for the heap to follow the same alignment requirement as
809 * CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
810 * then this should be set to CPU_ALIGNMENT.
811 *
812 * NOTE:  This does not have to be a power of 2.  It does have to
813 *        be greater or equal to than CPU_ALIGNMENT.
814 */
815#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
816
817/**
818 * This number corresponds to the byte alignment requirement for memory
819 * buffers allocated by the partition manager.  This alignment requirement
820 * may be stricter than that for the data types alignment specified by
821 * CPU_ALIGNMENT.  It is common for the partition to follow the same
822 * alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
823 * enough for the partition, then this should be set to CPU_ALIGNMENT.
824 *
825 * NOTE:  This does not have to be a power of 2.  It does have to
826 *        be greater or equal to than CPU_ALIGNMENT.
827 */
828#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
829
830/**
831 * Stack frames must be doubleword aligned according to the System V ABI for
832 * SPARC.
833 */
834#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
835
836#ifndef ASM
837
838/*
839 *  ISR handler macros
840 */
841
842/**
843 * Support routine to initialize the RTEMS vector table after it is allocated.
844 */
845#define _CPU_Initialize_vectors()
846
847/**
848 * Disable all interrupts for a critical section.  The previous
849 * level is returned in _level.
850 */
851#define _CPU_ISR_Disable( _level ) \
852  (_level) = sparc_disable_interrupts()
853
854/**
855 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
856 * This indicates the end of a critical section.  The parameter
857 * _level is not modified.
858 */
859#define _CPU_ISR_Enable( _level ) \
860  sparc_enable_interrupts( _level )
861
862/**
863 * This temporarily restores the interrupt to _level before immediately
864 * disabling them again.  This is used to divide long critical
865 * sections into two or more parts.  The parameter _level is not
866 * modified.
867 */
868#define _CPU_ISR_Flash( _level ) \
869  sparc_flash_interrupts( _level )
870
871#define _CPU_ISR_Is_enabled( _isr_cookie ) \
872  sparc_interrupt_is_enabled( _isr_cookie )
873
874RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
875{
876  return ( level & SPARC_PSR_PIL_MASK ) == 0;
877}
878
879/**
880 * Map interrupt level in task mode onto the hardware that the CPU
881 * actually provides.  Currently, interrupt levels which do not
882 * map onto the CPU in a straight fashion are undefined.
883 */
884#define _CPU_ISR_Set_level( _newlevel ) \
885   sparc_enable_interrupts( _newlevel << 8)
886
887/**
888 * @brief Obtain the current interrupt disable level.
889 *
890 * This method is invoked to return the current interrupt disable level.
891 *
892 * @return This method returns the current interrupt disable level.
893 */
894uint32_t   _CPU_ISR_Get_level( void );
895
896/* end of ISR handler macros */
897
898/* Context handler macros */
899
900/**
901 * Initialize the context to a state suitable for starting a
902 * task after a context restore operation.  Generally, this
903 * involves:
904 *
905 * - setting a starting address
906 * - preparing the stack
907 * - preparing the stack and frame pointers
908 * - setting the proper interrupt level in the context
909 * - initializing the floating point context
910 *
911 * @param[in] the_context points to the context area
912 * @param[in] stack_base is the low address of the allocated stack area
913 * @param[in] size is the size of the stack area in bytes
914 * @param[in] new_level is the interrupt level for the task
915 * @param[in] entry_point is the task's entry point
916 * @param[in] is_fp is set to TRUE if the task is a floating point task
917 * @param[in] tls_area is the thread-local storage (TLS) area
918 *
919 * NOTE:  Implemented as a subroutine for the SPARC port.
920 */
921void _CPU_Context_Initialize(
922  Context_Control  *the_context,
923  uint32_t         *stack_base,
924  uint32_t          size,
925  uint32_t          new_level,
926  void             *entry_point,
927  bool              is_fp,
928  void             *tls_area
929);
930
931/**
932 * This macro is invoked from _Thread_Handler to do whatever CPU
933 * specific magic is required that must be done in the context of
934 * the thread when it starts.
935 *
936 * On the SPARC, this is setting the frame pointer so GDB is happy.
937 * Make GDB stop unwinding at _Thread_Handler, previous register window
938 * Frame pointer is 0 and calling address must be a function with starting
939 * with a SAVE instruction. If return address is leaf-function (no SAVE)
940 * GDB will not look at prev reg window fp.
941 *
942 * _Thread_Handler is known to start with SAVE.
943 */
944#define _CPU_Context_Initialization_at_thread_begin() \
945  do { \
946    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
947  } while (0)
948
949/**
950 * This routine is responsible for somehow restarting the currently
951 * executing task.
952 *
953 * On the SPARC, this is is relatively painless but requires a small
954 * amount of wrapper code before using the regular restore code in
955 * of the context switch.
956 */
957#define _CPU_Context_Restart_self( _the_context ) \
958   _CPU_Context_restore( (_the_context) );
959
960/**
961 * This routine initializes the FP context area passed to it to.
962 *
963 * The SPARC allows us to use the simple initialization model
964 * in which an "initial" FP context was saved into _CPU_Null_fp_context
965 * at CPU initialization and it is simply copied into the destination
966 * context.
967 */
968#define _CPU_Context_Initialize_fp( _destination ) \
969  do { \
970   *(*(_destination)) = _CPU_Null_fp_context; \
971  } while (0)
972
973/* end of Context handler macros */
974
975/* Fatal Error manager macros */
976
977/**
978 * This routine copies _error into a known place -- typically a stack
979 * location or a register, optionally disables interrupts, and
980 * halts/stops the CPU.
981 */
982extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
983  RTEMS_NO_RETURN;
984
985/* end of Fatal Error manager macros */
986
987/* Bitfield handler macros */
988
989#if ( SPARC_HAS_BITSCAN == 0 )
990  /**
991   * The SPARC port uses the generic C algorithm for bitfield scan if the
992   * CPU model does not have a scan instruction.
993   */
994  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
995#else
996  #error "scan instruction not currently supported by RTEMS!!"
997#endif
998
999/* end of Bitfield handler macros */
1000
1001/* functions */
1002
1003/**
1004 * @brief SPARC specific initialization.
1005 *
1006 * This routine performs CPU dependent initialization.
1007 */
1008void _CPU_Initialize(void);
1009
1010/**
1011 * @brief SPARC specific raw ISR installer.
1012 *
1013 * This routine installs @a new_handler to be directly called from the trap
1014 * table.
1015 *
1016 * @param[in] vector is the vector number
1017 * @param[in] new_handler is the new ISR handler
1018 * @param[in] old_handler will contain the old ISR handler
1019 */
1020void _CPU_ISR_install_raw_handler(
1021  uint32_t    vector,
1022  proc_ptr    new_handler,
1023  proc_ptr   *old_handler
1024);
1025
1026/**
1027 * @brief SPARC specific RTEMS ISR installer.
1028 *
1029 * This routine installs an interrupt vector.
1030 *
1031 * @param[in] vector is the vector number
1032 * @param[in] new_handler is the new ISR handler
1033 * @param[in] old_handler will contain the old ISR handler
1034 */
1035
1036void _CPU_ISR_install_vector(
1037  uint32_t    vector,
1038  proc_ptr    new_handler,
1039  proc_ptr   *old_handler
1040);
1041
1042/**
1043 * @brief SPARC specific context switch.
1044 *
1045 * This routine switches from the run context to the heir context.
1046 *
1047 * @param[in] run is the currently executing thread
1048 * @param[in] heir will become the currently executing thread
1049 */
1050void _CPU_Context_switch(
1051  Context_Control  *run,
1052  Context_Control  *heir
1053);
1054
1055/**
1056 * @brief SPARC specific context restore.
1057 *
1058 * This routine is generally used only to restart self in an
1059 * efficient manner.
1060 *
1061 * @param[in] new_context is the context to restore
1062 */
1063void _CPU_Context_restore(
1064  Context_Control *new_context
1065) RTEMS_NO_RETURN;
1066
1067#if defined(RTEMS_SMP)
1068  uint32_t _CPU_SMP_Initialize( void );
1069
1070  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1071
1072  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1073
1074  void _CPU_SMP_Prepare_start_multitasking( void );
1075
1076  #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
1077    static inline uint32_t _CPU_SMP_Get_current_processor( void )
1078    {
1079      return _LEON3_Get_current_processor();
1080    }
1081  #else
1082    uint32_t _CPU_SMP_Get_current_processor( void );
1083  #endif
1084
1085  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1086
1087  static inline void _CPU_SMP_Processor_event_broadcast( void )
1088  {
1089    __asm__ volatile ( "" : : : "memory" );
1090  }
1091
1092  static inline void _CPU_SMP_Processor_event_receive( void )
1093  {
1094    __asm__ volatile ( "" : : : "memory" );
1095  }
1096#endif
1097
1098/**
1099 * @brief SPARC specific save FPU method.
1100 *
1101 * This routine saves the floating point context passed to it.
1102 *
1103 * @param[in] fp_context_ptr is the area to save into
1104 */
1105void _CPU_Context_save_fp(
1106  Context_Control_fp **fp_context_ptr
1107);
1108
1109/**
1110 * @brief SPARC specific restore FPU method.
1111 *
1112 * This routine restores the floating point context passed to it.
1113 *
1114 * @param[in] fp_context_ptr is the area to restore from
1115 */
1116void _CPU_Context_restore_fp(
1117  Context_Control_fp **fp_context_ptr
1118);
1119
1120void _CPU_Context_volatile_clobber( uintptr_t pattern );
1121
1122void _CPU_Context_validate( uintptr_t pattern );
1123
1124typedef struct {
1125  uint32_t trap;
1126  CPU_Interrupt_frame *isf;
1127} CPU_Exception_frame;
1128
1129void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1130
1131/**
1132 * @brief SPARC specific method to endian swap an uint32_t.
1133 *
1134 * The following routine swaps the endian format of an unsigned int.
1135 * It must be static because it is referenced indirectly.
1136 *
1137 * @param[in] value is the value to endian swap
1138 *
1139 * This version will work on any processor, but if you come across a better
1140 * way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
1141 * entity as shown below is not any more efficient on the SPARC.
1142 *
1143 *    - swap least significant two bytes with 16-bit rotate
1144 *    - swap upper and lower 16-bits
1145 *    - swap most significant two bytes with 16-bit rotate
1146 *
1147 * It is not obvious how the SPARC can do significantly better than the
1148 * generic code.  gcc 2.7.0 only generates about 12 instructions for the
1149 * following code at optimization level four (i.e. -O4).
1150 */
1151static inline uint32_t CPU_swap_u32(
1152  uint32_t value
1153)
1154{
1155  uint32_t   byte1, byte2, byte3, byte4, swapped;
1156
1157  byte4 = (value >> 24) & 0xff;
1158  byte3 = (value >> 16) & 0xff;
1159  byte2 = (value >> 8)  & 0xff;
1160  byte1 =  value        & 0xff;
1161
1162  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1163  return( swapped );
1164}
1165
1166/**
1167 * @brief SPARC specific method to endian swap an uint16_t.
1168 *
1169 * The following routine swaps the endian format of a uint16_t.
1170 *
1171 * @param[in] value is the value to endian swap
1172 */
1173#define CPU_swap_u16( value ) \
1174  (((value&0xff) << 8) | ((value >> 8)&0xff))
1175
1176typedef uint32_t CPU_Counter_ticks;
1177
1178typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
1179
1180typedef CPU_Counter_ticks ( *SPARC_Counter_difference )(
1181  CPU_Counter_ticks second,
1182  CPU_Counter_ticks first
1183);
1184
1185/*
1186 * The SPARC processors supported by RTEMS have no built-in CPU counter
1187 * support.  We have to use some hardware counter module for this purpose, for
1188 * example the GPTIMER instance used by the clock driver.  The BSP must provide
1189 * an implementation of the CPU counter read and difference functions.  This
1190 * allows the use of dynamic hardware enumeration.
1191 */
1192typedef struct {
1193  SPARC_Counter_read                counter_read;
1194  SPARC_Counter_difference          counter_difference;
1195  volatile const CPU_Counter_ticks *counter_address;
1196} SPARC_Counter;
1197
1198extern const SPARC_Counter _SPARC_Counter;
1199
1200static inline CPU_Counter_ticks _CPU_Counter_read( void )
1201{
1202  return ( *_SPARC_Counter.counter_read )();
1203}
1204
1205static inline CPU_Counter_ticks _CPU_Counter_difference(
1206  CPU_Counter_ticks second,
1207  CPU_Counter_ticks first
1208)
1209{
1210  return ( *_SPARC_Counter.counter_difference )( second, first );
1211}
1212
1213#endif /* ASM */
1214
1215#ifdef __cplusplus
1216}
1217#endif
1218
1219#endif
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