source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ 8e87c6e9

4.104.114.84.9
Last change on this file since 8e87c6e9 was 8e87c6e9, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:16:32 PM

2002-04-01 Ralf Corsepius <corsepiu@…>

  • cpu.c: Remove call to sparc_init_tbr/NO_TABLE_MOVE.
  • rtems/score/cpu.h: Remove NO_TABLE_MOVE conditional code.
  • Property mode set to 100644
File size: 28.3 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the port of
4 *  the executive to the SPARC processor.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/sparc.h>               /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/types.h>
26#endif
27
28/* conditional compilation parameters */
29
30/*
31 *  Should the calls to _Thread_Enable_dispatch be inlined?
32 *
33 *  If TRUE, then they are inlined.
34 *  If FALSE, then a subroutine call is made.
35 */
36
37#define CPU_INLINE_ENABLE_DISPATCH       TRUE
38
39/*
40 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
41 *  be unrolled one time?  In unrolled each iteration of the loop examines
42 *  two "nodes" on the chain being searched.  Otherwise, only one node
43 *  is examined per iteration.
44 *
45 *  If TRUE, then the loops are unrolled.
46 *  If FALSE, then the loops are not unrolled.
47 *
48 *  This parameter could go either way on the SPARC.  The interrupt flash
49 *  code is relatively lengthy given the requirements for nops following
50 *  writes to the psr.  But if the clock speed were high enough, this would
51 *  not represent a great deal of time.
52 */
53
54#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
55
56/*
57 *  Does the executive manage a dedicated interrupt stack in software?
58 *
59 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
60 *  If FALSE, nothing is done.
61 *
62 *  The SPARC does not have a dedicated HW interrupt stack and one has
63 *  been implemented in SW.
64 */
65
66#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
67
68/*
69 *  Does this CPU have hardware support for a dedicated interrupt stack?
70 *
71 *  If TRUE, then it must be installed during initialization.
72 *  If FALSE, then no installation is performed.
73 *
74 *  The SPARC does not have a dedicated HW interrupt stack.
75 */
76
77#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
78
79/*
80 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
81 *
82 *  If TRUE, then the memory is allocated during initialization.
83 *  If FALSE, then the memory is allocated during initialization.
84 */
85
86#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
87
88/*
89 *  Does the RTEMS invoke the user's ISR with the vector number and
90 *  a pointer to the saved interrupt frame (1) or just the vector
91 *  number (0)?
92 */
93
94#define CPU_ISR_PASSES_FRAME_POINTER 0
95
96/*
97 *  Does the CPU have hardware floating point?
98 *
99 *  If TRUE, then the FLOATING_POINT task attribute is supported.
100 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
101 */
102
103#if ( SPARC_HAS_FPU == 1 )
104#define CPU_HARDWARE_FP     TRUE
105#else
106#define CPU_HARDWARE_FP     FALSE
107#endif
108#define CPU_SOFTWARE_FP     FALSE
109
110/*
111 *  Are all tasks FLOATING_POINT tasks implicitly?
112 *
113 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
114 *  If FALSE, then the FLOATING_POINT task attribute is followed.
115 */
116
117#define CPU_ALL_TASKS_ARE_FP     FALSE
118
119/*
120 *  Should the IDLE task have a floating point context?
121 *
122 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
123 *  and it has a floating point context which is switched in and out.
124 *  If FALSE, then the IDLE task does not have a floating point context.
125 */
126
127#define CPU_IDLE_TASK_IS_FP      FALSE
128
129/*
130 *  Should the saving of the floating point registers be deferred
131 *  until a context switch is made to another different floating point
132 *  task?
133 *
134 *  If TRUE, then the floating point context will not be stored until
135 *  necessary.  It will remain in the floating point registers and not
136 *  disturned until another floating point task is switched to.
137 *
138 *  If FALSE, then the floating point context is saved when a floating
139 *  point task is switched out and restored when the next floating point
140 *  task is restored.  The state of the floating point registers between
141 *  those two operations is not specified.
142 */
143
144#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
145
146/*
147 *  Does this port provide a CPU dependent IDLE task implementation?
148 *
149 *  If TRUE, then the routine _CPU_Thread_Idle_body
150 *  must be provided and is the default IDLE thread body instead of
151 *  _CPU_Thread_Idle_body.
152 *
153 *  If FALSE, then use the generic IDLE thread body if the BSP does
154 *  not provide one.
155 */
156
157#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
158
159/*
160 *  Does the stack grow up (toward higher addresses) or down
161 *  (toward lower addresses)?
162 *
163 *  If TRUE, then the grows upward.
164 *  If FALSE, then the grows toward smaller addresses.
165 *
166 *  The stack grows to lower addresses on the SPARC.
167 */
168
169#define CPU_STACK_GROWS_UP               FALSE
170
171/*
172 *  The following is the variable attribute used to force alignment
173 *  of critical data structures.  On some processors it may make
174 *  sense to have these aligned on tighter boundaries than
175 *  the minimum requirements of the compiler in order to have as
176 *  much of the critical data area as possible in a cache line.
177 *
178 *  The SPARC does not appear to have particularly strict alignment
179 *  requirements.  This value was chosen to take advantages of caches.
180 */
181
182#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
183
184/*
185 *  Define what is required to specify how the network to host conversion
186 *  routines are handled.
187 */
188
189#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
190#define CPU_BIG_ENDIAN                           TRUE
191#define CPU_LITTLE_ENDIAN                        FALSE
192
193/*
194 *  The following defines the number of bits actually used in the
195 *  interrupt field of the task mode.  How those bits map to the
196 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
197 *
198 *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
199 */
200
201#define CPU_MODES_INTERRUPT_MASK   0x0000000F
202
203/*
204 *  This structure represents the organization of the minimum stack frame
205 *  for the SPARC.  More framing information is required in certain situaions
206 *  such as when there are a large number of out parameters or when the callee
207 *  must save floating point registers.
208 */
209
210#ifndef ASM
211
212typedef struct {
213  unsigned32  l0;
214  unsigned32  l1;
215  unsigned32  l2;
216  unsigned32  l3;
217  unsigned32  l4;
218  unsigned32  l5;
219  unsigned32  l6;
220  unsigned32  l7;
221  unsigned32  i0;
222  unsigned32  i1;
223  unsigned32  i2;
224  unsigned32  i3;
225  unsigned32  i4;
226  unsigned32  i5;
227  unsigned32  i6_fp;
228  unsigned32  i7;
229  void       *structure_return_address;
230  /*
231   *  The following are for the callee to save the register arguments in
232   *  should this be necessary.
233   */
234  unsigned32  saved_arg0;
235  unsigned32  saved_arg1;
236  unsigned32  saved_arg2;
237  unsigned32  saved_arg3;
238  unsigned32  saved_arg4;
239  unsigned32  saved_arg5;
240  unsigned32  pad0;
241}  CPU_Minimum_stack_frame;
242
243#endif /* ASM */
244
245#define CPU_STACK_FRAME_L0_OFFSET             0x00
246#define CPU_STACK_FRAME_L1_OFFSET             0x04
247#define CPU_STACK_FRAME_L2_OFFSET             0x08
248#define CPU_STACK_FRAME_L3_OFFSET             0x0c
249#define CPU_STACK_FRAME_L4_OFFSET             0x10
250#define CPU_STACK_FRAME_L5_OFFSET             0x14
251#define CPU_STACK_FRAME_L6_OFFSET             0x18
252#define CPU_STACK_FRAME_L7_OFFSET             0x1c
253#define CPU_STACK_FRAME_I0_OFFSET             0x20
254#define CPU_STACK_FRAME_I1_OFFSET             0x24
255#define CPU_STACK_FRAME_I2_OFFSET             0x28
256#define CPU_STACK_FRAME_I3_OFFSET             0x2c
257#define CPU_STACK_FRAME_I4_OFFSET             0x30
258#define CPU_STACK_FRAME_I5_OFFSET             0x34
259#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
260#define CPU_STACK_FRAME_I7_OFFSET             0x3c
261#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
262#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
263#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
264#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
265#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
266#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
267#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
268#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
269
270#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
271
272/*
273 * Contexts
274 *
275 *  Generally there are 2 types of context to save.
276 *     1. Interrupt registers to save
277 *     2. Task level registers to save
278 *
279 *  This means we have the following 3 context items:
280 *     1. task level context stuff::  Context_Control
281 *     2. floating point task stuff:: Context_Control_fp
282 *     3. special interrupt level context :: Context_Control_interrupt
283 *
284 *  On the SPARC, we are relatively conservative in that we save most
285 *  of the CPU state in the context area.  The ET (enable trap) bit and
286 *  the CWP (current window pointer) fields of the PSR are considered
287 *  system wide resources and are not maintained on a per-thread basis.
288 */
289
290#ifndef ASM
291
292typedef struct {
293    /*
294     *  Using a double g0_g1 will put everything in this structure on a
295     *  double word boundary which allows us to use double word loads
296     *  and stores safely in the context switch.
297     */
298    double     g0_g1;
299    unsigned32 g2;
300    unsigned32 g3;
301    unsigned32 g4;
302    unsigned32 g5;
303    unsigned32 g6;
304    unsigned32 g7;
305
306    unsigned32 l0;
307    unsigned32 l1;
308    unsigned32 l2;
309    unsigned32 l3;
310    unsigned32 l4;
311    unsigned32 l5;
312    unsigned32 l6;
313    unsigned32 l7;
314
315    unsigned32 i0;
316    unsigned32 i1;
317    unsigned32 i2;
318    unsigned32 i3;
319    unsigned32 i4;
320    unsigned32 i5;
321    unsigned32 i6_fp;
322    unsigned32 i7;
323
324    unsigned32 o0;
325    unsigned32 o1;
326    unsigned32 o2;
327    unsigned32 o3;
328    unsigned32 o4;
329    unsigned32 o5;
330    unsigned32 o6_sp;
331    unsigned32 o7;
332
333    unsigned32 psr;
334} Context_Control;
335
336#endif /* ASM */
337
338/*
339 *  Offsets of fields with Context_Control for assembly routines.
340 */
341
342#define G0_OFFSET    0x00
343#define G1_OFFSET    0x04
344#define G2_OFFSET    0x08
345#define G3_OFFSET    0x0C
346#define G4_OFFSET    0x10
347#define G5_OFFSET    0x14
348#define G6_OFFSET    0x18
349#define G7_OFFSET    0x1C
350
351#define L0_OFFSET    0x20
352#define L1_OFFSET    0x24
353#define L2_OFFSET    0x28
354#define L3_OFFSET    0x2C
355#define L4_OFFSET    0x30
356#define L5_OFFSET    0x34
357#define L6_OFFSET    0x38
358#define L7_OFFSET    0x3C
359
360#define I0_OFFSET    0x40
361#define I1_OFFSET    0x44
362#define I2_OFFSET    0x48
363#define I3_OFFSET    0x4C
364#define I4_OFFSET    0x50
365#define I5_OFFSET    0x54
366#define I6_FP_OFFSET 0x58
367#define I7_OFFSET    0x5C
368
369#define O0_OFFSET    0x60
370#define O1_OFFSET    0x64
371#define O2_OFFSET    0x68
372#define O3_OFFSET    0x6C
373#define O4_OFFSET    0x70
374#define O5_OFFSET    0x74
375#define O6_SP_OFFSET 0x78
376#define O7_OFFSET    0x7C
377
378#define PSR_OFFSET   0x80
379
380#define CONTEXT_CONTROL_SIZE 0x84
381
382/*
383 *  The floating point context area.
384 */
385
386#ifndef ASM
387
388typedef struct {
389    double      f0_f1;
390    double      f2_f3;
391    double      f4_f5;
392    double      f6_f7;
393    double      f8_f9;
394    double      f10_f11;
395    double      f12_f13;
396    double      f14_f15;
397    double      f16_f17;
398    double      f18_f19;
399    double      f20_f21;
400    double      f22_f23;
401    double      f24_f25;
402    double      f26_f27;
403    double      f28_f29;
404    double      f30_f31;
405    unsigned32  fsr;
406} Context_Control_fp;
407
408#endif /* ASM */
409
410/*
411 *  Offsets of fields with Context_Control_fp for assembly routines.
412 */
413
414#define FO_F1_OFFSET     0x00
415#define F2_F3_OFFSET     0x08
416#define F4_F5_OFFSET     0x10
417#define F6_F7_OFFSET     0x18
418#define F8_F9_OFFSET     0x20
419#define F1O_F11_OFFSET   0x28
420#define F12_F13_OFFSET   0x30
421#define F14_F15_OFFSET   0x38
422#define F16_F17_OFFSET   0x40
423#define F18_F19_OFFSET   0x48
424#define F2O_F21_OFFSET   0x50
425#define F22_F23_OFFSET   0x58
426#define F24_F25_OFFSET   0x60
427#define F26_F27_OFFSET   0x68
428#define F28_F29_OFFSET   0x70
429#define F3O_F31_OFFSET   0x78
430#define FSR_OFFSET       0x80
431
432#define CONTEXT_CONTROL_FP_SIZE 0x84
433
434#ifndef ASM
435
436/*
437 *  Context saved on stack for an interrupt.
438 *
439 *  NOTE:  The PSR, PC, and NPC are only saved in this structure for the
440 *         benefit of the user's handler.
441 */
442
443typedef struct {
444  CPU_Minimum_stack_frame  Stack_frame;
445  unsigned32               psr;
446  unsigned32               pc;
447  unsigned32               npc;
448  unsigned32               g1;
449  unsigned32               g2;
450  unsigned32               g3;
451  unsigned32               g4;
452  unsigned32               g5;
453  unsigned32               g6;
454  unsigned32               g7;
455  unsigned32               i0;
456  unsigned32               i1;
457  unsigned32               i2;
458  unsigned32               i3;
459  unsigned32               i4;
460  unsigned32               i5;
461  unsigned32               i6_fp;
462  unsigned32               i7;
463  unsigned32               y;
464  unsigned32               tpc;
465} CPU_Interrupt_frame;
466
467#endif /* ASM */
468
469/*
470 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
471 */
472
473#define ISF_STACK_FRAME_OFFSET 0x00
474#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
475#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
476#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
477#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
478#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
479#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
480#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
481#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
482#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
483#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
484#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
485#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
486#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
487#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
488#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
489#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
490#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
491#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
492#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
493#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
494
495#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
496#ifndef ASM
497
498/*
499 *  The following table contains the information required to configure
500 *  the processor specific parameters.
501 */
502
503typedef struct {
504  void       (*pretasking_hook)( void );
505  void       (*predriver_hook)( void );
506  void       (*postdriver_hook)( void );
507  void       (*idle_task)( void );
508  boolean      do_zero_of_workspace;
509  unsigned32   idle_task_stack_size;
510  unsigned32   interrupt_stack_size;
511  unsigned32   extra_mpci_receive_server_stack;
512  void *     (*stack_allocate_hook)( unsigned32 );
513  void       (*stack_free_hook)( void* );
514  /* end of fields required on all CPUs */
515
516}   rtems_cpu_table;
517
518/*
519 *  Macros to access required entires in the CPU Table are in
520 *  the file rtems/system.h.
521 */
522
523/*
524 *  Macros to access SPARC specific additions to the CPU Table
525 */
526
527/* There are no CPU specific additions to the CPU Table for this port. */
528
529/*
530 *  This variable is contains the initialize context for the FP unit.
531 *  It is filled in by _CPU_Initialize and copied into the task's FP
532 *  context area during _CPU_Context_Initialize.
533 */
534
535SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
536
537/*
538 *  This stack is allocated by the Interrupt Manager and the switch
539 *  is performed in _ISR_Handler.  These variables contain pointers
540 *  to the lowest and highest addresses in the chunk of memory allocated
541 *  for the interrupt stack.  Since it is unknown whether the stack
542 *  grows up or down (in general), this give the CPU dependent
543 *  code the option of picking the version it wants to use.  Thus
544 *  both must be present if either is.
545 *
546 *  The SPARC supports a software based interrupt stack and these
547 *  are required.
548 */
549
550SCORE_EXTERN void *_CPU_Interrupt_stack_low;
551SCORE_EXTERN void *_CPU_Interrupt_stack_high;
552
553/*
554 *  The following type defines an entry in the SPARC's trap table.
555 *
556 *  NOTE: The instructions chosen are RTEMS dependent although one is
557 *        obligated to use two of the four instructions to perform a
558 *        long jump.  The other instructions load one register with the
559 *        trap type (a.k.a. vector) and another with the psr.
560 */
561 
562typedef struct {
563  unsigned32   mov_psr_l0;                     /* mov   %psr, %l0           */
564  unsigned32   sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
565  unsigned32   jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
566  unsigned32   mov_vector_l3;                  /* mov   _vector, %l3        */
567} CPU_Trap_table_entry;
568 
569/*
570 *  This is the set of opcodes for the instructions loaded into a trap
571 *  table entry.  The routine which installs a handler is responsible
572 *  for filling in the fields for the _handler address and the _vector
573 *  trap type.
574 *
575 *  The constants following this structure are masks for the fields which
576 *  must be filled in when the handler is installed.
577 */
578 
579extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
580
581/*
582 *  The size of the floating point context area. 
583 */
584
585#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
586
587#endif
588
589/*
590 *  Amount of extra stack (above minimum stack size) required by
591 *  MPCI receive server thread.  Remember that in a multiprocessor
592 *  system this thread must exist and be able to process all directives.
593 */
594
595#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
596
597/*
598 *  This defines the number of entries in the ISR_Vector_table managed
599 *  by the executive.
600 *
601 *  On the SPARC, there are really only 256 vectors.  However, the executive
602 *  has no easy, fast, reliable way to determine which traps are synchronous
603 *  and which are asynchronous.  By default, synchronous traps return to the
604 *  instruction which caused the interrupt.  So if you install a software
605 *  trap handler as an executive interrupt handler (which is desirable since
606 *  RTEMS takes care of window and register issues), then the executive needs
607 *  to know that the return address is to the trap rather than the instruction
608 *  following the trap.
609 *
610 *  So vectors 0 through 255 are treated as regular asynchronous traps which
611 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
612 *  by the executive to be synchronous and to require that the return address
613 *  be fudged.
614 *
615 *  If you use this mechanism to install a trap handler which must reexecute
616 *  the instruction which caused the trap, then it should be installed as
617 *  an asynchronous trap.  This will avoid the executive changing the return
618 *  address.
619 */
620
621#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
622#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
623
624#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
625#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
626#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
627
628#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
629
630/*
631 *  This is defined if the port has a special way to report the ISR nesting
632 *  level.  Most ports maintain the variable _ISR_Nest_level.
633 */
634
635#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
636
637/*
638 *  Should be large enough to run all tests.  This insures
639 *  that a "reasonable" small application should not have any problems.
640 *
641 *  This appears to be a fairly generous number for the SPARC since
642 *  represents a call depth of about 20 routines based on the minimum
643 *  stack frame.
644 */
645
646#define CPU_STACK_MINIMUM_SIZE  (1024*4)
647
648/*
649 *  CPU's worst alignment requirement for data types on a byte boundary.  This
650 *  alignment does not take into account the requirements for the stack.
651 *
652 *  On the SPARC, this is required for double word loads and stores.
653 */
654
655#define CPU_ALIGNMENT      8
656
657/*
658 *  This number corresponds to the byte alignment requirement for the
659 *  heap handler.  This alignment requirement may be stricter than that
660 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
661 *  common for the heap to follow the same alignment requirement as
662 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
663 *  then this should be set to CPU_ALIGNMENT.
664 *
665 *  NOTE:  This does not have to be a power of 2.  It does have to
666 *         be greater or equal to than CPU_ALIGNMENT.
667 */
668
669#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
670
671/*
672 *  This number corresponds to the byte alignment requirement for memory
673 *  buffers allocated by the partition manager.  This alignment requirement
674 *  may be stricter than that for the data types alignment specified by
675 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
676 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
677 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
678 *
679 *  NOTE:  This does not have to be a power of 2.  It does have to
680 *         be greater or equal to than CPU_ALIGNMENT.
681 */
682
683#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
684
685/*
686 *  This number corresponds to the byte alignment requirement for the
687 *  stack.  This alignment requirement may be stricter than that for the
688 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
689 *  is strict enough for the stack, then this should be set to 0.
690 *
691 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
692 *
693 *  The alignment restrictions for the SPARC are not that strict but this
694 *  should unsure that the stack is always sufficiently alignment that the
695 *  window overflow, underflow, and flush routines can use double word loads
696 *  and stores.
697 */
698
699#define CPU_STACK_ALIGNMENT        16
700
701#ifndef ASM
702
703extern unsigned int sparc_disable_interrupts();
704extern void sparc_enable_interrupts();
705
706/*
707 *  ISR handler macros
708 */
709
710/*
711 *  Support routine to initialize the RTEMS vector table after it is allocated.
712 */
713
714#define _CPU_Initialize_vectors()
715
716/*
717 *  Disable all interrupts for a critical section.  The previous
718 *  level is returned in _level.
719 */
720
721#define _CPU_ISR_Disable( _level ) \
722  (_level) = sparc_disable_interrupts()
723 
724/*
725 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
726 *  This indicates the end of a critical section.  The parameter
727 *  _level is not modified.
728 */
729
730#define _CPU_ISR_Enable( _level ) \
731  sparc_enable_interrupts( _level )
732/*
733 *  This temporarily restores the interrupt to _level before immediately
734 *  disabling them again.  This is used to divide long critical
735 *  sections into two or more parts.  The parameter _level is not
736 *  modified.
737 */
738
739#define _CPU_ISR_Flash( _level ) \
740  sparc_flash_interrupts( _level )
741 
742/*
743 *  Map interrupt level in task mode onto the hardware that the CPU
744 *  actually provides.  Currently, interrupt levels which do not
745 *  map onto the CPU in a straight fashion are undefined. 
746 */
747
748#define _CPU_ISR_Set_level( _newlevel ) \
749   sparc_enable_interrupts( _newlevel << 8)
750 
751unsigned32 _CPU_ISR_Get_level( void );
752 
753/* end of ISR handler macros */
754
755/* Context handler macros */
756
757/*
758 *  Initialize the context to a state suitable for starting a
759 *  task after a context restore operation.  Generally, this
760 *  involves:
761 *
762 *     - setting a starting address
763 *     - preparing the stack
764 *     - preparing the stack and frame pointers
765 *     - setting the proper interrupt level in the context
766 *     - initializing the floating point context
767 *
768 *  NOTE:  Implemented as a subroutine for the SPARC port.
769 */
770
771void _CPU_Context_Initialize(
772  Context_Control  *the_context,
773  unsigned32       *stack_base,
774  unsigned32        size,
775  unsigned32        new_level,
776  void             *entry_point,
777  boolean           is_fp
778);
779
780/*
781 *  This routine is responsible for somehow restarting the currently
782 *  executing task. 
783 *
784 *  On the SPARC, this is is relatively painless but requires a small
785 *  amount of wrapper code before using the regular restore code in
786 *  of the context switch.
787 */
788
789#define _CPU_Context_Restart_self( _the_context ) \
790   _CPU_Context_restore( (_the_context) );
791
792/*
793 *  The FP context area for the SPARC is a simple structure and nothing
794 *  special is required to find the "starting load point"
795 */
796
797#define _CPU_Context_Fp_start( _base, _offset ) \
798   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
799
800/*
801 *  This routine initializes the FP context area passed to it to.
802 *
803 *  The SPARC allows us to use the simple initialization model
804 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
805 *  at CPU initialization and it is simply copied into the destination
806 *  context.
807 */
808
809#define _CPU_Context_Initialize_fp( _destination ) \
810  do { \
811   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
812  } while (0)
813
814/* end of Context handler macros */
815
816/* Fatal Error manager macros */
817
818/*
819 *  This routine copies _error into a known place -- typically a stack
820 *  location or a register, optionally disables interrupts, and
821 *  halts/stops the CPU.
822 */
823
824#define _CPU_Fatal_halt( _error ) \
825  do { \
826    unsigned32 level; \
827    \
828    level = sparc_disable_interrupts(); \
829    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
830    while (1); /* loop forever */ \
831  } while (0)
832
833/* end of Fatal Error manager macros */
834
835/* Bitfield handler macros */
836
837/*
838 *  The SPARC port uses the generic C algorithm for bitfield scan if the
839 *  CPU model does not have a scan instruction.
840 */
841
842#if ( SPARC_HAS_BITSCAN == 0 )
843#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
844#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
845#else
846#error "scan instruction not currently supported by RTEMS!!"
847#endif
848
849/* end of Bitfield handler macros */
850
851/* Priority handler handler macros */
852
853/*
854 *  The SPARC port uses the generic C algorithm for bitfield scan if the
855 *  CPU model does not have a scan instruction.
856 */
857
858#if ( SPARC_HAS_BITSCAN == 1 )
859#error "scan instruction not currently supported by RTEMS!!"
860#endif
861
862/* end of Priority handler macros */
863
864/* functions */
865
866/*
867 *  _CPU_Initialize
868 *
869 *  This routine performs CPU dependent initialization.
870 */
871
872void _CPU_Initialize(
873  rtems_cpu_table  *cpu_table,
874  void            (*thread_dispatch)
875);
876
877/*
878 *  _CPU_ISR_install_raw_handler
879 *
880 *  This routine installs new_handler to be directly called from the trap
881 *  table.
882 */
883 
884void _CPU_ISR_install_raw_handler(
885  unsigned32  vector,
886  proc_ptr    new_handler,
887  proc_ptr   *old_handler
888);
889
890/*
891 *  _CPU_ISR_install_vector
892 *
893 *  This routine installs an interrupt vector.
894 */
895
896void _CPU_ISR_install_vector(
897  unsigned32  vector,
898  proc_ptr    new_handler,
899  proc_ptr   *old_handler
900);
901
902#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
903 
904/*
905 *  _CPU_Thread_Idle_body
906 *
907 *  Some SPARC implementations have low power, sleep, or idle modes.  This
908 *  tries to take advantage of those models.
909 */
910 
911void _CPU_Thread_Idle_body( void );
912 
913#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
914
915/*
916 *  _CPU_Context_switch
917 *
918 *  This routine switches from the run context to the heir context.
919 */
920
921void _CPU_Context_switch(
922  Context_Control  *run,
923  Context_Control  *heir
924);
925
926/*
927 *  _CPU_Context_restore
928 *
929 *  This routine is generally used only to restart self in an
930 *  efficient manner.
931 */
932
933void _CPU_Context_restore(
934  Context_Control *new_context
935);
936
937/*
938 *  _CPU_Context_save_fp
939 *
940 *  This routine saves the floating point context passed to it.
941 */
942
943void _CPU_Context_save_fp(
944  void **fp_context_ptr
945);
946
947/*
948 *  _CPU_Context_restore_fp
949 *
950 *  This routine restores the floating point context passed to it.
951 */
952
953void _CPU_Context_restore_fp(
954  void **fp_context_ptr
955);
956
957/*
958 *  CPU_swap_u32
959 *
960 *  The following routine swaps the endian format of an unsigned int.
961 *  It must be static because it is referenced indirectly.
962 *
963 *  This version will work on any processor, but if you come across a better
964 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
965 *  entity as shown below is not any more efficient on the SPARC.
966 *
967 *     swap least significant two bytes with 16-bit rotate
968 *     swap upper and lower 16-bits
969 *     swap most significant two bytes with 16-bit rotate
970 *
971 *  It is not obvious how the SPARC can do significantly better than the
972 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
973 *  following code at optimization level four (i.e. -O4).
974 */
975 
976static inline unsigned int CPU_swap_u32(
977  unsigned int value
978)
979{
980  unsigned32 byte1, byte2, byte3, byte4, swapped;
981 
982  byte4 = (value >> 24) & 0xff;
983  byte3 = (value >> 16) & 0xff;
984  byte2 = (value >> 8)  & 0xff;
985  byte1 =  value        & 0xff;
986 
987  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
988  return( swapped );
989}
990
991#define CPU_swap_u16( value ) \
992  (((value&0xff) << 8) | ((value >> 8)&0xff))
993
994#endif ASM
995
996#ifdef __cplusplus
997}
998#endif
999
1000#endif
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