1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This include file contains information pertaining to the port of |
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7 | * the executive to the SPARC processor. |
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8 | * |
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9 | * COPYRIGHT (c) 1989-2006. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_CPU_H |
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20 | #define _RTEMS_SCORE_CPU_H |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif |
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25 | |
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26 | #include <rtems/score/sparc.h> /* pick up machine definitions */ |
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27 | #ifndef ASM |
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28 | #include <rtems/score/types.h> |
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29 | #endif |
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30 | |
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31 | /* conditional compilation parameters */ |
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32 | |
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33 | /* |
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34 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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35 | * |
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36 | * If TRUE, then they are inlined. |
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37 | * If FALSE, then a subroutine call is made. |
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38 | */ |
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39 | |
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40 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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41 | |
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42 | /* |
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43 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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44 | * be unrolled one time? In unrolled each iteration of the loop examines |
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45 | * two "nodes" on the chain being searched. Otherwise, only one node |
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46 | * is examined per iteration. |
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47 | * |
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48 | * If TRUE, then the loops are unrolled. |
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49 | * If FALSE, then the loops are not unrolled. |
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50 | * |
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51 | * This parameter could go either way on the SPARC. The interrupt flash |
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52 | * code is relatively lengthy given the requirements for nops following |
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53 | * writes to the psr. But if the clock speed were high enough, this would |
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54 | * not represent a great deal of time. |
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55 | */ |
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56 | |
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57 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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58 | |
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59 | /* |
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60 | * Does the executive manage a dedicated interrupt stack in software? |
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61 | * |
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62 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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63 | * If FALSE, nothing is done. |
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64 | * |
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65 | * The SPARC does not have a dedicated HW interrupt stack and one has |
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66 | * been implemented in SW. |
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67 | */ |
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68 | |
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69 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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70 | |
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71 | /* |
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72 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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73 | * |
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74 | * If TRUE, then it must be installed during initialization. |
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75 | * If FALSE, then no installation is performed. |
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76 | * |
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77 | * The SPARC does not have a dedicated HW interrupt stack. |
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78 | */ |
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79 | |
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80 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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81 | |
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82 | /* |
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83 | * Do we allocate a dedicated interrupt stack in the Interrupt Manager? |
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84 | * |
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85 | * If TRUE, then the memory is allocated during initialization. |
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86 | * If FALSE, then the memory is allocated during initialization. |
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87 | */ |
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88 | |
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89 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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90 | |
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91 | /* |
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92 | * Does the RTEMS invoke the user's ISR with the vector number and |
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93 | * a pointer to the saved interrupt frame (1) or just the vector |
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94 | * number (0)? |
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95 | */ |
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96 | |
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97 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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98 | |
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99 | /* |
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100 | * Does the CPU have hardware floating point? |
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101 | * |
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102 | * If TRUE, then the FLOATING_POINT task attribute is supported. |
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103 | * If FALSE, then the FLOATING_POINT task attribute is ignored. |
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104 | */ |
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105 | |
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106 | #if ( SPARC_HAS_FPU == 1 ) |
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107 | #define CPU_HARDWARE_FP TRUE |
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108 | #else |
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109 | #define CPU_HARDWARE_FP FALSE |
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110 | #endif |
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111 | #define CPU_SOFTWARE_FP FALSE |
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112 | |
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113 | /* |
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114 | * Are all tasks FLOATING_POINT tasks implicitly? |
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115 | * |
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116 | * If TRUE, then the FLOATING_POINT task attribute is assumed. |
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117 | * If FALSE, then the FLOATING_POINT task attribute is followed. |
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118 | */ |
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119 | |
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120 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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121 | |
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122 | /* |
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123 | * Should the IDLE task have a floating point context? |
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124 | * |
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125 | * If TRUE, then the IDLE task is created as a FLOATING_POINT task |
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126 | * and it has a floating point context which is switched in and out. |
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127 | * If FALSE, then the IDLE task does not have a floating point context. |
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128 | */ |
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129 | |
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130 | #define CPU_IDLE_TASK_IS_FP FALSE |
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131 | |
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132 | /* |
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133 | * Should the saving of the floating point registers be deferred |
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134 | * until a context switch is made to another different floating point |
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135 | * task? |
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136 | * |
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137 | * If TRUE, then the floating point context will not be stored until |
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138 | * necessary. It will remain in the floating point registers and not |
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139 | * disturned until another floating point task is switched to. |
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140 | * |
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141 | * If FALSE, then the floating point context is saved when a floating |
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142 | * point task is switched out and restored when the next floating point |
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143 | * task is restored. The state of the floating point registers between |
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144 | * those two operations is not specified. |
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145 | */ |
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146 | |
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147 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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148 | |
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149 | /* |
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150 | * Does this port provide a CPU dependent IDLE task implementation? |
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151 | * |
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152 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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153 | * must be provided and is the default IDLE thread body instead of |
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154 | * _CPU_Thread_Idle_body. |
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155 | * |
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156 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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157 | * not provide one. |
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158 | */ |
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159 | |
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160 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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161 | |
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162 | /* |
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163 | * Does the stack grow up (toward higher addresses) or down |
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164 | * (toward lower addresses)? |
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165 | * |
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166 | * If TRUE, then the grows upward. |
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167 | * If FALSE, then the grows toward smaller addresses. |
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168 | * |
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169 | * The stack grows to lower addresses on the SPARC. |
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170 | */ |
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171 | |
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172 | #define CPU_STACK_GROWS_UP FALSE |
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173 | |
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174 | /* |
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175 | * The following is the variable attribute used to force alignment |
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176 | * of critical data structures. On some processors it may make |
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177 | * sense to have these aligned on tighter boundaries than |
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178 | * the minimum requirements of the compiler in order to have as |
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179 | * much of the critical data area as possible in a cache line. |
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180 | * |
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181 | * The SPARC does not appear to have particularly strict alignment |
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182 | * requirements. This value was chosen to take advantages of caches. |
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183 | */ |
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184 | |
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185 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) |
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186 | |
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187 | /* |
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188 | * Define what is required to specify how the network to host conversion |
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189 | * routines are handled. |
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190 | */ |
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191 | |
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192 | #define CPU_BIG_ENDIAN TRUE |
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193 | #define CPU_LITTLE_ENDIAN FALSE |
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194 | |
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195 | /* |
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196 | * The following defines the number of bits actually used in the |
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197 | * interrupt field of the task mode. How those bits map to the |
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198 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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199 | * |
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200 | * The SPARC has 16 interrupt levels in the PIL field of the PSR. |
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201 | */ |
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202 | |
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203 | #define CPU_MODES_INTERRUPT_MASK 0x0000000F |
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204 | |
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205 | /* |
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206 | * This structure represents the organization of the minimum stack frame |
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207 | * for the SPARC. More framing information is required in certain situaions |
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208 | * such as when there are a large number of out parameters or when the callee |
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209 | * must save floating point registers. |
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210 | */ |
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211 | |
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212 | #ifndef ASM |
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213 | |
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214 | typedef struct { |
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215 | uint32_t l0; |
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216 | uint32_t l1; |
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217 | uint32_t l2; |
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218 | uint32_t l3; |
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219 | uint32_t l4; |
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220 | uint32_t l5; |
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221 | uint32_t l6; |
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222 | uint32_t l7; |
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223 | uint32_t i0; |
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224 | uint32_t i1; |
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225 | uint32_t i2; |
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226 | uint32_t i3; |
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227 | uint32_t i4; |
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228 | uint32_t i5; |
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229 | uint32_t i6_fp; |
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230 | uint32_t i7; |
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231 | void *structure_return_address; |
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232 | /* |
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233 | * The following are for the callee to save the register arguments in |
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234 | * should this be necessary. |
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235 | */ |
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236 | uint32_t saved_arg0; |
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237 | uint32_t saved_arg1; |
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238 | uint32_t saved_arg2; |
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239 | uint32_t saved_arg3; |
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240 | uint32_t saved_arg4; |
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241 | uint32_t saved_arg5; |
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242 | uint32_t pad0; |
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243 | } CPU_Minimum_stack_frame; |
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244 | |
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245 | #endif /* ASM */ |
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246 | |
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247 | #define CPU_STACK_FRAME_L0_OFFSET 0x00 |
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248 | #define CPU_STACK_FRAME_L1_OFFSET 0x04 |
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249 | #define CPU_STACK_FRAME_L2_OFFSET 0x08 |
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250 | #define CPU_STACK_FRAME_L3_OFFSET 0x0c |
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251 | #define CPU_STACK_FRAME_L4_OFFSET 0x10 |
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252 | #define CPU_STACK_FRAME_L5_OFFSET 0x14 |
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253 | #define CPU_STACK_FRAME_L6_OFFSET 0x18 |
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254 | #define CPU_STACK_FRAME_L7_OFFSET 0x1c |
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255 | #define CPU_STACK_FRAME_I0_OFFSET 0x20 |
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256 | #define CPU_STACK_FRAME_I1_OFFSET 0x24 |
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257 | #define CPU_STACK_FRAME_I2_OFFSET 0x28 |
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258 | #define CPU_STACK_FRAME_I3_OFFSET 0x2c |
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259 | #define CPU_STACK_FRAME_I4_OFFSET 0x30 |
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260 | #define CPU_STACK_FRAME_I5_OFFSET 0x34 |
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261 | #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 |
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262 | #define CPU_STACK_FRAME_I7_OFFSET 0x3c |
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263 | #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 |
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264 | #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 |
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265 | #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 |
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266 | #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c |
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267 | #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 |
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268 | #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 |
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269 | #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 |
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270 | #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c |
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271 | |
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272 | #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 |
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273 | |
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274 | /* |
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275 | * Contexts |
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276 | * |
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277 | * Generally there are 2 types of context to save. |
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278 | * 1. Interrupt registers to save |
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279 | * 2. Task level registers to save |
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280 | * |
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281 | * This means we have the following 3 context items: |
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282 | * 1. task level context stuff:: Context_Control |
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283 | * 2. floating point task stuff:: Context_Control_fp |
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284 | * 3. special interrupt level context :: Context_Control_interrupt |
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285 | * |
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286 | * On the SPARC, we are relatively conservative in that we save most |
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287 | * of the CPU state in the context area. The ET (enable trap) bit and |
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288 | * the CWP (current window pointer) fields of the PSR are considered |
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289 | * system wide resources and are not maintained on a per-thread basis. |
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290 | */ |
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291 | |
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292 | #ifndef ASM |
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293 | |
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294 | typedef struct { |
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295 | /* |
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296 | * Using a double g0_g1 will put everything in this structure on a |
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297 | * double word boundary which allows us to use double word loads |
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298 | * and stores safely in the context switch. |
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299 | */ |
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300 | double g0_g1; |
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301 | uint32_t g2; |
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302 | uint32_t g3; |
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303 | uint32_t g4; |
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304 | uint32_t g5; |
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305 | uint32_t g6; |
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306 | uint32_t g7; |
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307 | |
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308 | uint32_t l0; |
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309 | uint32_t l1; |
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310 | uint32_t l2; |
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311 | uint32_t l3; |
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312 | uint32_t l4; |
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313 | uint32_t l5; |
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314 | uint32_t l6; |
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315 | uint32_t l7; |
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316 | |
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317 | uint32_t i0; |
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318 | uint32_t i1; |
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319 | uint32_t i2; |
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320 | uint32_t i3; |
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321 | uint32_t i4; |
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322 | uint32_t i5; |
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323 | uint32_t i6_fp; |
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324 | uint32_t i7; |
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325 | |
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326 | uint32_t o0; |
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327 | uint32_t o1; |
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328 | uint32_t o2; |
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329 | uint32_t o3; |
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330 | uint32_t o4; |
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331 | uint32_t o5; |
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332 | uint32_t o6_sp; |
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333 | uint32_t o7; |
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334 | |
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335 | uint32_t psr; |
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336 | } Context_Control; |
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337 | |
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338 | #endif /* ASM */ |
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339 | |
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340 | /* |
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341 | * Offsets of fields with Context_Control for assembly routines. |
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342 | */ |
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343 | |
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344 | #define G0_OFFSET 0x00 |
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345 | #define G1_OFFSET 0x04 |
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346 | #define G2_OFFSET 0x08 |
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347 | #define G3_OFFSET 0x0C |
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348 | #define G4_OFFSET 0x10 |
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349 | #define G5_OFFSET 0x14 |
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350 | #define G6_OFFSET 0x18 |
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351 | #define G7_OFFSET 0x1C |
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352 | |
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353 | #define L0_OFFSET 0x20 |
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354 | #define L1_OFFSET 0x24 |
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355 | #define L2_OFFSET 0x28 |
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356 | #define L3_OFFSET 0x2C |
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357 | #define L4_OFFSET 0x30 |
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358 | #define L5_OFFSET 0x34 |
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359 | #define L6_OFFSET 0x38 |
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360 | #define L7_OFFSET 0x3C |
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361 | |
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362 | #define I0_OFFSET 0x40 |
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363 | #define I1_OFFSET 0x44 |
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364 | #define I2_OFFSET 0x48 |
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365 | #define I3_OFFSET 0x4C |
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366 | #define I4_OFFSET 0x50 |
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367 | #define I5_OFFSET 0x54 |
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368 | #define I6_FP_OFFSET 0x58 |
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369 | #define I7_OFFSET 0x5C |
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370 | |
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371 | #define O0_OFFSET 0x60 |
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372 | #define O1_OFFSET 0x64 |
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373 | #define O2_OFFSET 0x68 |
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374 | #define O3_OFFSET 0x6C |
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375 | #define O4_OFFSET 0x70 |
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376 | #define O5_OFFSET 0x74 |
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377 | #define O6_SP_OFFSET 0x78 |
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378 | #define O7_OFFSET 0x7C |
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379 | |
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380 | #define PSR_OFFSET 0x80 |
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381 | |
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382 | #define CONTEXT_CONTROL_SIZE 0x84 |
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383 | |
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384 | /* |
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385 | * The floating point context area. |
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386 | */ |
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387 | |
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388 | #ifndef ASM |
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389 | |
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390 | typedef struct { |
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391 | double f0_f1; |
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392 | double f2_f3; |
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393 | double f4_f5; |
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394 | double f6_f7; |
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395 | double f8_f9; |
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396 | double f10_f11; |
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397 | double f12_f13; |
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398 | double f14_f15; |
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399 | double f16_f17; |
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400 | double f18_f19; |
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401 | double f20_f21; |
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402 | double f22_f23; |
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403 | double f24_f25; |
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404 | double f26_f27; |
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405 | double f28_f29; |
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406 | double f30_f31; |
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407 | uint32_t fsr; |
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408 | } Context_Control_fp; |
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409 | |
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410 | #endif /* ASM */ |
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411 | |
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412 | /* |
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413 | * Offsets of fields with Context_Control_fp for assembly routines. |
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414 | */ |
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415 | |
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416 | #define FO_F1_OFFSET 0x00 |
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417 | #define F2_F3_OFFSET 0x08 |
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418 | #define F4_F5_OFFSET 0x10 |
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419 | #define F6_F7_OFFSET 0x18 |
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420 | #define F8_F9_OFFSET 0x20 |
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421 | #define F1O_F11_OFFSET 0x28 |
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422 | #define F12_F13_OFFSET 0x30 |
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423 | #define F14_F15_OFFSET 0x38 |
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424 | #define F16_F17_OFFSET 0x40 |
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425 | #define F18_F19_OFFSET 0x48 |
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426 | #define F2O_F21_OFFSET 0x50 |
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427 | #define F22_F23_OFFSET 0x58 |
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428 | #define F24_F25_OFFSET 0x60 |
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429 | #define F26_F27_OFFSET 0x68 |
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430 | #define F28_F29_OFFSET 0x70 |
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431 | #define F3O_F31_OFFSET 0x78 |
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432 | #define FSR_OFFSET 0x80 |
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433 | |
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434 | #define CONTEXT_CONTROL_FP_SIZE 0x84 |
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435 | |
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436 | #ifndef ASM |
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437 | |
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438 | /* |
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439 | * Context saved on stack for an interrupt. |
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440 | * |
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441 | * NOTE: The PSR, PC, and NPC are only saved in this structure for the |
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442 | * benefit of the user's handler. |
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443 | */ |
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444 | |
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445 | typedef struct { |
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446 | CPU_Minimum_stack_frame Stack_frame; |
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447 | uint32_t psr; |
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448 | uint32_t pc; |
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449 | uint32_t npc; |
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450 | uint32_t g1; |
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451 | uint32_t g2; |
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452 | uint32_t g3; |
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453 | uint32_t g4; |
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454 | uint32_t g5; |
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455 | uint32_t g6; |
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456 | uint32_t g7; |
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457 | uint32_t i0; |
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458 | uint32_t i1; |
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459 | uint32_t i2; |
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460 | uint32_t i3; |
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461 | uint32_t i4; |
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462 | uint32_t i5; |
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463 | uint32_t i6_fp; |
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464 | uint32_t i7; |
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465 | uint32_t y; |
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466 | uint32_t tpc; |
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467 | } CPU_Interrupt_frame; |
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468 | |
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469 | #endif /* ASM */ |
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470 | |
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471 | /* |
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472 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
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473 | */ |
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474 | |
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475 | #define ISF_STACK_FRAME_OFFSET 0x00 |
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476 | #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 |
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477 | #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 |
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478 | #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 |
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479 | #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c |
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480 | #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 |
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481 | #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 |
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482 | #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 |
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483 | #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c |
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484 | #define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 |
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485 | #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 |
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486 | #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 |
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487 | #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c |
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488 | #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 |
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489 | #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 |
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490 | #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 |
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491 | #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c |
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492 | #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 |
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493 | #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 |
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494 | #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 |
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495 | #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c |
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496 | |
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497 | #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 |
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498 | #ifndef ASM |
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499 | |
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500 | /* |
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501 | * The following table contains the information required to configure |
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502 | * the processor specific parameters. |
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503 | */ |
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504 | |
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505 | typedef struct { |
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506 | void (*pretasking_hook)( void ); |
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507 | void (*predriver_hook)( void ); |
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508 | void (*postdriver_hook)( void ); |
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509 | void (*idle_task)( void ); |
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510 | boolean do_zero_of_workspace; |
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511 | uint32_t idle_task_stack_size; |
---|
512 | uint32_t interrupt_stack_size; |
---|
513 | uint32_t extra_mpci_receive_server_stack; |
---|
514 | void * (*stack_allocate_hook)( uint32_t ); |
---|
515 | void (*stack_free_hook)( void* ); |
---|
516 | /* end of fields required on all CPUs */ |
---|
517 | |
---|
518 | } rtems_cpu_table; |
---|
519 | |
---|
520 | /* |
---|
521 | * Macros to access required entires in the CPU Table are in |
---|
522 | * the file rtems/system.h. |
---|
523 | */ |
---|
524 | |
---|
525 | /* |
---|
526 | * Macros to access SPARC specific additions to the CPU Table |
---|
527 | */ |
---|
528 | |
---|
529 | /* There are no CPU specific additions to the CPU Table for this port. */ |
---|
530 | |
---|
531 | /* |
---|
532 | * This variable is contains the initialize context for the FP unit. |
---|
533 | * It is filled in by _CPU_Initialize and copied into the task's FP |
---|
534 | * context area during _CPU_Context_Initialize. |
---|
535 | */ |
---|
536 | |
---|
537 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; |
---|
538 | |
---|
539 | /* |
---|
540 | * This stack is allocated by the Interrupt Manager and the switch |
---|
541 | * is performed in _ISR_Handler. These variables contain pointers |
---|
542 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
543 | * for the interrupt stack. Since it is unknown whether the stack |
---|
544 | * grows up or down (in general), this give the CPU dependent |
---|
545 | * code the option of picking the version it wants to use. Thus |
---|
546 | * both must be present if either is. |
---|
547 | * |
---|
548 | * The SPARC supports a software based interrupt stack and these |
---|
549 | * are required. |
---|
550 | */ |
---|
551 | |
---|
552 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
553 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
554 | |
---|
555 | /* |
---|
556 | * The following type defines an entry in the SPARC's trap table. |
---|
557 | * |
---|
558 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
559 | * obligated to use two of the four instructions to perform a |
---|
560 | * long jump. The other instructions load one register with the |
---|
561 | * trap type (a.k.a. vector) and another with the psr. |
---|
562 | */ |
---|
563 | |
---|
564 | typedef struct { |
---|
565 | uint32_t mov_psr_l0; /* mov %psr, %l0 */ |
---|
566 | uint32_t sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ |
---|
567 | uint32_t jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ |
---|
568 | uint32_t mov_vector_l3; /* mov _vector, %l3 */ |
---|
569 | } CPU_Trap_table_entry; |
---|
570 | |
---|
571 | /* |
---|
572 | * This is the set of opcodes for the instructions loaded into a trap |
---|
573 | * table entry. The routine which installs a handler is responsible |
---|
574 | * for filling in the fields for the _handler address and the _vector |
---|
575 | * trap type. |
---|
576 | * |
---|
577 | * The constants following this structure are masks for the fields which |
---|
578 | * must be filled in when the handler is installed. |
---|
579 | */ |
---|
580 | |
---|
581 | extern const CPU_Trap_table_entry _CPU_Trap_slot_template; |
---|
582 | |
---|
583 | /* |
---|
584 | * The size of the floating point context area. |
---|
585 | */ |
---|
586 | |
---|
587 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
588 | |
---|
589 | #endif |
---|
590 | |
---|
591 | /* |
---|
592 | * Amount of extra stack (above minimum stack size) required by |
---|
593 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
594 | * system this thread must exist and be able to process all directives. |
---|
595 | */ |
---|
596 | |
---|
597 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
---|
598 | |
---|
599 | /* |
---|
600 | * This defines the number of entries in the ISR_Vector_table managed |
---|
601 | * by the executive. |
---|
602 | * |
---|
603 | * On the SPARC, there are really only 256 vectors. However, the executive |
---|
604 | * has no easy, fast, reliable way to determine which traps are synchronous |
---|
605 | * and which are asynchronous. By default, synchronous traps return to the |
---|
606 | * instruction which caused the interrupt. So if you install a software |
---|
607 | * trap handler as an executive interrupt handler (which is desirable since |
---|
608 | * RTEMS takes care of window and register issues), then the executive needs |
---|
609 | * to know that the return address is to the trap rather than the instruction |
---|
610 | * following the trap. |
---|
611 | * |
---|
612 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
---|
613 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
---|
614 | * by the executive to be synchronous and to require that the return address |
---|
615 | * be fudged. |
---|
616 | * |
---|
617 | * If you use this mechanism to install a trap handler which must reexecute |
---|
618 | * the instruction which caused the trap, then it should be installed as |
---|
619 | * an asynchronous trap. This will avoid the executive changing the return |
---|
620 | * address. |
---|
621 | */ |
---|
622 | |
---|
623 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
624 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 |
---|
625 | |
---|
626 | #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
---|
627 | #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
---|
628 | #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) |
---|
629 | |
---|
630 | #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) |
---|
631 | |
---|
632 | /* |
---|
633 | * This is defined if the port has a special way to report the ISR nesting |
---|
634 | * level. Most ports maintain the variable _ISR_Nest_level. |
---|
635 | */ |
---|
636 | |
---|
637 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
638 | |
---|
639 | /* |
---|
640 | * Should be large enough to run all tests. This ensures |
---|
641 | * that a "reasonable" small application should not have any problems. |
---|
642 | * |
---|
643 | * This appears to be a fairly generous number for the SPARC since |
---|
644 | * represents a call depth of about 20 routines based on the minimum |
---|
645 | * stack frame. |
---|
646 | */ |
---|
647 | |
---|
648 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
649 | |
---|
650 | /* |
---|
651 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
652 | * alignment does not take into account the requirements for the stack. |
---|
653 | * |
---|
654 | * On the SPARC, this is required for double word loads and stores. |
---|
655 | */ |
---|
656 | |
---|
657 | #define CPU_ALIGNMENT 8 |
---|
658 | |
---|
659 | /* |
---|
660 | * This number corresponds to the byte alignment requirement for the |
---|
661 | * heap handler. This alignment requirement may be stricter than that |
---|
662 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
663 | * common for the heap to follow the same alignment requirement as |
---|
664 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
665 | * then this should be set to CPU_ALIGNMENT. |
---|
666 | * |
---|
667 | * NOTE: This does not have to be a power of 2. It does have to |
---|
668 | * be greater or equal to than CPU_ALIGNMENT. |
---|
669 | */ |
---|
670 | |
---|
671 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
672 | |
---|
673 | /* |
---|
674 | * This number corresponds to the byte alignment requirement for memory |
---|
675 | * buffers allocated by the partition manager. This alignment requirement |
---|
676 | * may be stricter than that for the data types alignment specified by |
---|
677 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
678 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
679 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
680 | * |
---|
681 | * NOTE: This does not have to be a power of 2. It does have to |
---|
682 | * be greater or equal to than CPU_ALIGNMENT. |
---|
683 | */ |
---|
684 | |
---|
685 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
686 | |
---|
687 | /* |
---|
688 | * This number corresponds to the byte alignment requirement for the |
---|
689 | * stack. This alignment requirement may be stricter than that for the |
---|
690 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
691 | * is strict enough for the stack, then this should be set to 0. |
---|
692 | * |
---|
693 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
694 | * |
---|
695 | * The alignment restrictions for the SPARC are not that strict but this |
---|
696 | * should unsure that the stack is always sufficiently alignment that the |
---|
697 | * window overflow, underflow, and flush routines can use double word loads |
---|
698 | * and stores. |
---|
699 | */ |
---|
700 | |
---|
701 | #define CPU_STACK_ALIGNMENT 16 |
---|
702 | |
---|
703 | #ifndef ASM |
---|
704 | |
---|
705 | extern unsigned int sparc_disable_interrupts(); |
---|
706 | extern void sparc_enable_interrupts(); |
---|
707 | |
---|
708 | /* |
---|
709 | * ISR handler macros |
---|
710 | */ |
---|
711 | |
---|
712 | /* |
---|
713 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
714 | */ |
---|
715 | |
---|
716 | #define _CPU_Initialize_vectors() |
---|
717 | |
---|
718 | /* |
---|
719 | * Disable all interrupts for a critical section. The previous |
---|
720 | * level is returned in _level. |
---|
721 | */ |
---|
722 | |
---|
723 | #define _CPU_ISR_Disable( _level ) \ |
---|
724 | (_level) = sparc_disable_interrupts() |
---|
725 | |
---|
726 | /* |
---|
727 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
728 | * This indicates the end of a critical section. The parameter |
---|
729 | * _level is not modified. |
---|
730 | */ |
---|
731 | |
---|
732 | #define _CPU_ISR_Enable( _level ) \ |
---|
733 | sparc_enable_interrupts( _level ) |
---|
734 | /* |
---|
735 | * This temporarily restores the interrupt to _level before immediately |
---|
736 | * disabling them again. This is used to divide long critical |
---|
737 | * sections into two or more parts. The parameter _level is not |
---|
738 | * modified. |
---|
739 | */ |
---|
740 | |
---|
741 | #define _CPU_ISR_Flash( _level ) \ |
---|
742 | sparc_flash_interrupts( _level ) |
---|
743 | |
---|
744 | /* |
---|
745 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
746 | * actually provides. Currently, interrupt levels which do not |
---|
747 | * map onto the CPU in a straight fashion are undefined. |
---|
748 | */ |
---|
749 | |
---|
750 | #define _CPU_ISR_Set_level( _newlevel ) \ |
---|
751 | sparc_enable_interrupts( _newlevel << 8) |
---|
752 | |
---|
753 | uint32_t _CPU_ISR_Get_level( void ); |
---|
754 | |
---|
755 | /* end of ISR handler macros */ |
---|
756 | |
---|
757 | /* Context handler macros */ |
---|
758 | |
---|
759 | /* |
---|
760 | * Initialize the context to a state suitable for starting a |
---|
761 | * task after a context restore operation. Generally, this |
---|
762 | * involves: |
---|
763 | * |
---|
764 | * - setting a starting address |
---|
765 | * - preparing the stack |
---|
766 | * - preparing the stack and frame pointers |
---|
767 | * - setting the proper interrupt level in the context |
---|
768 | * - initializing the floating point context |
---|
769 | * |
---|
770 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
771 | */ |
---|
772 | |
---|
773 | void _CPU_Context_Initialize( |
---|
774 | Context_Control *the_context, |
---|
775 | uint32_t *stack_base, |
---|
776 | uint32_t size, |
---|
777 | uint32_t new_level, |
---|
778 | void *entry_point, |
---|
779 | boolean is_fp |
---|
780 | ); |
---|
781 | |
---|
782 | /* |
---|
783 | * This routine is responsible for somehow restarting the currently |
---|
784 | * executing task. |
---|
785 | * |
---|
786 | * On the SPARC, this is is relatively painless but requires a small |
---|
787 | * amount of wrapper code before using the regular restore code in |
---|
788 | * of the context switch. |
---|
789 | */ |
---|
790 | |
---|
791 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
792 | _CPU_Context_restore( (_the_context) ); |
---|
793 | |
---|
794 | /* |
---|
795 | * The FP context area for the SPARC is a simple structure and nothing |
---|
796 | * special is required to find the "starting load point" |
---|
797 | */ |
---|
798 | |
---|
799 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
800 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
801 | |
---|
802 | /* |
---|
803 | * This routine initializes the FP context area passed to it to. |
---|
804 | * |
---|
805 | * The SPARC allows us to use the simple initialization model |
---|
806 | * in which an "initial" FP context was saved into _CPU_Null_fp_context |
---|
807 | * at CPU initialization and it is simply copied into the destination |
---|
808 | * context. |
---|
809 | */ |
---|
810 | |
---|
811 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
812 | do { \ |
---|
813 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
814 | } while (0) |
---|
815 | |
---|
816 | /* end of Context handler macros */ |
---|
817 | |
---|
818 | /* Fatal Error manager macros */ |
---|
819 | |
---|
820 | /* |
---|
821 | * This routine copies _error into a known place -- typically a stack |
---|
822 | * location or a register, optionally disables interrupts, and |
---|
823 | * halts/stops the CPU. |
---|
824 | */ |
---|
825 | |
---|
826 | #define _CPU_Fatal_halt( _error ) \ |
---|
827 | do { \ |
---|
828 | uint32_t level; \ |
---|
829 | \ |
---|
830 | level = sparc_disable_interrupts(); \ |
---|
831 | asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ |
---|
832 | while (1); /* loop forever */ \ |
---|
833 | } while (0) |
---|
834 | |
---|
835 | /* end of Fatal Error manager macros */ |
---|
836 | |
---|
837 | /* Bitfield handler macros */ |
---|
838 | |
---|
839 | /* |
---|
840 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
841 | * CPU model does not have a scan instruction. |
---|
842 | */ |
---|
843 | |
---|
844 | #if ( SPARC_HAS_BITSCAN == 0 ) |
---|
845 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
846 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
847 | #else |
---|
848 | #error "scan instruction not currently supported by RTEMS!!" |
---|
849 | #endif |
---|
850 | |
---|
851 | /* end of Bitfield handler macros */ |
---|
852 | |
---|
853 | /* Priority handler handler macros */ |
---|
854 | |
---|
855 | /* |
---|
856 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
857 | * CPU model does not have a scan instruction. |
---|
858 | */ |
---|
859 | |
---|
860 | #if ( SPARC_HAS_BITSCAN == 1 ) |
---|
861 | #error "scan instruction not currently supported by RTEMS!!" |
---|
862 | #endif |
---|
863 | |
---|
864 | /* end of Priority handler macros */ |
---|
865 | |
---|
866 | /* functions */ |
---|
867 | |
---|
868 | /* |
---|
869 | * _CPU_Initialize |
---|
870 | * |
---|
871 | * This routine performs CPU dependent initialization. |
---|
872 | */ |
---|
873 | |
---|
874 | void _CPU_Initialize( |
---|
875 | rtems_cpu_table *cpu_table, |
---|
876 | void (*thread_dispatch) |
---|
877 | ); |
---|
878 | |
---|
879 | /* |
---|
880 | * _CPU_ISR_install_raw_handler |
---|
881 | * |
---|
882 | * This routine installs new_handler to be directly called from the trap |
---|
883 | * table. |
---|
884 | */ |
---|
885 | |
---|
886 | void _CPU_ISR_install_raw_handler( |
---|
887 | uint32_t vector, |
---|
888 | proc_ptr new_handler, |
---|
889 | proc_ptr *old_handler |
---|
890 | ); |
---|
891 | |
---|
892 | /* |
---|
893 | * _CPU_ISR_install_vector |
---|
894 | * |
---|
895 | * This routine installs an interrupt vector. |
---|
896 | */ |
---|
897 | |
---|
898 | void _CPU_ISR_install_vector( |
---|
899 | uint32_t vector, |
---|
900 | proc_ptr new_handler, |
---|
901 | proc_ptr *old_handler |
---|
902 | ); |
---|
903 | |
---|
904 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
---|
905 | |
---|
906 | /* |
---|
907 | * _CPU_Thread_Idle_body |
---|
908 | * |
---|
909 | * Some SPARC implementations have low power, sleep, or idle modes. This |
---|
910 | * tries to take advantage of those models. |
---|
911 | */ |
---|
912 | |
---|
913 | void _CPU_Thread_Idle_body( void ); |
---|
914 | |
---|
915 | #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ |
---|
916 | |
---|
917 | /* |
---|
918 | * _CPU_Context_switch |
---|
919 | * |
---|
920 | * This routine switches from the run context to the heir context. |
---|
921 | */ |
---|
922 | |
---|
923 | void _CPU_Context_switch( |
---|
924 | Context_Control *run, |
---|
925 | Context_Control *heir |
---|
926 | ); |
---|
927 | |
---|
928 | /* |
---|
929 | * _CPU_Context_restore |
---|
930 | * |
---|
931 | * This routine is generally used only to restart self in an |
---|
932 | * efficient manner. |
---|
933 | */ |
---|
934 | |
---|
935 | void _CPU_Context_restore( |
---|
936 | Context_Control *new_context |
---|
937 | ); |
---|
938 | |
---|
939 | /* |
---|
940 | * _CPU_Context_save_fp |
---|
941 | * |
---|
942 | * This routine saves the floating point context passed to it. |
---|
943 | */ |
---|
944 | |
---|
945 | void _CPU_Context_save_fp( |
---|
946 | Context_Control_fp **fp_context_ptr |
---|
947 | ); |
---|
948 | |
---|
949 | /* |
---|
950 | * _CPU_Context_restore_fp |
---|
951 | * |
---|
952 | * This routine restores the floating point context passed to it. |
---|
953 | */ |
---|
954 | |
---|
955 | void _CPU_Context_restore_fp( |
---|
956 | Context_Control_fp **fp_context_ptr |
---|
957 | ); |
---|
958 | |
---|
959 | /* |
---|
960 | * CPU_swap_u32 |
---|
961 | * |
---|
962 | * The following routine swaps the endian format of an unsigned int. |
---|
963 | * It must be static because it is referenced indirectly. |
---|
964 | * |
---|
965 | * This version will work on any processor, but if you come across a better |
---|
966 | * way for the SPARC PLEASE use it. The most common way to swap a 32-bit |
---|
967 | * entity as shown below is not any more efficient on the SPARC. |
---|
968 | * |
---|
969 | * swap least significant two bytes with 16-bit rotate |
---|
970 | * swap upper and lower 16-bits |
---|
971 | * swap most significant two bytes with 16-bit rotate |
---|
972 | * |
---|
973 | * It is not obvious how the SPARC can do significantly better than the |
---|
974 | * generic code. gcc 2.7.0 only generates about 12 instructions for the |
---|
975 | * following code at optimization level four (i.e. -O4). |
---|
976 | */ |
---|
977 | |
---|
978 | static inline uint32_t CPU_swap_u32( |
---|
979 | uint32_t value |
---|
980 | ) |
---|
981 | { |
---|
982 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
983 | |
---|
984 | byte4 = (value >> 24) & 0xff; |
---|
985 | byte3 = (value >> 16) & 0xff; |
---|
986 | byte2 = (value >> 8) & 0xff; |
---|
987 | byte1 = value & 0xff; |
---|
988 | |
---|
989 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
990 | return( swapped ); |
---|
991 | } |
---|
992 | |
---|
993 | #define CPU_swap_u16( value ) \ |
---|
994 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
995 | |
---|
996 | #endif /* ASM */ |
---|
997 | |
---|
998 | #ifdef __cplusplus |
---|
999 | } |
---|
1000 | #endif |
---|
1001 | |
---|
1002 | #endif |
---|