1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief SPARC CPU Department Source |
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5 | * |
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6 | * This include file contains information pertaining to the port of |
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7 | * the executive to the SPARC processor. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * COPYRIGHT (c) 1989-2011. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_CPU_H |
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20 | #define _RTEMS_SCORE_CPU_H |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif |
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25 | |
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26 | #include <rtems/score/types.h> |
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27 | #include <rtems/score/sparc.h> |
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28 | |
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29 | /* conditional compilation parameters */ |
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30 | |
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31 | /** |
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32 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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33 | * |
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34 | * - If TRUE, then they are inlined. |
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35 | * - If FALSE, then a subroutine call is made. |
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36 | * |
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37 | * On this port, it is faster to inline _Thread_Enable_dispatch. |
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38 | */ |
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39 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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40 | |
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41 | /** |
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42 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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43 | * be unrolled one time? In unrolled each iteration of the loop examines |
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44 | * two "nodes" on the chain being searched. Otherwise, only one node |
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45 | * is examined per iteration. |
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46 | * |
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47 | * - If TRUE, then the loops are unrolled. |
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48 | * - If FALSE, then the loops are not unrolled. |
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49 | * |
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50 | * This parameter could go either way on the SPARC. The interrupt flash |
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51 | * code is relatively lengthy given the requirements for nops following |
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52 | * writes to the psr. But if the clock speed were high enough, this would |
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53 | * not represent a great deal of time. |
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54 | */ |
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55 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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56 | |
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57 | /** |
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58 | * Does the executive manage a dedicated interrupt stack in software? |
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59 | * |
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60 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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61 | * If FALSE, nothing is done. |
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62 | * |
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63 | * The SPARC does not have a dedicated HW interrupt stack and one has |
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64 | * been implemented in SW. |
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65 | */ |
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66 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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67 | |
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68 | /** |
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69 | * Does the CPU follow the simple vectored interrupt model? |
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70 | * |
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71 | * - If TRUE, then RTEMS allocates the vector table it internally manages. |
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72 | * - If FALSE, then the BSP is assumed to allocate and manage the vector |
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73 | * table |
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74 | * |
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75 | * THe SPARC is a simple vectored architecture. Usually there is no |
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76 | * PIC and the CPU directly vectors the interrupts. |
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77 | */ |
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78 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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79 | |
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80 | /** |
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81 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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82 | * |
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83 | * - If TRUE, then it must be installed during initialization. |
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84 | * - If FALSE, then no installation is performed. |
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85 | * |
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86 | * The SPARC does not have a dedicated HW interrupt stack. |
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87 | */ |
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88 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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89 | |
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90 | /** |
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91 | * Do we allocate a dedicated interrupt stack in the Interrupt Manager? |
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92 | * |
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93 | * - If TRUE, then the memory is allocated during initialization. |
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94 | * - If FALSE, then the memory is allocated during initialization. |
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95 | * |
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96 | * The SPARC does not have hardware support for switching to a |
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97 | * dedicated interrupt stack. The port includes support for doing this |
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98 | * in software. |
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99 | * |
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100 | */ |
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101 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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102 | |
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103 | /** |
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104 | * Does the RTEMS invoke the user's ISR with the vector number and |
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105 | * a pointer to the saved interrupt frame (1) or just the vector |
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106 | * number (0)? |
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107 | * |
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108 | * The SPARC port does not pass an Interrupt Stack Frame pointer to |
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109 | * interrupt handlers. |
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110 | */ |
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111 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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112 | |
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113 | /** |
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114 | * Does the CPU have hardware floating point? |
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115 | * |
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116 | * - If TRUE, then the FLOATING_POINT task attribute is supported. |
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117 | * - If FALSE, then the FLOATING_POINT task attribute is ignored. |
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118 | * |
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119 | * This is set based upon the multilib settings. |
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120 | */ |
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121 | #if ( SPARC_HAS_FPU == 1 ) |
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122 | #define CPU_HARDWARE_FP TRUE |
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123 | #else |
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124 | #define CPU_HARDWARE_FP FALSE |
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125 | #endif |
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126 | |
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127 | /** |
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128 | * The SPARC GCC port does not have a software floating point library |
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129 | * that requires RTEMS assistance. |
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130 | */ |
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131 | #define CPU_SOFTWARE_FP FALSE |
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132 | |
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133 | /** |
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134 | * Are all tasks FLOATING_POINT tasks implicitly? |
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135 | * |
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136 | * - If TRUE, then the FLOATING_POINT task attribute is assumed. |
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137 | * - If FALSE, then the FLOATING_POINT task attribute is followed. |
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138 | * |
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139 | * The SPARC GCC port does not implicitly use floating point registers. |
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140 | */ |
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141 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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142 | |
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143 | /** |
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144 | * Should the IDLE task have a floating point context? |
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145 | * |
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146 | * - If TRUE, then the IDLE task is created as a FLOATING_POINT task |
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147 | * and it has a floating point context which is switched in and out. |
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148 | * - If FALSE, then the IDLE task does not have a floating point context. |
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149 | * |
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150 | * The IDLE task does not have to be floating point on the SPARC. |
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151 | */ |
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152 | #define CPU_IDLE_TASK_IS_FP FALSE |
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153 | |
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154 | /** |
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155 | * Should the saving of the floating point registers be deferred |
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156 | * until a context switch is made to another different floating point |
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157 | * task? |
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158 | * |
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159 | * - If TRUE, then the floating point context will not be stored until |
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160 | * necessary. It will remain in the floating point registers and not |
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161 | * disturned until another floating point task is switched to. |
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162 | * |
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163 | * - If FALSE, then the floating point context is saved when a floating |
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164 | * point task is switched out and restored when the next floating point |
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165 | * task is restored. The state of the floating point registers between |
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166 | * those two operations is not specified. |
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167 | * |
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168 | * On the SPARC, we can disable the FPU for integer only tasks so |
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169 | * it is safe to defer floating point context switches. |
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170 | */ |
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171 | #if defined(RTEMS_SMP) |
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172 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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173 | #else |
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174 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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175 | #endif |
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176 | |
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177 | /** |
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178 | * Does this port provide a CPU dependent IDLE task implementation? |
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179 | * |
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180 | * - If TRUE, then the routine _CPU_Thread_Idle_body |
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181 | * must be provided and is the default IDLE thread body instead of |
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182 | * _CPU_Thread_Idle_body. |
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183 | * |
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184 | * - If FALSE, then use the generic IDLE thread body if the BSP does |
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185 | * not provide one. |
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186 | * |
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187 | * The SPARC architecture does not have a low power or halt instruction. |
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188 | * It is left to the BSP and/or CPU specific code to provide an IDLE |
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189 | * thread body which is aware of low power modes. |
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190 | */ |
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191 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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192 | |
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193 | /** |
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194 | * Does the stack grow up (toward higher addresses) or down |
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195 | * (toward lower addresses)? |
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196 | * |
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197 | * - If TRUE, then the grows upward. |
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198 | * - If FALSE, then the grows toward smaller addresses. |
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199 | * |
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200 | * The stack grows to lower addresses on the SPARC. |
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201 | */ |
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202 | #define CPU_STACK_GROWS_UP FALSE |
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203 | |
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204 | /** |
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205 | * The following is the variable attribute used to force alignment |
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206 | * of critical data structures. On some processors it may make |
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207 | * sense to have these aligned on tighter boundaries than |
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208 | * the minimum requirements of the compiler in order to have as |
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209 | * much of the critical data area as possible in a cache line. |
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210 | * |
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211 | * The SPARC does not appear to have particularly strict alignment |
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212 | * requirements. This value was chosen to take advantages of caches. |
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213 | */ |
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214 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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215 | |
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216 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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217 | |
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218 | /** |
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219 | * Define what is required to specify how the network to host conversion |
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220 | * routines are handled. |
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221 | * |
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222 | * The SPARC is big endian. |
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223 | */ |
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224 | #define CPU_BIG_ENDIAN TRUE |
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225 | |
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226 | /** |
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227 | * Define what is required to specify how the network to host conversion |
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228 | * routines are handled. |
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229 | * |
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230 | * The SPARC is NOT little endian. |
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231 | */ |
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232 | #define CPU_LITTLE_ENDIAN FALSE |
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233 | |
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234 | /** |
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235 | * The following defines the number of bits actually used in the |
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236 | * interrupt field of the task mode. How those bits map to the |
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237 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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238 | * |
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239 | * The SPARC has 16 interrupt levels in the PIL field of the PSR. |
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240 | */ |
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241 | #define CPU_MODES_INTERRUPT_MASK 0x0000000F |
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242 | |
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243 | #ifndef ASM |
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244 | /** |
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245 | * This structure represents the organization of the minimum stack frame |
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246 | * for the SPARC. More framing information is required in certain situaions |
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247 | * such as when there are a large number of out parameters or when the callee |
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248 | * must save floating point registers. |
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249 | */ |
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250 | typedef struct { |
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251 | /** This is the offset of the l0 register. */ |
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252 | uint32_t l0; |
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253 | /** This is the offset of the l1 register. */ |
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254 | uint32_t l1; |
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255 | /** This is the offset of the l2 register. */ |
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256 | uint32_t l2; |
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257 | /** This is the offset of the l3 register. */ |
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258 | uint32_t l3; |
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259 | /** This is the offset of the l4 register. */ |
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260 | uint32_t l4; |
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261 | /** This is the offset of the l5 register. */ |
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262 | uint32_t l5; |
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263 | /** This is the offset of the l6 register. */ |
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264 | uint32_t l6; |
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265 | /** This is the offset of the l7 register. */ |
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266 | uint32_t l7; |
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267 | /** This is the offset of the l0 register. */ |
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268 | uint32_t i0; |
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269 | /** This is the offset of the i1 register. */ |
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270 | uint32_t i1; |
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271 | /** This is the offset of the i2 register. */ |
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272 | uint32_t i2; |
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273 | /** This is the offset of the i3 register. */ |
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274 | uint32_t i3; |
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275 | /** This is the offset of the i4 register. */ |
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276 | uint32_t i4; |
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277 | /** This is the offset of the i5 register. */ |
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278 | uint32_t i5; |
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279 | /** This is the offset of the i6 register. */ |
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280 | uint32_t i6_fp; |
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281 | /** This is the offset of the i7 register. */ |
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282 | uint32_t i7; |
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283 | /** This is the offset of the register used to return structures. */ |
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284 | void *structure_return_address; |
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285 | |
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286 | /* |
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287 | * The following are for the callee to save the register arguments in |
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288 | * should this be necessary. |
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289 | */ |
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290 | /** This is the offset of the register for saved argument 0. */ |
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291 | uint32_t saved_arg0; |
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292 | /** This is the offset of the register for saved argument 1. */ |
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293 | uint32_t saved_arg1; |
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294 | /** This is the offset of the register for saved argument 2. */ |
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295 | uint32_t saved_arg2; |
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296 | /** This is the offset of the register for saved argument 3. */ |
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297 | uint32_t saved_arg3; |
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298 | /** This is the offset of the register for saved argument 4. */ |
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299 | uint32_t saved_arg4; |
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300 | /** This is the offset of the register for saved argument 5. */ |
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301 | uint32_t saved_arg5; |
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302 | /** This field pads the structure so ldd and std instructions can be used. */ |
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303 | uint32_t pad0; |
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304 | } CPU_Minimum_stack_frame; |
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305 | |
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306 | #endif /* ASM */ |
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307 | |
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308 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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309 | #define CPU_STACK_FRAME_L0_OFFSET 0x00 |
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310 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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311 | #define CPU_STACK_FRAME_L1_OFFSET 0x04 |
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312 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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313 | #define CPU_STACK_FRAME_L2_OFFSET 0x08 |
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314 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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315 | #define CPU_STACK_FRAME_L3_OFFSET 0x0c |
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316 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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317 | #define CPU_STACK_FRAME_L4_OFFSET 0x10 |
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318 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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319 | #define CPU_STACK_FRAME_L5_OFFSET 0x14 |
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320 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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321 | #define CPU_STACK_FRAME_L6_OFFSET 0x18 |
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322 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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323 | #define CPU_STACK_FRAME_L7_OFFSET 0x1c |
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324 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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325 | #define CPU_STACK_FRAME_I0_OFFSET 0x20 |
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326 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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327 | #define CPU_STACK_FRAME_I1_OFFSET 0x24 |
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328 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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329 | #define CPU_STACK_FRAME_I2_OFFSET 0x28 |
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330 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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331 | #define CPU_STACK_FRAME_I3_OFFSET 0x2c |
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332 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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333 | #define CPU_STACK_FRAME_I4_OFFSET 0x30 |
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334 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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335 | #define CPU_STACK_FRAME_I5_OFFSET 0x34 |
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336 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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337 | #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 |
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338 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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339 | #define CPU_STACK_FRAME_I7_OFFSET 0x3c |
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340 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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341 | #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 |
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342 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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343 | #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 |
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344 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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345 | #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 |
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346 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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347 | #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c |
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348 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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349 | #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 |
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350 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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351 | #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 |
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352 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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353 | #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 |
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354 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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355 | #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c |
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356 | |
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357 | /** This defines the size of the minimum stack frame. */ |
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358 | #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 |
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359 | |
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360 | #define CPU_PER_CPU_CONTROL_SIZE 4 |
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361 | |
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362 | /** |
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363 | * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field |
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364 | * relative to the Per_CPU_Control begin. |
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365 | */ |
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366 | #define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 |
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367 | |
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368 | /** |
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369 | * @defgroup Contexts SPARC Context Structures |
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370 | * |
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371 | * @ingroup Score |
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372 | * |
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373 | * Generally there are 2 types of context to save. |
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374 | * + Interrupt registers to save |
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375 | * + Task level registers to save |
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376 | * |
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377 | * This means we have the following 3 context items: |
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378 | * + task level context stuff:: Context_Control |
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379 | * + floating point task stuff:: Context_Control_fp |
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380 | * + special interrupt level context :: Context_Control_interrupt |
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381 | * |
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382 | * On the SPARC, we are relatively conservative in that we save most |
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383 | * of the CPU state in the context area. The ET (enable trap) bit and |
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384 | * the CWP (current window pointer) fields of the PSR are considered |
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385 | * system wide resources and are not maintained on a per-thread basis. |
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386 | */ |
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387 | /**@{**/ |
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388 | |
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389 | #ifndef ASM |
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390 | |
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391 | typedef struct { |
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392 | /** |
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393 | * This flag is context switched with each thread. It indicates |
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394 | * that THIS thread has an _ISR_Dispatch stack frame on its stack. |
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395 | * By using this flag, we can avoid nesting more interrupt dispatching |
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396 | * attempts on a previously interrupted thread's stack. |
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397 | */ |
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398 | uint32_t isr_dispatch_disable; |
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399 | } CPU_Per_CPU_control; |
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400 | |
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401 | /** |
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402 | * @brief SPARC basic context. |
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403 | * |
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404 | * This structure defines the non-volatile integer and processor state context |
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405 | * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY |
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406 | * INTERFACE - SPARC Processor Supplement", Third Edition. |
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407 | */ |
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408 | typedef struct { |
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409 | /** |
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410 | * Using a double g2_g3 will put everything in this structure on a |
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411 | * double word boundary which allows us to use double word loads |
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412 | * and stores safely in the context switch. |
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413 | */ |
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414 | double g2_g3; |
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415 | /** This will contain the contents of the g4 register. */ |
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416 | uint32_t g4; |
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417 | /** This will contain the contents of the g5 register. */ |
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418 | uint32_t g5; |
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419 | /** This will contain the contents of the g6 register. */ |
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420 | uint32_t g6; |
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421 | /** This will contain the contents of the g7 register. */ |
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422 | uint32_t g7; |
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423 | |
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424 | /** This will contain the contents of the l0 register. */ |
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425 | uint32_t l0; |
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426 | /** This will contain the contents of the l1 register. */ |
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427 | uint32_t l1; |
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428 | /** This will contain the contents of the l2 register. */ |
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429 | uint32_t l2; |
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430 | /** This will contain the contents of the l3 register. */ |
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431 | uint32_t l3; |
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432 | /** This will contain the contents of the l4 register. */ |
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433 | uint32_t l4; |
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434 | /** This will contain the contents of the l5 registeer.*/ |
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435 | uint32_t l5; |
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436 | /** This will contain the contents of the l6 register. */ |
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437 | uint32_t l6; |
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438 | /** This will contain the contents of the l7 register. */ |
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439 | uint32_t l7; |
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440 | |
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441 | /** This will contain the contents of the i0 register. */ |
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442 | uint32_t i0; |
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443 | /** This will contain the contents of the i1 register. */ |
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444 | uint32_t i1; |
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445 | /** This will contain the contents of the i2 register. */ |
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446 | uint32_t i2; |
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447 | /** This will contain the contents of the i3 register. */ |
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448 | uint32_t i3; |
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449 | /** This will contain the contents of the i4 register. */ |
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450 | uint32_t i4; |
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451 | /** This will contain the contents of the i5 register. */ |
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452 | uint32_t i5; |
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453 | /** This will contain the contents of the i6 (e.g. frame pointer) register. */ |
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454 | uint32_t i6_fp; |
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455 | /** This will contain the contents of the i7 register. */ |
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456 | uint32_t i7; |
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457 | |
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458 | /** This will contain the contents of the o6 (e.g. frame pointer) register. */ |
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459 | uint32_t o6_sp; |
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460 | /** |
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461 | * This will contain the contents of the o7 (e.g. address of CALL |
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462 | * instruction) register. |
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463 | */ |
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464 | uint32_t o7; |
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465 | |
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466 | /** This will contain the contents of the processor status register. */ |
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467 | uint32_t psr; |
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468 | /** |
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469 | * This field is used to prevent heavy nesting of calls to _Thread_Dispatch |
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470 | * on an interrupted task's stack. This is problematic on the slower |
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471 | * SPARC CPU models at high interrupt rates. |
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472 | */ |
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473 | uint32_t isr_dispatch_disable; |
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474 | } Context_Control; |
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475 | |
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476 | /** |
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477 | * This macro provides a CPU independent way for RTEMS to access the |
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478 | * stack pointer in a context structure. The actual name and offset is |
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479 | * CPU architecture dependent. |
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480 | */ |
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481 | #define _CPU_Context_Get_SP( _context ) \ |
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482 | (_context)->o6_sp |
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483 | |
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484 | #endif /* ASM */ |
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485 | |
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486 | /* |
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487 | * Offsets of fields with Context_Control for assembly routines. |
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488 | */ |
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489 | |
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490 | /** This macro defines an offset into the context for use in assembly. */ |
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491 | #define G2_OFFSET 0x00 |
---|
492 | /** This macro defines an offset into the context for use in assembly. */ |
---|
493 | #define G3_OFFSET 0x04 |
---|
494 | /** This macro defines an offset into the context for use in assembly. */ |
---|
495 | #define G4_OFFSET 0x08 |
---|
496 | /** This macro defines an offset into the context for use in assembly. */ |
---|
497 | #define G5_OFFSET 0x0C |
---|
498 | /** This macro defines an offset into the context for use in assembly. */ |
---|
499 | #define G6_OFFSET 0x10 |
---|
500 | /** This macro defines an offset into the context for use in assembly. */ |
---|
501 | #define G7_OFFSET 0x14 |
---|
502 | |
---|
503 | /** This macro defines an offset into the context for use in assembly. */ |
---|
504 | #define L0_OFFSET 0x18 |
---|
505 | /** This macro defines an offset into the context for use in assembly. */ |
---|
506 | #define L1_OFFSET 0x1C |
---|
507 | /** This macro defines an offset into the context for use in assembly. */ |
---|
508 | #define L2_OFFSET 0x20 |
---|
509 | /** This macro defines an offset into the context for use in assembly. */ |
---|
510 | #define L3_OFFSET 0x24 |
---|
511 | /** This macro defines an offset into the context for use in assembly. */ |
---|
512 | #define L4_OFFSET 0x28 |
---|
513 | /** This macro defines an offset into the context for use in assembly. */ |
---|
514 | #define L5_OFFSET 0x2C |
---|
515 | /** This macro defines an offset into the context for use in assembly. */ |
---|
516 | #define L6_OFFSET 0x30 |
---|
517 | /** This macro defines an offset into the context for use in assembly. */ |
---|
518 | #define L7_OFFSET 0x34 |
---|
519 | |
---|
520 | /** This macro defines an offset into the context for use in assembly. */ |
---|
521 | #define I0_OFFSET 0x38 |
---|
522 | /** This macro defines an offset into the context for use in assembly. */ |
---|
523 | #define I1_OFFSET 0x3C |
---|
524 | /** This macro defines an offset into the context for use in assembly. */ |
---|
525 | #define I2_OFFSET 0x40 |
---|
526 | /** This macro defines an offset into the context for use in assembly. */ |
---|
527 | #define I3_OFFSET 0x44 |
---|
528 | /** This macro defines an offset into the context for use in assembly. */ |
---|
529 | #define I4_OFFSET 0x48 |
---|
530 | /** This macro defines an offset into the context for use in assembly. */ |
---|
531 | #define I5_OFFSET 0x4C |
---|
532 | /** This macro defines an offset into the context for use in assembly. */ |
---|
533 | #define I6_FP_OFFSET 0x50 |
---|
534 | /** This macro defines an offset into the context for use in assembly. */ |
---|
535 | #define I7_OFFSET 0x54 |
---|
536 | |
---|
537 | /** This macro defines an offset into the context for use in assembly. */ |
---|
538 | #define O6_SP_OFFSET 0x58 |
---|
539 | /** This macro defines an offset into the context for use in assembly. */ |
---|
540 | #define O7_OFFSET 0x5C |
---|
541 | |
---|
542 | /** This macro defines an offset into the context for use in assembly. */ |
---|
543 | #define PSR_OFFSET 0x60 |
---|
544 | /** This macro defines an offset into the context for use in assembly. */ |
---|
545 | #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x64 |
---|
546 | |
---|
547 | /** This defines the size of the context area for use in assembly. */ |
---|
548 | #define CONTEXT_CONTROL_SIZE 0x68 |
---|
549 | |
---|
550 | #ifndef ASM |
---|
551 | /** |
---|
552 | * @brief SPARC basic context. |
---|
553 | * |
---|
554 | * This structure defines floating point context area. |
---|
555 | */ |
---|
556 | typedef struct { |
---|
557 | /** This will contain the contents of the f0 and f1 register. */ |
---|
558 | double f0_f1; |
---|
559 | /** This will contain the contents of the f2 and f3 register. */ |
---|
560 | double f2_f3; |
---|
561 | /** This will contain the contents of the f4 and f5 register. */ |
---|
562 | double f4_f5; |
---|
563 | /** This will contain the contents of the f6 and f7 register. */ |
---|
564 | double f6_f7; |
---|
565 | /** This will contain the contents of the f8 and f9 register. */ |
---|
566 | double f8_f9; |
---|
567 | /** This will contain the contents of the f10 and f11 register. */ |
---|
568 | double f10_f11; |
---|
569 | /** This will contain the contents of the f12 and f13 register. */ |
---|
570 | double f12_f13; |
---|
571 | /** This will contain the contents of the f14 and f15 register. */ |
---|
572 | double f14_f15; |
---|
573 | /** This will contain the contents of the f16 and f17 register. */ |
---|
574 | double f16_f17; |
---|
575 | /** This will contain the contents of the f18 and f19 register. */ |
---|
576 | double f18_f19; |
---|
577 | /** This will contain the contents of the f20 and f21 register. */ |
---|
578 | double f20_f21; |
---|
579 | /** This will contain the contents of the f22 and f23 register. */ |
---|
580 | double f22_f23; |
---|
581 | /** This will contain the contents of the f24 and f25 register. */ |
---|
582 | double f24_f25; |
---|
583 | /** This will contain the contents of the f26 and f27 register. */ |
---|
584 | double f26_f27; |
---|
585 | /** This will contain the contents of the f28 and f29 register. */ |
---|
586 | double f28_f29; |
---|
587 | /** This will contain the contents of the f30 and f31 register. */ |
---|
588 | double f30_f31; |
---|
589 | /** This will contain the contents of the floating point status register. */ |
---|
590 | uint32_t fsr; |
---|
591 | } Context_Control_fp; |
---|
592 | |
---|
593 | #endif /* ASM */ |
---|
594 | |
---|
595 | /* |
---|
596 | * Offsets of fields with Context_Control_fp for assembly routines. |
---|
597 | */ |
---|
598 | |
---|
599 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
600 | #define FO_F1_OFFSET 0x00 |
---|
601 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
602 | #define F2_F3_OFFSET 0x08 |
---|
603 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
604 | #define F4_F5_OFFSET 0x10 |
---|
605 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
606 | #define F6_F7_OFFSET 0x18 |
---|
607 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
608 | #define F8_F9_OFFSET 0x20 |
---|
609 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
610 | #define F1O_F11_OFFSET 0x28 |
---|
611 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
612 | #define F12_F13_OFFSET 0x30 |
---|
613 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
614 | #define F14_F15_OFFSET 0x38 |
---|
615 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
616 | #define F16_F17_OFFSET 0x40 |
---|
617 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
618 | #define F18_F19_OFFSET 0x48 |
---|
619 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
620 | #define F2O_F21_OFFSET 0x50 |
---|
621 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
622 | #define F22_F23_OFFSET 0x58 |
---|
623 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
624 | #define F24_F25_OFFSET 0x60 |
---|
625 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
626 | #define F26_F27_OFFSET 0x68 |
---|
627 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
628 | #define F28_F29_OFFSET 0x70 |
---|
629 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
630 | #define F3O_F31_OFFSET 0x78 |
---|
631 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
632 | #define FSR_OFFSET 0x80 |
---|
633 | |
---|
634 | /** This defines the size of the FPU context area for use in assembly. */ |
---|
635 | #define CONTEXT_CONTROL_FP_SIZE 0x84 |
---|
636 | |
---|
637 | #ifndef ASM |
---|
638 | |
---|
639 | /** @} */ |
---|
640 | |
---|
641 | /** |
---|
642 | * @brief Interrupt stack frame (ISF). |
---|
643 | * |
---|
644 | * Context saved on stack for an interrupt. |
---|
645 | * |
---|
646 | * NOTE: The PSR, PC, and NPC are only saved in this structure for the |
---|
647 | * benefit of the user's handler. |
---|
648 | */ |
---|
649 | typedef struct { |
---|
650 | /** On an interrupt, we must save the minimum stack frame. */ |
---|
651 | CPU_Minimum_stack_frame Stack_frame; |
---|
652 | /** This is the offset of the PSR on an ISF. */ |
---|
653 | uint32_t psr; |
---|
654 | /** This is the offset of the XXX on an ISF. */ |
---|
655 | uint32_t pc; |
---|
656 | /** This is the offset of the XXX on an ISF. */ |
---|
657 | uint32_t npc; |
---|
658 | /** This is the offset of the g1 register on an ISF. */ |
---|
659 | uint32_t g1; |
---|
660 | /** This is the offset of the g2 register on an ISF. */ |
---|
661 | uint32_t g2; |
---|
662 | /** This is the offset of the g3 register on an ISF. */ |
---|
663 | uint32_t g3; |
---|
664 | /** This is the offset of the g4 register on an ISF. */ |
---|
665 | uint32_t g4; |
---|
666 | /** This is the offset of the g5 register on an ISF. */ |
---|
667 | uint32_t g5; |
---|
668 | /** This is the offset of the g6 register on an ISF. */ |
---|
669 | uint32_t g6; |
---|
670 | /** This is the offset of the g7 register on an ISF. */ |
---|
671 | uint32_t g7; |
---|
672 | /** This is the offset of the i0 register on an ISF. */ |
---|
673 | uint32_t i0; |
---|
674 | /** This is the offset of the i1 register on an ISF. */ |
---|
675 | uint32_t i1; |
---|
676 | /** This is the offset of the i2 register on an ISF. */ |
---|
677 | uint32_t i2; |
---|
678 | /** This is the offset of the i3 register on an ISF. */ |
---|
679 | uint32_t i3; |
---|
680 | /** This is the offset of the i4 register on an ISF. */ |
---|
681 | uint32_t i4; |
---|
682 | /** This is the offset of the i5 register on an ISF. */ |
---|
683 | uint32_t i5; |
---|
684 | /** This is the offset of the i6 register on an ISF. */ |
---|
685 | uint32_t i6_fp; |
---|
686 | /** This is the offset of the i7 register on an ISF. */ |
---|
687 | uint32_t i7; |
---|
688 | /** This is the offset of the y register on an ISF. */ |
---|
689 | uint32_t y; |
---|
690 | /** This is the offset of the tpc register on an ISF. */ |
---|
691 | uint32_t tpc; |
---|
692 | } CPU_Interrupt_frame; |
---|
693 | |
---|
694 | #endif /* ASM */ |
---|
695 | |
---|
696 | /* |
---|
697 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
---|
698 | */ |
---|
699 | |
---|
700 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
701 | #define ISF_STACK_FRAME_OFFSET 0x00 |
---|
702 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
703 | #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 |
---|
704 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
705 | #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 |
---|
706 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
707 | #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 |
---|
708 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
709 | #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c |
---|
710 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
711 | #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 |
---|
712 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
713 | #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 |
---|
714 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
715 | #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 |
---|
716 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
717 | #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c |
---|
718 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
719 | #define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 |
---|
720 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
721 | #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 |
---|
722 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
723 | #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 |
---|
724 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
725 | #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c |
---|
726 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
727 | #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 |
---|
728 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
729 | #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 |
---|
730 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
731 | #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 |
---|
732 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
733 | #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c |
---|
734 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
735 | #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 |
---|
736 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
737 | #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 |
---|
738 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
739 | #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 |
---|
740 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
741 | #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c |
---|
742 | |
---|
743 | /** This defines the size of the ISF area for use in assembly. */ |
---|
744 | #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ |
---|
745 | CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 |
---|
746 | |
---|
747 | #ifndef ASM |
---|
748 | /** |
---|
749 | * This variable is contains the initialize context for the FP unit. |
---|
750 | * It is filled in by _CPU_Initialize and copied into the task's FP |
---|
751 | * context area during _CPU_Context_Initialize. |
---|
752 | */ |
---|
753 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; |
---|
754 | |
---|
755 | /** |
---|
756 | * The following type defines an entry in the SPARC's trap table. |
---|
757 | * |
---|
758 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
759 | * obligated to use two of the four instructions to perform a |
---|
760 | * long jump. The other instructions load one register with the |
---|
761 | * trap type (a.k.a. vector) and another with the psr. |
---|
762 | */ |
---|
763 | typedef struct { |
---|
764 | /** This will contain a "mov %psr, %l0" instruction. */ |
---|
765 | uint32_t mov_psr_l0; |
---|
766 | /** This will contain a "sethi %hi(_handler), %l4" instruction. */ |
---|
767 | uint32_t sethi_of_handler_to_l4; |
---|
768 | /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ |
---|
769 | uint32_t jmp_to_low_of_handler_plus_l4; |
---|
770 | /** This will contain a " mov _vector, %l3" instruction. */ |
---|
771 | uint32_t mov_vector_l3; |
---|
772 | } CPU_Trap_table_entry; |
---|
773 | |
---|
774 | /** |
---|
775 | * This is the set of opcodes for the instructions loaded into a trap |
---|
776 | * table entry. The routine which installs a handler is responsible |
---|
777 | * for filling in the fields for the _handler address and the _vector |
---|
778 | * trap type. |
---|
779 | * |
---|
780 | * The constants following this structure are masks for the fields which |
---|
781 | * must be filled in when the handler is installed. |
---|
782 | */ |
---|
783 | extern const CPU_Trap_table_entry _CPU_Trap_slot_template; |
---|
784 | |
---|
785 | /** |
---|
786 | * The size of the floating point context area. |
---|
787 | */ |
---|
788 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
789 | |
---|
790 | #endif |
---|
791 | |
---|
792 | /** |
---|
793 | * Amount of extra stack (above minimum stack size) required by |
---|
794 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
795 | * system this thread must exist and be able to process all directives. |
---|
796 | */ |
---|
797 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
---|
798 | |
---|
799 | /** |
---|
800 | * This defines the number of entries in the ISR_Vector_table managed |
---|
801 | * by the executive. |
---|
802 | * |
---|
803 | * On the SPARC, there are really only 256 vectors. However, the executive |
---|
804 | * has no easy, fast, reliable way to determine which traps are synchronous |
---|
805 | * and which are asynchronous. By default, synchronous traps return to the |
---|
806 | * instruction which caused the interrupt. So if you install a software |
---|
807 | * trap handler as an executive interrupt handler (which is desirable since |
---|
808 | * RTEMS takes care of window and register issues), then the executive needs |
---|
809 | * to know that the return address is to the trap rather than the instruction |
---|
810 | * following the trap. |
---|
811 | * |
---|
812 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
---|
813 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
---|
814 | * by the executive to be synchronous and to require that the return address |
---|
815 | * be fudged. |
---|
816 | * |
---|
817 | * If you use this mechanism to install a trap handler which must reexecute |
---|
818 | * the instruction which caused the trap, then it should be installed as |
---|
819 | * an asynchronous trap. This will avoid the executive changing the return |
---|
820 | * address. |
---|
821 | */ |
---|
822 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
823 | |
---|
824 | /** |
---|
825 | * The SPARC has 256 vectors but the port treats 256-512 as synchronous |
---|
826 | * traps. |
---|
827 | */ |
---|
828 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 |
---|
829 | |
---|
830 | /** |
---|
831 | * This is the bit step in a vector number to indicate it is being installed |
---|
832 | * as a synchronous trap. |
---|
833 | */ |
---|
834 | #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
---|
835 | |
---|
836 | /** |
---|
837 | * This macro indicates that @a _trap as an asynchronous trap. |
---|
838 | */ |
---|
839 | #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
---|
840 | |
---|
841 | /** |
---|
842 | * This macro indicates that @a _trap as a synchronous trap. |
---|
843 | */ |
---|
844 | #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) |
---|
845 | |
---|
846 | /** |
---|
847 | * This macro returns the real hardware vector number associated with @a _trap. |
---|
848 | */ |
---|
849 | #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) |
---|
850 | |
---|
851 | /** |
---|
852 | * This is defined if the port has a special way to report the ISR nesting |
---|
853 | * level. Most ports maintain the variable _ISR_Nest_level. |
---|
854 | */ |
---|
855 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
856 | |
---|
857 | /** |
---|
858 | * Should be large enough to run all tests. This ensures |
---|
859 | * that a "reasonable" small application should not have any problems. |
---|
860 | * |
---|
861 | * This appears to be a fairly generous number for the SPARC since |
---|
862 | * represents a call depth of about 20 routines based on the minimum |
---|
863 | * stack frame. |
---|
864 | */ |
---|
865 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
866 | |
---|
867 | /** |
---|
868 | * What is the size of a pointer on this architecture? |
---|
869 | */ |
---|
870 | #define CPU_SIZEOF_POINTER 4 |
---|
871 | |
---|
872 | /** |
---|
873 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
874 | * alignment does not take into account the requirements for the stack. |
---|
875 | * |
---|
876 | * On the SPARC, this is required for double word loads and stores. |
---|
877 | */ |
---|
878 | #define CPU_ALIGNMENT 8 |
---|
879 | |
---|
880 | /** |
---|
881 | * This number corresponds to the byte alignment requirement for the |
---|
882 | * heap handler. This alignment requirement may be stricter than that |
---|
883 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
884 | * common for the heap to follow the same alignment requirement as |
---|
885 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
886 | * then this should be set to CPU_ALIGNMENT. |
---|
887 | * |
---|
888 | * NOTE: This does not have to be a power of 2. It does have to |
---|
889 | * be greater or equal to than CPU_ALIGNMENT. |
---|
890 | */ |
---|
891 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
892 | |
---|
893 | /** |
---|
894 | * This number corresponds to the byte alignment requirement for memory |
---|
895 | * buffers allocated by the partition manager. This alignment requirement |
---|
896 | * may be stricter than that for the data types alignment specified by |
---|
897 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
898 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
899 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
900 | * |
---|
901 | * NOTE: This does not have to be a power of 2. It does have to |
---|
902 | * be greater or equal to than CPU_ALIGNMENT. |
---|
903 | */ |
---|
904 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
905 | |
---|
906 | /** |
---|
907 | * This number corresponds to the byte alignment requirement for the |
---|
908 | * stack. This alignment requirement may be stricter than that for the |
---|
909 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
910 | * is strict enough for the stack, then this should be set to 0. |
---|
911 | * |
---|
912 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
913 | * |
---|
914 | * The alignment restrictions for the SPARC are not that strict but this |
---|
915 | * should unsure that the stack is always sufficiently alignment that the |
---|
916 | * window overflow, underflow, and flush routines can use double word loads |
---|
917 | * and stores. |
---|
918 | */ |
---|
919 | #define CPU_STACK_ALIGNMENT 16 |
---|
920 | |
---|
921 | #ifndef ASM |
---|
922 | |
---|
923 | /* |
---|
924 | * ISR handler macros |
---|
925 | */ |
---|
926 | |
---|
927 | /** |
---|
928 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
929 | */ |
---|
930 | #define _CPU_Initialize_vectors() |
---|
931 | |
---|
932 | /** |
---|
933 | * Disable all interrupts for a critical section. The previous |
---|
934 | * level is returned in _level. |
---|
935 | */ |
---|
936 | #define _CPU_ISR_Disable( _level ) \ |
---|
937 | (_level) = sparc_disable_interrupts() |
---|
938 | |
---|
939 | /** |
---|
940 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
941 | * This indicates the end of a critical section. The parameter |
---|
942 | * _level is not modified. |
---|
943 | */ |
---|
944 | #define _CPU_ISR_Enable( _level ) \ |
---|
945 | sparc_enable_interrupts( _level ) |
---|
946 | |
---|
947 | /** |
---|
948 | * This temporarily restores the interrupt to _level before immediately |
---|
949 | * disabling them again. This is used to divide long critical |
---|
950 | * sections into two or more parts. The parameter _level is not |
---|
951 | * modified. |
---|
952 | */ |
---|
953 | #define _CPU_ISR_Flash( _level ) \ |
---|
954 | sparc_flash_interrupts( _level ) |
---|
955 | |
---|
956 | /** |
---|
957 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
958 | * actually provides. Currently, interrupt levels which do not |
---|
959 | * map onto the CPU in a straight fashion are undefined. |
---|
960 | */ |
---|
961 | #define _CPU_ISR_Set_level( _newlevel ) \ |
---|
962 | sparc_enable_interrupts( _newlevel << 8) |
---|
963 | |
---|
964 | /** |
---|
965 | * @brief Obtain the current interrupt disable level. |
---|
966 | * |
---|
967 | * This method is invoked to return the current interrupt disable level. |
---|
968 | * |
---|
969 | * @return This method returns the current interrupt disable level. |
---|
970 | */ |
---|
971 | uint32_t _CPU_ISR_Get_level( void ); |
---|
972 | |
---|
973 | /* end of ISR handler macros */ |
---|
974 | |
---|
975 | /* Context handler macros */ |
---|
976 | |
---|
977 | /** |
---|
978 | * Initialize the context to a state suitable for starting a |
---|
979 | * task after a context restore operation. Generally, this |
---|
980 | * involves: |
---|
981 | * |
---|
982 | * - setting a starting address |
---|
983 | * - preparing the stack |
---|
984 | * - preparing the stack and frame pointers |
---|
985 | * - setting the proper interrupt level in the context |
---|
986 | * - initializing the floating point context |
---|
987 | * |
---|
988 | * @param[in] the_context points to the context area |
---|
989 | * @param[in] stack_base is the low address of the allocated stack area |
---|
990 | * @param[in] size is the size of the stack area in bytes |
---|
991 | * @param[in] new_level is the interrupt level for the task |
---|
992 | * @param[in] entry_point is the task's entry point |
---|
993 | * @param[in] is_fp is set to TRUE if the task is a floating point task |
---|
994 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
995 | * |
---|
996 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
997 | */ |
---|
998 | void _CPU_Context_Initialize( |
---|
999 | Context_Control *the_context, |
---|
1000 | uint32_t *stack_base, |
---|
1001 | uint32_t size, |
---|
1002 | uint32_t new_level, |
---|
1003 | void *entry_point, |
---|
1004 | bool is_fp, |
---|
1005 | void *tls_area |
---|
1006 | ); |
---|
1007 | |
---|
1008 | /** |
---|
1009 | * This macro is invoked from _Thread_Handler to do whatever CPU |
---|
1010 | * specific magic is required that must be done in the context of |
---|
1011 | * the thread when it starts. |
---|
1012 | * |
---|
1013 | * On the SPARC, this is setting the frame pointer so GDB is happy. |
---|
1014 | * Make GDB stop unwinding at _Thread_Handler, previous register window |
---|
1015 | * Frame pointer is 0 and calling address must be a function with starting |
---|
1016 | * with a SAVE instruction. If return address is leaf-function (no SAVE) |
---|
1017 | * GDB will not look at prev reg window fp. |
---|
1018 | * |
---|
1019 | * _Thread_Handler is known to start with SAVE. |
---|
1020 | */ |
---|
1021 | #define _CPU_Context_Initialization_at_thread_begin() \ |
---|
1022 | do { \ |
---|
1023 | __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ |
---|
1024 | } while (0) |
---|
1025 | |
---|
1026 | /** |
---|
1027 | * This routine is responsible for somehow restarting the currently |
---|
1028 | * executing task. |
---|
1029 | * |
---|
1030 | * On the SPARC, this is is relatively painless but requires a small |
---|
1031 | * amount of wrapper code before using the regular restore code in |
---|
1032 | * of the context switch. |
---|
1033 | */ |
---|
1034 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
1035 | _CPU_Context_restore( (_the_context) ); |
---|
1036 | |
---|
1037 | /** |
---|
1038 | * The FP context area for the SPARC is a simple structure and nothing |
---|
1039 | * special is required to find the "starting load point" |
---|
1040 | */ |
---|
1041 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
1042 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
1043 | |
---|
1044 | /** |
---|
1045 | * This routine initializes the FP context area passed to it to. |
---|
1046 | * |
---|
1047 | * The SPARC allows us to use the simple initialization model |
---|
1048 | * in which an "initial" FP context was saved into _CPU_Null_fp_context |
---|
1049 | * at CPU initialization and it is simply copied into the destination |
---|
1050 | * context. |
---|
1051 | */ |
---|
1052 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
1053 | do { \ |
---|
1054 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
1055 | } while (0) |
---|
1056 | |
---|
1057 | /* end of Context handler macros */ |
---|
1058 | |
---|
1059 | /* Fatal Error manager macros */ |
---|
1060 | |
---|
1061 | /** |
---|
1062 | * This routine copies _error into a known place -- typically a stack |
---|
1063 | * location or a register, optionally disables interrupts, and |
---|
1064 | * halts/stops the CPU. |
---|
1065 | */ |
---|
1066 | #define _CPU_Fatal_halt( _error ) \ |
---|
1067 | do { \ |
---|
1068 | uint32_t level; \ |
---|
1069 | \ |
---|
1070 | level = sparc_disable_interrupts(); \ |
---|
1071 | __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ |
---|
1072 | while (1); /* loop forever */ \ |
---|
1073 | } while (0) |
---|
1074 | |
---|
1075 | /* end of Fatal Error manager macros */ |
---|
1076 | |
---|
1077 | /* Bitfield handler macros */ |
---|
1078 | |
---|
1079 | #if ( SPARC_HAS_BITSCAN == 0 ) |
---|
1080 | /** |
---|
1081 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
1082 | * CPU model does not have a scan instruction. |
---|
1083 | */ |
---|
1084 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
1085 | /** |
---|
1086 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
1087 | * CPU model does not have a scan instruction. Thus is needs the generic |
---|
1088 | * data table used by that algorithm. |
---|
1089 | */ |
---|
1090 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
1091 | #else |
---|
1092 | #error "scan instruction not currently supported by RTEMS!!" |
---|
1093 | #endif |
---|
1094 | |
---|
1095 | /* end of Bitfield handler macros */ |
---|
1096 | |
---|
1097 | /* functions */ |
---|
1098 | |
---|
1099 | /** |
---|
1100 | * @brief SPARC specific initialization. |
---|
1101 | * |
---|
1102 | * This routine performs CPU dependent initialization. |
---|
1103 | */ |
---|
1104 | void _CPU_Initialize(void); |
---|
1105 | |
---|
1106 | /** |
---|
1107 | * @brief SPARC specific raw ISR installer. |
---|
1108 | * |
---|
1109 | * This routine installs @a new_handler to be directly called from the trap |
---|
1110 | * table. |
---|
1111 | * |
---|
1112 | * @param[in] vector is the vector number |
---|
1113 | * @param[in] new_handler is the new ISR handler |
---|
1114 | * @param[in] old_handler will contain the old ISR handler |
---|
1115 | */ |
---|
1116 | void _CPU_ISR_install_raw_handler( |
---|
1117 | uint32_t vector, |
---|
1118 | proc_ptr new_handler, |
---|
1119 | proc_ptr *old_handler |
---|
1120 | ); |
---|
1121 | |
---|
1122 | /** |
---|
1123 | * @brief SPARC specific RTEMS ISR installer. |
---|
1124 | * |
---|
1125 | * This routine installs an interrupt vector. |
---|
1126 | * |
---|
1127 | * @param[in] vector is the vector number |
---|
1128 | * @param[in] new_handler is the new ISR handler |
---|
1129 | * @param[in] old_handler will contain the old ISR handler |
---|
1130 | */ |
---|
1131 | |
---|
1132 | void _CPU_ISR_install_vector( |
---|
1133 | uint32_t vector, |
---|
1134 | proc_ptr new_handler, |
---|
1135 | proc_ptr *old_handler |
---|
1136 | ); |
---|
1137 | |
---|
1138 | /** |
---|
1139 | * @brief SPARC specific context switch. |
---|
1140 | * |
---|
1141 | * This routine switches from the run context to the heir context. |
---|
1142 | * |
---|
1143 | * @param[in] run is the currently executing thread |
---|
1144 | * @param[in] heir will become the currently executing thread |
---|
1145 | */ |
---|
1146 | void _CPU_Context_switch( |
---|
1147 | Context_Control *run, |
---|
1148 | Context_Control *heir |
---|
1149 | ); |
---|
1150 | |
---|
1151 | /** |
---|
1152 | * @brief SPARC specific context restore. |
---|
1153 | * |
---|
1154 | * This routine is generally used only to restart self in an |
---|
1155 | * efficient manner. |
---|
1156 | * |
---|
1157 | * @param[in] new_context is the context to restore |
---|
1158 | */ |
---|
1159 | void _CPU_Context_restore( |
---|
1160 | Context_Control *new_context |
---|
1161 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
1162 | |
---|
1163 | #if defined(RTEMS_SMP) |
---|
1164 | uint32_t _CPU_SMP_Initialize( uint32_t configured_cpu_count ); |
---|
1165 | |
---|
1166 | #if defined(__leon__) |
---|
1167 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
1168 | { |
---|
1169 | return _LEON3_Get_current_processor(); |
---|
1170 | } |
---|
1171 | #else |
---|
1172 | uint32_t _CPU_SMP_Get_current_processor( void ); |
---|
1173 | #endif |
---|
1174 | |
---|
1175 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
1176 | |
---|
1177 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
1178 | { |
---|
1179 | __asm__ volatile ( "" : : : "memory" ); |
---|
1180 | } |
---|
1181 | |
---|
1182 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
1183 | { |
---|
1184 | __asm__ volatile ( "" : : : "memory" ); |
---|
1185 | } |
---|
1186 | #endif |
---|
1187 | |
---|
1188 | /** |
---|
1189 | * @brief SPARC specific save FPU method. |
---|
1190 | * |
---|
1191 | * This routine saves the floating point context passed to it. |
---|
1192 | * |
---|
1193 | * @param[in] fp_context_ptr is the area to save into |
---|
1194 | */ |
---|
1195 | void _CPU_Context_save_fp( |
---|
1196 | Context_Control_fp **fp_context_ptr |
---|
1197 | ); |
---|
1198 | |
---|
1199 | /** |
---|
1200 | * @brief SPARC specific restore FPU method. |
---|
1201 | * |
---|
1202 | * This routine restores the floating point context passed to it. |
---|
1203 | * |
---|
1204 | * @param[in] fp_context_ptr is the area to restore from |
---|
1205 | */ |
---|
1206 | void _CPU_Context_restore_fp( |
---|
1207 | Context_Control_fp **fp_context_ptr |
---|
1208 | ); |
---|
1209 | |
---|
1210 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
1211 | { |
---|
1212 | /* TODO */ |
---|
1213 | } |
---|
1214 | |
---|
1215 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
1216 | { |
---|
1217 | while (1) { |
---|
1218 | /* TODO */ |
---|
1219 | } |
---|
1220 | } |
---|
1221 | |
---|
1222 | typedef struct { |
---|
1223 | uint32_t trap; |
---|
1224 | CPU_Interrupt_frame *isf; |
---|
1225 | } CPU_Exception_frame; |
---|
1226 | |
---|
1227 | void _BSP_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
1228 | |
---|
1229 | static inline void _CPU_Exception_frame_print( |
---|
1230 | const CPU_Exception_frame *frame |
---|
1231 | ) |
---|
1232 | { |
---|
1233 | _BSP_Exception_frame_print( frame ); |
---|
1234 | } |
---|
1235 | |
---|
1236 | /** |
---|
1237 | * @brief SPARC specific method to endian swap an uint32_t. |
---|
1238 | * |
---|
1239 | * The following routine swaps the endian format of an unsigned int. |
---|
1240 | * It must be static because it is referenced indirectly. |
---|
1241 | * |
---|
1242 | * @param[in] value is the value to endian swap |
---|
1243 | * |
---|
1244 | * This version will work on any processor, but if you come across a better |
---|
1245 | * way for the SPARC PLEASE use it. The most common way to swap a 32-bit |
---|
1246 | * entity as shown below is not any more efficient on the SPARC. |
---|
1247 | * |
---|
1248 | * - swap least significant two bytes with 16-bit rotate |
---|
1249 | * - swap upper and lower 16-bits |
---|
1250 | * - swap most significant two bytes with 16-bit rotate |
---|
1251 | * |
---|
1252 | * It is not obvious how the SPARC can do significantly better than the |
---|
1253 | * generic code. gcc 2.7.0 only generates about 12 instructions for the |
---|
1254 | * following code at optimization level four (i.e. -O4). |
---|
1255 | */ |
---|
1256 | static inline uint32_t CPU_swap_u32( |
---|
1257 | uint32_t value |
---|
1258 | ) |
---|
1259 | { |
---|
1260 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
1261 | |
---|
1262 | byte4 = (value >> 24) & 0xff; |
---|
1263 | byte3 = (value >> 16) & 0xff; |
---|
1264 | byte2 = (value >> 8) & 0xff; |
---|
1265 | byte1 = value & 0xff; |
---|
1266 | |
---|
1267 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
1268 | return( swapped ); |
---|
1269 | } |
---|
1270 | |
---|
1271 | /** |
---|
1272 | * @brief SPARC specific method to endian swap an uint16_t. |
---|
1273 | * |
---|
1274 | * The following routine swaps the endian format of a uint16_t. |
---|
1275 | * |
---|
1276 | * @param[in] value is the value to endian swap |
---|
1277 | */ |
---|
1278 | #define CPU_swap_u16( value ) \ |
---|
1279 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
1280 | |
---|
1281 | typedef uint32_t CPU_Counter_ticks; |
---|
1282 | |
---|
1283 | typedef CPU_Counter_ticks (*SPARC_Counter_difference)( |
---|
1284 | CPU_Counter_ticks second, |
---|
1285 | CPU_Counter_ticks first |
---|
1286 | ); |
---|
1287 | |
---|
1288 | /* |
---|
1289 | * The SPARC processors supported by RTEMS have no built-in CPU counter |
---|
1290 | * support. We have to use some hardware counter module for this purpose. The |
---|
1291 | * BSP must provide a 32-bit register which contains the current CPU counter |
---|
1292 | * value and a function for the difference calculation. It can use for example |
---|
1293 | * the GPTIMER instance used for the clock driver. |
---|
1294 | */ |
---|
1295 | typedef struct { |
---|
1296 | volatile const CPU_Counter_ticks *counter_register; |
---|
1297 | SPARC_Counter_difference counter_difference; |
---|
1298 | } SPARC_Counter; |
---|
1299 | |
---|
1300 | extern SPARC_Counter _SPARC_Counter; |
---|
1301 | |
---|
1302 | /* |
---|
1303 | * Returns always a value of one regardless of the parameters. This prevents |
---|
1304 | * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe |
---|
1305 | * default. |
---|
1306 | */ |
---|
1307 | CPU_Counter_ticks _SPARC_Counter_difference_default( |
---|
1308 | CPU_Counter_ticks second, |
---|
1309 | CPU_Counter_ticks first |
---|
1310 | ); |
---|
1311 | |
---|
1312 | static inline bool _SPARC_Counter_is_default( void ) |
---|
1313 | { |
---|
1314 | return _SPARC_Counter.counter_difference |
---|
1315 | == _SPARC_Counter_difference_default; |
---|
1316 | } |
---|
1317 | |
---|
1318 | static inline void _SPARC_Counter_initialize( |
---|
1319 | volatile const CPU_Counter_ticks *counter_register, |
---|
1320 | SPARC_Counter_difference counter_difference |
---|
1321 | ) |
---|
1322 | { |
---|
1323 | _SPARC_Counter.counter_register = counter_register; |
---|
1324 | _SPARC_Counter.counter_difference = counter_difference; |
---|
1325 | } |
---|
1326 | |
---|
1327 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
1328 | { |
---|
1329 | return *_SPARC_Counter.counter_register; |
---|
1330 | } |
---|
1331 | |
---|
1332 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
1333 | CPU_Counter_ticks second, |
---|
1334 | CPU_Counter_ticks first |
---|
1335 | ) |
---|
1336 | { |
---|
1337 | return (*_SPARC_Counter.counter_difference)( second, first ); |
---|
1338 | } |
---|
1339 | |
---|
1340 | #endif /* ASM */ |
---|
1341 | |
---|
1342 | #ifdef __cplusplus |
---|
1343 | } |
---|
1344 | #endif |
---|
1345 | |
---|
1346 | #endif |
---|