source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ 3ccb4b0

4.104.114.84.95
Last change on this file since 3ccb4b0 was ada7b9e, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/17/07 at 04:49:05

Use Context_Control_fp* instead of void* for fp_contexts. Eliminate evil casts.

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File size: 28.3 KB
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1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the port of
7 *  the executive to the SPARC processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/sparc.h>               /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33/*
34 *  Should the calls to _Thread_Enable_dispatch be inlined?
35 *
36 *  If TRUE, then they are inlined.
37 *  If FALSE, then a subroutine call is made.
38 */
39
40#define CPU_INLINE_ENABLE_DISPATCH       TRUE
41
42/*
43 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
44 *  be unrolled one time?  In unrolled each iteration of the loop examines
45 *  two "nodes" on the chain being searched.  Otherwise, only one node
46 *  is examined per iteration.
47 *
48 *  If TRUE, then the loops are unrolled.
49 *  If FALSE, then the loops are not unrolled.
50 *
51 *  This parameter could go either way on the SPARC.  The interrupt flash
52 *  code is relatively lengthy given the requirements for nops following
53 *  writes to the psr.  But if the clock speed were high enough, this would
54 *  not represent a great deal of time.
55 */
56
57#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
58
59/*
60 *  Does the executive manage a dedicated interrupt stack in software?
61 *
62 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
63 *  If FALSE, nothing is done.
64 *
65 *  The SPARC does not have a dedicated HW interrupt stack and one has
66 *  been implemented in SW.
67 */
68
69#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
70
71/*
72 *  Does this CPU have hardware support for a dedicated interrupt stack?
73 *
74 *  If TRUE, then it must be installed during initialization.
75 *  If FALSE, then no installation is performed.
76 *
77 *  The SPARC does not have a dedicated HW interrupt stack.
78 */
79
80#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
81
82/*
83 *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
84 *
85 *  If TRUE, then the memory is allocated during initialization.
86 *  If FALSE, then the memory is allocated during initialization.
87 */
88
89#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
90
91/*
92 *  Does the RTEMS invoke the user's ISR with the vector number and
93 *  a pointer to the saved interrupt frame (1) or just the vector
94 *  number (0)?
95 */
96
97#define CPU_ISR_PASSES_FRAME_POINTER 0
98
99/*
100 *  Does the CPU have hardware floating point?
101 *
102 *  If TRUE, then the FLOATING_POINT task attribute is supported.
103 *  If FALSE, then the FLOATING_POINT task attribute is ignored.
104 */
105
106#if ( SPARC_HAS_FPU == 1 )
107#define CPU_HARDWARE_FP     TRUE
108#else
109#define CPU_HARDWARE_FP     FALSE
110#endif
111#define CPU_SOFTWARE_FP     FALSE
112
113/*
114 *  Are all tasks FLOATING_POINT tasks implicitly?
115 *
116 *  If TRUE, then the FLOATING_POINT task attribute is assumed.
117 *  If FALSE, then the FLOATING_POINT task attribute is followed.
118 */
119
120#define CPU_ALL_TASKS_ARE_FP     FALSE
121
122/*
123 *  Should the IDLE task have a floating point context?
124 *
125 *  If TRUE, then the IDLE task is created as a FLOATING_POINT task
126 *  and it has a floating point context which is switched in and out.
127 *  If FALSE, then the IDLE task does not have a floating point context.
128 */
129
130#define CPU_IDLE_TASK_IS_FP      FALSE
131
132/*
133 *  Should the saving of the floating point registers be deferred
134 *  until a context switch is made to another different floating point
135 *  task?
136 *
137 *  If TRUE, then the floating point context will not be stored until
138 *  necessary.  It will remain in the floating point registers and not
139 *  disturned until another floating point task is switched to.
140 *
141 *  If FALSE, then the floating point context is saved when a floating
142 *  point task is switched out and restored when the next floating point
143 *  task is restored.  The state of the floating point registers between
144 *  those two operations is not specified.
145 */
146
147#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
148
149/*
150 *  Does this port provide a CPU dependent IDLE task implementation?
151 *
152 *  If TRUE, then the routine _CPU_Thread_Idle_body
153 *  must be provided and is the default IDLE thread body instead of
154 *  _CPU_Thread_Idle_body.
155 *
156 *  If FALSE, then use the generic IDLE thread body if the BSP does
157 *  not provide one.
158 */
159
160#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
161
162/*
163 *  Does the stack grow up (toward higher addresses) or down
164 *  (toward lower addresses)?
165 *
166 *  If TRUE, then the grows upward.
167 *  If FALSE, then the grows toward smaller addresses.
168 *
169 *  The stack grows to lower addresses on the SPARC.
170 */
171
172#define CPU_STACK_GROWS_UP               FALSE
173
174/*
175 *  The following is the variable attribute used to force alignment
176 *  of critical data structures.  On some processors it may make
177 *  sense to have these aligned on tighter boundaries than
178 *  the minimum requirements of the compiler in order to have as
179 *  much of the critical data area as possible in a cache line.
180 *
181 *  The SPARC does not appear to have particularly strict alignment
182 *  requirements.  This value was chosen to take advantages of caches.
183 */
184
185#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
186
187/*
188 *  Define what is required to specify how the network to host conversion
189 *  routines are handled.
190 */
191
192#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
193#define CPU_BIG_ENDIAN                           TRUE
194#define CPU_LITTLE_ENDIAN                        FALSE
195
196/*
197 *  The following defines the number of bits actually used in the
198 *  interrupt field of the task mode.  How those bits map to the
199 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
200 *
201 *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
202 */
203
204#define CPU_MODES_INTERRUPT_MASK   0x0000000F
205
206/*
207 *  This structure represents the organization of the minimum stack frame
208 *  for the SPARC.  More framing information is required in certain situaions
209 *  such as when there are a large number of out parameters or when the callee
210 *  must save floating point registers.
211 */
212
213#ifndef ASM
214
215typedef struct {
216  uint32_t    l0;
217  uint32_t    l1;
218  uint32_t    l2;
219  uint32_t    l3;
220  uint32_t    l4;
221  uint32_t    l5;
222  uint32_t    l6;
223  uint32_t    l7;
224  uint32_t    i0;
225  uint32_t    i1;
226  uint32_t    i2;
227  uint32_t    i3;
228  uint32_t    i4;
229  uint32_t    i5;
230  uint32_t    i6_fp;
231  uint32_t    i7;
232  void       *structure_return_address;
233  /*
234   *  The following are for the callee to save the register arguments in
235   *  should this be necessary.
236   */
237  uint32_t    saved_arg0;
238  uint32_t    saved_arg1;
239  uint32_t    saved_arg2;
240  uint32_t    saved_arg3;
241  uint32_t    saved_arg4;
242  uint32_t    saved_arg5;
243  uint32_t    pad0;
244}  CPU_Minimum_stack_frame;
245
246#endif /* ASM */
247
248#define CPU_STACK_FRAME_L0_OFFSET             0x00
249#define CPU_STACK_FRAME_L1_OFFSET             0x04
250#define CPU_STACK_FRAME_L2_OFFSET             0x08
251#define CPU_STACK_FRAME_L3_OFFSET             0x0c
252#define CPU_STACK_FRAME_L4_OFFSET             0x10
253#define CPU_STACK_FRAME_L5_OFFSET             0x14
254#define CPU_STACK_FRAME_L6_OFFSET             0x18
255#define CPU_STACK_FRAME_L7_OFFSET             0x1c
256#define CPU_STACK_FRAME_I0_OFFSET             0x20
257#define CPU_STACK_FRAME_I1_OFFSET             0x24
258#define CPU_STACK_FRAME_I2_OFFSET             0x28
259#define CPU_STACK_FRAME_I3_OFFSET             0x2c
260#define CPU_STACK_FRAME_I4_OFFSET             0x30
261#define CPU_STACK_FRAME_I5_OFFSET             0x34
262#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
263#define CPU_STACK_FRAME_I7_OFFSET             0x3c
264#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
265#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
266#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
267#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
268#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
269#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
270#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
271#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
272
273#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
274
275/*
276 * Contexts
277 *
278 *  Generally there are 2 types of context to save.
279 *     1. Interrupt registers to save
280 *     2. Task level registers to save
281 *
282 *  This means we have the following 3 context items:
283 *     1. task level context stuff::  Context_Control
284 *     2. floating point task stuff:: Context_Control_fp
285 *     3. special interrupt level context :: Context_Control_interrupt
286 *
287 *  On the SPARC, we are relatively conservative in that we save most
288 *  of the CPU state in the context area.  The ET (enable trap) bit and
289 *  the CWP (current window pointer) fields of the PSR are considered
290 *  system wide resources and are not maintained on a per-thread basis.
291 */
292
293#ifndef ASM
294
295typedef struct {
296    /*
297     *  Using a double g0_g1 will put everything in this structure on a
298     *  double word boundary which allows us to use double word loads
299     *  and stores safely in the context switch.
300     */
301    double     g0_g1;
302    uint32_t   g2;
303    uint32_t   g3;
304    uint32_t   g4;
305    uint32_t   g5;
306    uint32_t   g6;
307    uint32_t   g7;
308
309    uint32_t   l0;
310    uint32_t   l1;
311    uint32_t   l2;
312    uint32_t   l3;
313    uint32_t   l4;
314    uint32_t   l5;
315    uint32_t   l6;
316    uint32_t   l7;
317
318    uint32_t   i0;
319    uint32_t   i1;
320    uint32_t   i2;
321    uint32_t   i3;
322    uint32_t   i4;
323    uint32_t   i5;
324    uint32_t   i6_fp;
325    uint32_t   i7;
326
327    uint32_t   o0;
328    uint32_t   o1;
329    uint32_t   o2;
330    uint32_t   o3;
331    uint32_t   o4;
332    uint32_t   o5;
333    uint32_t   o6_sp;
334    uint32_t   o7;
335
336    uint32_t   psr;
337} Context_Control;
338
339#endif /* ASM */
340
341/*
342 *  Offsets of fields with Context_Control for assembly routines.
343 */
344
345#define G0_OFFSET    0x00
346#define G1_OFFSET    0x04
347#define G2_OFFSET    0x08
348#define G3_OFFSET    0x0C
349#define G4_OFFSET    0x10
350#define G5_OFFSET    0x14
351#define G6_OFFSET    0x18
352#define G7_OFFSET    0x1C
353
354#define L0_OFFSET    0x20
355#define L1_OFFSET    0x24
356#define L2_OFFSET    0x28
357#define L3_OFFSET    0x2C
358#define L4_OFFSET    0x30
359#define L5_OFFSET    0x34
360#define L6_OFFSET    0x38
361#define L7_OFFSET    0x3C
362
363#define I0_OFFSET    0x40
364#define I1_OFFSET    0x44
365#define I2_OFFSET    0x48
366#define I3_OFFSET    0x4C
367#define I4_OFFSET    0x50
368#define I5_OFFSET    0x54
369#define I6_FP_OFFSET 0x58
370#define I7_OFFSET    0x5C
371
372#define O0_OFFSET    0x60
373#define O1_OFFSET    0x64
374#define O2_OFFSET    0x68
375#define O3_OFFSET    0x6C
376#define O4_OFFSET    0x70
377#define O5_OFFSET    0x74
378#define O6_SP_OFFSET 0x78
379#define O7_OFFSET    0x7C
380
381#define PSR_OFFSET   0x80
382
383#define CONTEXT_CONTROL_SIZE 0x84
384
385/*
386 *  The floating point context area.
387 */
388
389#ifndef ASM
390
391typedef struct {
392    double      f0_f1;
393    double      f2_f3;
394    double      f4_f5;
395    double      f6_f7;
396    double      f8_f9;
397    double      f10_f11;
398    double      f12_f13;
399    double      f14_f15;
400    double      f16_f17;
401    double      f18_f19;
402    double      f20_f21;
403    double      f22_f23;
404    double      f24_f25;
405    double      f26_f27;
406    double      f28_f29;
407    double      f30_f31;
408    uint32_t    fsr;
409} Context_Control_fp;
410
411#endif /* ASM */
412
413/*
414 *  Offsets of fields with Context_Control_fp for assembly routines.
415 */
416
417#define FO_F1_OFFSET     0x00
418#define F2_F3_OFFSET     0x08
419#define F4_F5_OFFSET     0x10
420#define F6_F7_OFFSET     0x18
421#define F8_F9_OFFSET     0x20
422#define F1O_F11_OFFSET   0x28
423#define F12_F13_OFFSET   0x30
424#define F14_F15_OFFSET   0x38
425#define F16_F17_OFFSET   0x40
426#define F18_F19_OFFSET   0x48
427#define F2O_F21_OFFSET   0x50
428#define F22_F23_OFFSET   0x58
429#define F24_F25_OFFSET   0x60
430#define F26_F27_OFFSET   0x68
431#define F28_F29_OFFSET   0x70
432#define F3O_F31_OFFSET   0x78
433#define FSR_OFFSET       0x80
434
435#define CONTEXT_CONTROL_FP_SIZE 0x84
436
437#ifndef ASM
438
439/*
440 *  Context saved on stack for an interrupt.
441 *
442 *  NOTE:  The PSR, PC, and NPC are only saved in this structure for the
443 *         benefit of the user's handler.
444 */
445
446typedef struct {
447  CPU_Minimum_stack_frame  Stack_frame;
448  uint32_t                 psr;
449  uint32_t                 pc;
450  uint32_t                 npc;
451  uint32_t                 g1;
452  uint32_t                 g2;
453  uint32_t                 g3;
454  uint32_t                 g4;
455  uint32_t                 g5;
456  uint32_t                 g6;
457  uint32_t                 g7;
458  uint32_t                 i0;
459  uint32_t                 i1;
460  uint32_t                 i2;
461  uint32_t                 i3;
462  uint32_t                 i4;
463  uint32_t                 i5;
464  uint32_t                 i6_fp;
465  uint32_t                 i7;
466  uint32_t                 y;
467  uint32_t                 tpc;
468} CPU_Interrupt_frame;
469
470#endif /* ASM */
471
472/*
473 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
474 */
475
476#define ISF_STACK_FRAME_OFFSET 0x00
477#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
478#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
479#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
480#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
481#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
482#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
483#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
484#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
485#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
486#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
487#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
488#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
489#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
490#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
491#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
492#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
493#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
494#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
495#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
496#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
497
498#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
499#ifndef ASM
500
501/*
502 *  The following table contains the information required to configure
503 *  the processor specific parameters.
504 */
505
506typedef struct {
507  void       (*pretasking_hook)( void );
508  void       (*predriver_hook)( void );
509  void       (*postdriver_hook)( void );
510  void       (*idle_task)( void );
511  boolean      do_zero_of_workspace;
512  uint32_t     idle_task_stack_size;
513  uint32_t     interrupt_stack_size;
514  uint32_t     extra_mpci_receive_server_stack;
515  void *     (*stack_allocate_hook)( uint32_t   );
516  void       (*stack_free_hook)( void* );
517  /* end of fields required on all CPUs */
518
519}   rtems_cpu_table;
520
521/*
522 *  Macros to access required entires in the CPU Table are in
523 *  the file rtems/system.h.
524 */
525
526/*
527 *  Macros to access SPARC specific additions to the CPU Table
528 */
529
530/* There are no CPU specific additions to the CPU Table for this port. */
531
532/*
533 *  This variable is contains the initialize context for the FP unit.
534 *  It is filled in by _CPU_Initialize and copied into the task's FP
535 *  context area during _CPU_Context_Initialize.
536 */
537
538SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
539
540/*
541 *  This stack is allocated by the Interrupt Manager and the switch
542 *  is performed in _ISR_Handler.  These variables contain pointers
543 *  to the lowest and highest addresses in the chunk of memory allocated
544 *  for the interrupt stack.  Since it is unknown whether the stack
545 *  grows up or down (in general), this give the CPU dependent
546 *  code the option of picking the version it wants to use.  Thus
547 *  both must be present if either is.
548 *
549 *  The SPARC supports a software based interrupt stack and these
550 *  are required.
551 */
552
553SCORE_EXTERN void *_CPU_Interrupt_stack_low;
554SCORE_EXTERN void *_CPU_Interrupt_stack_high;
555
556/*
557 *  The following type defines an entry in the SPARC's trap table.
558 *
559 *  NOTE: The instructions chosen are RTEMS dependent although one is
560 *        obligated to use two of the four instructions to perform a
561 *        long jump.  The other instructions load one register with the
562 *        trap type (a.k.a. vector) and another with the psr.
563 */
564 
565typedef struct {
566  uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
567  uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
568  uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
569  uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
570} CPU_Trap_table_entry;
571 
572/*
573 *  This is the set of opcodes for the instructions loaded into a trap
574 *  table entry.  The routine which installs a handler is responsible
575 *  for filling in the fields for the _handler address and the _vector
576 *  trap type.
577 *
578 *  The constants following this structure are masks for the fields which
579 *  must be filled in when the handler is installed.
580 */
581 
582extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
583
584/*
585 *  The size of the floating point context area. 
586 */
587
588#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
589
590#endif
591
592/*
593 *  Amount of extra stack (above minimum stack size) required by
594 *  MPCI receive server thread.  Remember that in a multiprocessor
595 *  system this thread must exist and be able to process all directives.
596 */
597
598#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
599
600/*
601 *  This defines the number of entries in the ISR_Vector_table managed
602 *  by the executive.
603 *
604 *  On the SPARC, there are really only 256 vectors.  However, the executive
605 *  has no easy, fast, reliable way to determine which traps are synchronous
606 *  and which are asynchronous.  By default, synchronous traps return to the
607 *  instruction which caused the interrupt.  So if you install a software
608 *  trap handler as an executive interrupt handler (which is desirable since
609 *  RTEMS takes care of window and register issues), then the executive needs
610 *  to know that the return address is to the trap rather than the instruction
611 *  following the trap.
612 *
613 *  So vectors 0 through 255 are treated as regular asynchronous traps which
614 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
615 *  by the executive to be synchronous and to require that the return address
616 *  be fudged.
617 *
618 *  If you use this mechanism to install a trap handler which must reexecute
619 *  the instruction which caused the trap, then it should be installed as
620 *  an asynchronous trap.  This will avoid the executive changing the return
621 *  address.
622 */
623
624#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
625#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
626
627#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
628#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
629#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
630
631#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
632
633/*
634 *  This is defined if the port has a special way to report the ISR nesting
635 *  level.  Most ports maintain the variable _ISR_Nest_level.
636 */
637
638#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
639
640/*
641 *  Should be large enough to run all tests.  This ensures
642 *  that a "reasonable" small application should not have any problems.
643 *
644 *  This appears to be a fairly generous number for the SPARC since
645 *  represents a call depth of about 20 routines based on the minimum
646 *  stack frame.
647 */
648
649#define CPU_STACK_MINIMUM_SIZE  (1024*4)
650
651/*
652 *  CPU's worst alignment requirement for data types on a byte boundary.  This
653 *  alignment does not take into account the requirements for the stack.
654 *
655 *  On the SPARC, this is required for double word loads and stores.
656 */
657
658#define CPU_ALIGNMENT      8
659
660/*
661 *  This number corresponds to the byte alignment requirement for the
662 *  heap handler.  This alignment requirement may be stricter than that
663 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
664 *  common for the heap to follow the same alignment requirement as
665 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
666 *  then this should be set to CPU_ALIGNMENT.
667 *
668 *  NOTE:  This does not have to be a power of 2.  It does have to
669 *         be greater or equal to than CPU_ALIGNMENT.
670 */
671
672#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
673
674/*
675 *  This number corresponds to the byte alignment requirement for memory
676 *  buffers allocated by the partition manager.  This alignment requirement
677 *  may be stricter than that for the data types alignment specified by
678 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
679 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
680 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
681 *
682 *  NOTE:  This does not have to be a power of 2.  It does have to
683 *         be greater or equal to than CPU_ALIGNMENT.
684 */
685
686#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
687
688/*
689 *  This number corresponds to the byte alignment requirement for the
690 *  stack.  This alignment requirement may be stricter than that for the
691 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
692 *  is strict enough for the stack, then this should be set to 0.
693 *
694 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
695 *
696 *  The alignment restrictions for the SPARC are not that strict but this
697 *  should unsure that the stack is always sufficiently alignment that the
698 *  window overflow, underflow, and flush routines can use double word loads
699 *  and stores.
700 */
701
702#define CPU_STACK_ALIGNMENT        16
703
704#ifndef ASM
705
706extern unsigned int sparc_disable_interrupts();
707extern void sparc_enable_interrupts();
708
709/*
710 *  ISR handler macros
711 */
712
713/*
714 *  Support routine to initialize the RTEMS vector table after it is allocated.
715 */
716
717#define _CPU_Initialize_vectors()
718
719/*
720 *  Disable all interrupts for a critical section.  The previous
721 *  level is returned in _level.
722 */
723
724#define _CPU_ISR_Disable( _level ) \
725  (_level) = sparc_disable_interrupts()
726 
727/*
728 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
729 *  This indicates the end of a critical section.  The parameter
730 *  _level is not modified.
731 */
732
733#define _CPU_ISR_Enable( _level ) \
734  sparc_enable_interrupts( _level )
735/*
736 *  This temporarily restores the interrupt to _level before immediately
737 *  disabling them again.  This is used to divide long critical
738 *  sections into two or more parts.  The parameter _level is not
739 *  modified.
740 */
741
742#define _CPU_ISR_Flash( _level ) \
743  sparc_flash_interrupts( _level )
744 
745/*
746 *  Map interrupt level in task mode onto the hardware that the CPU
747 *  actually provides.  Currently, interrupt levels which do not
748 *  map onto the CPU in a straight fashion are undefined. 
749 */
750
751#define _CPU_ISR_Set_level( _newlevel ) \
752   sparc_enable_interrupts( _newlevel << 8)
753 
754uint32_t   _CPU_ISR_Get_level( void );
755 
756/* end of ISR handler macros */
757
758/* Context handler macros */
759
760/*
761 *  Initialize the context to a state suitable for starting a
762 *  task after a context restore operation.  Generally, this
763 *  involves:
764 *
765 *     - setting a starting address
766 *     - preparing the stack
767 *     - preparing the stack and frame pointers
768 *     - setting the proper interrupt level in the context
769 *     - initializing the floating point context
770 *
771 *  NOTE:  Implemented as a subroutine for the SPARC port.
772 */
773
774void _CPU_Context_Initialize(
775  Context_Control  *the_context,
776  uint32_t         *stack_base,
777  uint32_t          size,
778  uint32_t          new_level,
779  void             *entry_point,
780  boolean           is_fp
781);
782
783/*
784 *  This routine is responsible for somehow restarting the currently
785 *  executing task. 
786 *
787 *  On the SPARC, this is is relatively painless but requires a small
788 *  amount of wrapper code before using the regular restore code in
789 *  of the context switch.
790 */
791
792#define _CPU_Context_Restart_self( _the_context ) \
793   _CPU_Context_restore( (_the_context) );
794
795/*
796 *  The FP context area for the SPARC is a simple structure and nothing
797 *  special is required to find the "starting load point"
798 */
799
800#define _CPU_Context_Fp_start( _base, _offset ) \
801   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
802
803/*
804 *  This routine initializes the FP context area passed to it to.
805 *
806 *  The SPARC allows us to use the simple initialization model
807 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
808 *  at CPU initialization and it is simply copied into the destination
809 *  context.
810 */
811
812#define _CPU_Context_Initialize_fp( _destination ) \
813  do { \
814   *(*(_destination)) = _CPU_Null_fp_context; \
815  } while (0)
816
817/* end of Context handler macros */
818
819/* Fatal Error manager macros */
820
821/*
822 *  This routine copies _error into a known place -- typically a stack
823 *  location or a register, optionally disables interrupts, and
824 *  halts/stops the CPU.
825 */
826
827#define _CPU_Fatal_halt( _error ) \
828  do { \
829    uint32_t   level; \
830    \
831    level = sparc_disable_interrupts(); \
832    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
833    while (1); /* loop forever */ \
834  } while (0)
835
836/* end of Fatal Error manager macros */
837
838/* Bitfield handler macros */
839
840/*
841 *  The SPARC port uses the generic C algorithm for bitfield scan if the
842 *  CPU model does not have a scan instruction.
843 */
844
845#if ( SPARC_HAS_BITSCAN == 0 )
846#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
847#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
848#else
849#error "scan instruction not currently supported by RTEMS!!"
850#endif
851
852/* end of Bitfield handler macros */
853
854/* Priority handler handler macros */
855
856/*
857 *  The SPARC port uses the generic C algorithm for bitfield scan if the
858 *  CPU model does not have a scan instruction.
859 */
860
861#if ( SPARC_HAS_BITSCAN == 1 )
862#error "scan instruction not currently supported by RTEMS!!"
863#endif
864
865/* end of Priority handler macros */
866
867/* functions */
868
869/*
870 *  _CPU_Initialize
871 *
872 *  This routine performs CPU dependent initialization.
873 */
874
875void _CPU_Initialize(
876  rtems_cpu_table  *cpu_table,
877  void            (*thread_dispatch)
878);
879
880/*
881 *  _CPU_ISR_install_raw_handler
882 *
883 *  This routine installs new_handler to be directly called from the trap
884 *  table.
885 */
886 
887void _CPU_ISR_install_raw_handler(
888  uint32_t    vector,
889  proc_ptr    new_handler,
890  proc_ptr   *old_handler
891);
892
893/*
894 *  _CPU_ISR_install_vector
895 *
896 *  This routine installs an interrupt vector.
897 */
898
899void _CPU_ISR_install_vector(
900  uint32_t    vector,
901  proc_ptr    new_handler,
902  proc_ptr   *old_handler
903);
904
905#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
906 
907/*
908 *  _CPU_Thread_Idle_body
909 *
910 *  Some SPARC implementations have low power, sleep, or idle modes.  This
911 *  tries to take advantage of those models.
912 */
913 
914void _CPU_Thread_Idle_body( void );
915 
916#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
917
918/*
919 *  _CPU_Context_switch
920 *
921 *  This routine switches from the run context to the heir context.
922 */
923
924void _CPU_Context_switch(
925  Context_Control  *run,
926  Context_Control  *heir
927);
928
929/*
930 *  _CPU_Context_restore
931 *
932 *  This routine is generally used only to restart self in an
933 *  efficient manner.
934 */
935
936void _CPU_Context_restore(
937  Context_Control *new_context
938);
939
940/*
941 *  _CPU_Context_save_fp
942 *
943 *  This routine saves the floating point context passed to it.
944 */
945
946void _CPU_Context_save_fp(
947  Context_Control_fp **fp_context_ptr
948);
949
950/*
951 *  _CPU_Context_restore_fp
952 *
953 *  This routine restores the floating point context passed to it.
954 */
955
956void _CPU_Context_restore_fp(
957  Context_Control_fp **fp_context_ptr
958);
959
960/*
961 *  CPU_swap_u32
962 *
963 *  The following routine swaps the endian format of an unsigned int.
964 *  It must be static because it is referenced indirectly.
965 *
966 *  This version will work on any processor, but if you come across a better
967 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
968 *  entity as shown below is not any more efficient on the SPARC.
969 *
970 *     swap least significant two bytes with 16-bit rotate
971 *     swap upper and lower 16-bits
972 *     swap most significant two bytes with 16-bit rotate
973 *
974 *  It is not obvious how the SPARC can do significantly better than the
975 *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
976 *  following code at optimization level four (i.e. -O4).
977 */
978 
979static inline uint32_t CPU_swap_u32(
980  uint32_t value
981)
982{
983  uint32_t   byte1, byte2, byte3, byte4, swapped;
984 
985  byte4 = (value >> 24) & 0xff;
986  byte3 = (value >> 16) & 0xff;
987  byte2 = (value >> 8)  & 0xff;
988  byte1 =  value        & 0xff;
989 
990  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
991  return( swapped );
992}
993
994#define CPU_swap_u16( value ) \
995  (((value&0xff) << 8) | ((value >> 8)&0xff))
996
997#endif /* ASM */
998
999#ifdef __cplusplus
1000}
1001#endif
1002
1003#endif
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