source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ 2f6108f9

4.115
Last change on this file since 2f6108f9 was 2f6108f9, checked in by Sebastian Huber <sebastian.huber@…>, on May 28, 2013 at 8:58:19 AM

smp: Simplify SMP initialization sequence

Delete bsp_smp_wait_for(). Other parts of the system work without
timeout, e.g. the spinlocks. Using a timeout here does not make the
system more robust.

Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The
Per_CPU_State follows the Score naming conventions. Add
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to
change and observe states.

Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer.

Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive()
functions provided by the CPU port. Use these functions in
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state().

Add prototype for _SMP_Send_message().

Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is
now performed in rtems_smp_secondary_cpu_initialize(). Issuing the
first context switch in the context of the inter-processor interrupt is
not possible on systems with a modern interrupt controller. Such an
interrupt controler usually requires a handshake protocol with interrupt
acknowledge and end of interrupt signals. A direct context switch in an
interrupt handler circumvents the interrupt processing epilogue and may
leave the system in an inconsistent state.

Release lock in rtems_smp_process_interrupt() even if no message was
delivered. This prevents deadlock of the system.

Simplify and format _SMP_Send_message(),
_SMP_Request_other_cores_to_perform_first_context_switch(),
_SMP_Request_other_cores_to_dispatch() and
_SMP_Request_other_cores_to_shutdown().

  • Property mode set to 100644
File size: 45.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief SPARC CPU Department Source
5 *
6 * This include file contains information pertaining to the port of
7 * the executive to the SPARC processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/sparc.h>
28
29/* conditional compilation parameters */
30
31/**
32 * Should the calls to _Thread_Enable_dispatch be inlined?
33 *
34 * - If TRUE, then they are inlined.
35 * - If FALSE, then a subroutine call is made.
36 *
37 * On this port, it is faster to inline _Thread_Enable_dispatch.
38 */
39#define CPU_INLINE_ENABLE_DISPATCH       TRUE
40
41/**
42 * Should the body of the search loops in _Thread_queue_Enqueue_priority
43 * be unrolled one time?  In unrolled each iteration of the loop examines
44 * two "nodes" on the chain being searched.  Otherwise, only one node
45 * is examined per iteration.
46 *
47 * - If TRUE, then the loops are unrolled.
48 * - If FALSE, then the loops are not unrolled.
49 *
50 * This parameter could go either way on the SPARC.  The interrupt flash
51 * code is relatively lengthy given the requirements for nops following
52 * writes to the psr.  But if the clock speed were high enough, this would
53 * not represent a great deal of time.
54 */
55#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
56
57/**
58 * Does the executive manage a dedicated interrupt stack in software?
59 *
60 * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
61 * If FALSE, nothing is done.
62 *
63 * The SPARC does not have a dedicated HW interrupt stack and one has
64 * been implemented in SW.
65 */
66#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
67
68/**
69 * Does the CPU follow the simple vectored interrupt model?
70 *
71 * - If TRUE, then RTEMS allocates the vector table it internally manages.
72 * - If FALSE, then the BSP is assumed to allocate and manage the vector
73 *   table
74 *
75 * THe SPARC is a simple vectored architecture.  Usually there is no
76 * PIC and the CPU directly vectors the interrupts.
77 */
78#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
79
80/**
81 * Does this CPU have hardware support for a dedicated interrupt stack?
82 *
83 * - If TRUE, then it must be installed during initialization.
84 * - If FALSE, then no installation is performed.
85 *
86 * The SPARC does not have a dedicated HW interrupt stack.
87 */
88#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
89
90/**
91 * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
92 *
93 * - If TRUE, then the memory is allocated during initialization.
94 * - If FALSE, then the memory is allocated during initialization.
95 *
96 * The SPARC does not have hardware support for switching to a
97 * dedicated interrupt stack.  The port includes support for doing this
98 * in software.
99 *
100 */
101#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
102
103/**
104 * Does the RTEMS invoke the user's ISR with the vector number and
105 * a pointer to the saved interrupt frame (1) or just the vector
106 * number (0)?
107 *
108 * The SPARC port does not pass an Interrupt Stack Frame pointer to
109 * interrupt handlers.
110 */
111#define CPU_ISR_PASSES_FRAME_POINTER 0
112
113/**
114 * Does the CPU have hardware floating point?
115 *
116 * - If TRUE, then the FLOATING_POINT task attribute is supported.
117 * - If FALSE, then the FLOATING_POINT task attribute is ignored.
118 *
119 * This is set based upon the multilib settings.
120 */
121#if ( SPARC_HAS_FPU == 1 )
122  #define CPU_HARDWARE_FP     TRUE
123#else
124  #define CPU_HARDWARE_FP     FALSE
125#endif
126
127/**
128 * The SPARC GCC port does not have a software floating point library
129 * that requires RTEMS assistance.
130 */
131#define CPU_SOFTWARE_FP     FALSE
132
133/**
134 * Are all tasks FLOATING_POINT tasks implicitly?
135 *
136 * - If TRUE, then the FLOATING_POINT task attribute is assumed.
137 * - If FALSE, then the FLOATING_POINT task attribute is followed.
138 *
139 * The SPARC GCC port does not implicitly use floating point registers.
140 */
141#define CPU_ALL_TASKS_ARE_FP     FALSE
142
143/**
144 * Should the IDLE task have a floating point context?
145 *
146 * - If TRUE, then the IDLE task is created as a FLOATING_POINT task
147 *   and it has a floating point context which is switched in and out.
148 * - If FALSE, then the IDLE task does not have a floating point context.
149 *
150 * The IDLE task does not have to be floating point on the SPARC.
151 */
152#define CPU_IDLE_TASK_IS_FP      FALSE
153
154/**
155 * Should the saving of the floating point registers be deferred
156 * until a context switch is made to another different floating point
157 * task?
158 *
159 * - If TRUE, then the floating point context will not be stored until
160 * necessary.  It will remain in the floating point registers and not
161 * disturned until another floating point task is switched to.
162 *
163 * - If FALSE, then the floating point context is saved when a floating
164 * point task is switched out and restored when the next floating point
165 * task is restored.  The state of the floating point registers between
166 * those two operations is not specified.
167 *
168 * On the SPARC, we can disable the FPU for integer only tasks so
169 * it is safe to defer floating point context switches.
170 */
171#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
172
173/**
174 * Does this port provide a CPU dependent IDLE task implementation?
175 *
176 * - If TRUE, then the routine _CPU_Thread_Idle_body
177 * must be provided and is the default IDLE thread body instead of
178 * _CPU_Thread_Idle_body.
179 *
180 * - If FALSE, then use the generic IDLE thread body if the BSP does
181 * not provide one.
182 *
183 * The SPARC architecture does not have a low power or halt instruction.
184 * It is left to the BSP and/or CPU specific code to provide an IDLE
185 * thread body which is aware of low power modes.
186 */
187#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
188
189/**
190 * Does the stack grow up (toward higher addresses) or down
191 * (toward lower addresses)?
192 *
193 * - If TRUE, then the grows upward.
194 * - If FALSE, then the grows toward smaller addresses.
195 *
196 * The stack grows to lower addresses on the SPARC.
197 */
198#define CPU_STACK_GROWS_UP               FALSE
199
200/**
201 * The following is the variable attribute used to force alignment
202 * of critical data structures.  On some processors it may make
203 * sense to have these aligned on tighter boundaries than
204 * the minimum requirements of the compiler in order to have as
205 * much of the critical data area as possible in a cache line.
206 *
207 * The SPARC does not appear to have particularly strict alignment
208 * requirements.  This value was chosen to take advantages of caches.
209 */
210#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
211
212#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
213
214/**
215 * Define what is required to specify how the network to host conversion
216 * routines are handled.
217 *
218 * The SPARC is big endian.
219 */
220#define CPU_BIG_ENDIAN                           TRUE
221
222/**
223 * Define what is required to specify how the network to host conversion
224 * routines are handled.
225 *
226 * The SPARC is NOT little endian.
227 */
228#define CPU_LITTLE_ENDIAN                        FALSE
229
230/**
231 * The following defines the number of bits actually used in the
232 * interrupt field of the task mode.  How those bits map to the
233 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
234 *
235 * The SPARC has 16 interrupt levels in the PIL field of the PSR.
236 */
237#define CPU_MODES_INTERRUPT_MASK   0x0000000F
238
239#ifndef ASM
240/**
241 * This structure represents the organization of the minimum stack frame
242 * for the SPARC.  More framing information is required in certain situaions
243 * such as when there are a large number of out parameters or when the callee
244 * must save floating point registers.
245 */
246typedef struct {
247  /** This is the offset of the l0 register. */
248  uint32_t    l0;
249  /** This is the offset of the l1 register. */
250  uint32_t    l1;
251  /** This is the offset of the l2 register. */
252  uint32_t    l2;
253  /** This is the offset of the l3 register. */
254  uint32_t    l3;
255  /** This is the offset of the l4 register. */
256  uint32_t    l4;
257  /** This is the offset of the l5 register. */
258  uint32_t    l5;
259  /** This is the offset of the l6 register. */
260  uint32_t    l6;
261  /** This is the offset of the l7 register. */
262  uint32_t    l7;
263  /** This is the offset of the l0 register. */
264  uint32_t    i0;
265  /** This is the offset of the i1 register. */
266  uint32_t    i1;
267  /** This is the offset of the i2 register. */
268  uint32_t    i2;
269  /** This is the offset of the i3 register. */
270  uint32_t    i3;
271  /** This is the offset of the i4 register. */
272  uint32_t    i4;
273  /** This is the offset of the i5 register. */
274  uint32_t    i5;
275  /** This is the offset of the i6 register. */
276  uint32_t    i6_fp;
277  /** This is the offset of the i7 register. */
278  uint32_t    i7;
279  /** This is the offset of the register used to return structures. */
280  void       *structure_return_address;
281
282  /*
283   * The following are for the callee to save the register arguments in
284   * should this be necessary.
285   */
286  /** This is the offset of the register for saved argument 0. */
287  uint32_t    saved_arg0;
288  /** This is the offset of the register for saved argument 1. */
289  uint32_t    saved_arg1;
290  /** This is the offset of the register for saved argument 2. */
291  uint32_t    saved_arg2;
292  /** This is the offset of the register for saved argument 3. */
293  uint32_t    saved_arg3;
294  /** This is the offset of the register for saved argument 4. */
295  uint32_t    saved_arg4;
296  /** This is the offset of the register for saved argument 5. */
297  uint32_t    saved_arg5;
298  /** This field pads the structure so ldd and std instructions can be used. */
299  uint32_t    pad0;
300}  CPU_Minimum_stack_frame;
301
302#endif /* ASM */
303
304/** This macro defines an offset into the stack frame for use in assembly. */
305#define CPU_STACK_FRAME_L0_OFFSET             0x00
306/** This macro defines an offset into the stack frame for use in assembly. */
307#define CPU_STACK_FRAME_L1_OFFSET             0x04
308/** This macro defines an offset into the stack frame for use in assembly. */
309#define CPU_STACK_FRAME_L2_OFFSET             0x08
310/** This macro defines an offset into the stack frame for use in assembly. */
311#define CPU_STACK_FRAME_L3_OFFSET             0x0c
312/** This macro defines an offset into the stack frame for use in assembly. */
313#define CPU_STACK_FRAME_L4_OFFSET             0x10
314/** This macro defines an offset into the stack frame for use in assembly. */
315#define CPU_STACK_FRAME_L5_OFFSET             0x14
316/** This macro defines an offset into the stack frame for use in assembly. */
317#define CPU_STACK_FRAME_L6_OFFSET             0x18
318/** This macro defines an offset into the stack frame for use in assembly. */
319#define CPU_STACK_FRAME_L7_OFFSET             0x1c
320/** This macro defines an offset into the stack frame for use in assembly. */
321#define CPU_STACK_FRAME_I0_OFFSET             0x20
322/** This macro defines an offset into the stack frame for use in assembly. */
323#define CPU_STACK_FRAME_I1_OFFSET             0x24
324/** This macro defines an offset into the stack frame for use in assembly. */
325#define CPU_STACK_FRAME_I2_OFFSET             0x28
326/** This macro defines an offset into the stack frame for use in assembly. */
327#define CPU_STACK_FRAME_I3_OFFSET             0x2c
328/** This macro defines an offset into the stack frame for use in assembly. */
329#define CPU_STACK_FRAME_I4_OFFSET             0x30
330/** This macro defines an offset into the stack frame for use in assembly. */
331#define CPU_STACK_FRAME_I5_OFFSET             0x34
332/** This macro defines an offset into the stack frame for use in assembly. */
333#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
334/** This macro defines an offset into the stack frame for use in assembly. */
335#define CPU_STACK_FRAME_I7_OFFSET             0x3c
336/** This macro defines an offset into the stack frame for use in assembly. */
337#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
338/** This macro defines an offset into the stack frame for use in assembly. */
339#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
340/** This macro defines an offset into the stack frame for use in assembly. */
341#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
342/** This macro defines an offset into the stack frame for use in assembly. */
343#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
344/** This macro defines an offset into the stack frame for use in assembly. */
345#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
346/** This macro defines an offset into the stack frame for use in assembly. */
347#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
348/** This macro defines an offset into the stack frame for use in assembly. */
349#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
350/** This macro defines an offset into the stack frame for use in assembly. */
351#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
352
353/** This defines the size of the minimum stack frame. */
354#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
355
356/**
357 * @defgroup Contexts SPARC Context Structures
358 *
359 * @ingroup Score
360 *
361 * Generally there are 2 types of context to save.
362 *    + Interrupt registers to save
363 *    + Task level registers to save
364 *
365 * This means we have the following 3 context items:
366 *    + task level context stuff::  Context_Control
367 *    + floating point task stuff:: Context_Control_fp
368 *    + special interrupt level context :: Context_Control_interrupt
369 *
370 * On the SPARC, we are relatively conservative in that we save most
371 * of the CPU state in the context area.  The ET (enable trap) bit and
372 * the CWP (current window pointer) fields of the PSR are considered
373 * system wide resources and are not maintained on a per-thread basis.
374 */
375/**@{**/
376
377#ifndef ASM
378/**
379 * @brief SPARC basic context.
380 *
381 * This structure defines the basic integer and processor state context
382 * for the SPARC architecture.
383 */
384typedef struct {
385  /**
386   * Using a double g0_g1 will put everything in this structure on a
387   * double word boundary which allows us to use double word loads
388   * and stores safely in the context switch.
389   */
390  double     g0_g1;
391  /** This will contain the contents of the g2 register. */
392  uint32_t   g2;
393  /** This will contain the contents of the g3 register. */
394  uint32_t   g3;
395  /** This will contain the contents of the g4 register. */
396  uint32_t   g4;
397  /** This will contain the contents of the g5 register. */
398  uint32_t   g5;
399  /** This will contain the contents of the g6 register. */
400  uint32_t   g6;
401  /** This will contain the contents of the g7 register. */
402  uint32_t   g7;
403
404  /** This will contain the contents of the l0 register. */
405  uint32_t   l0;
406  /** This will contain the contents of the l1 register. */
407  uint32_t   l1;
408  /** This will contain the contents of the l2 register. */
409  uint32_t   l2;
410  /** This will contain the contents of the l3 register. */
411  uint32_t   l3;
412  /** This will contain the contents of the l4 register. */
413  uint32_t   l4;
414  /** This will contain the contents of the l5 registeer.*/
415  uint32_t   l5;
416  /** This will contain the contents of the l6 register. */
417  uint32_t   l6;
418  /** This will contain the contents of the l7 register. */
419  uint32_t   l7;
420
421  /** This will contain the contents of the i0 register. */
422  uint32_t   i0;
423  /** This will contain the contents of the i1 register. */
424  uint32_t   i1;
425  /** This will contain the contents of the i2 register. */
426  uint32_t   i2;
427  /** This will contain the contents of the i3 register. */
428  uint32_t   i3;
429  /** This will contain the contents of the i4 register. */
430  uint32_t   i4;
431  /** This will contain the contents of the i5 register. */
432  uint32_t   i5;
433  /** This will contain the contents of the i6 (e.g. frame pointer) register. */
434  uint32_t   i6_fp;
435  /** This will contain the contents of the i7 register. */
436  uint32_t   i7;
437
438  /** This will contain the contents of the o0 register. */
439  uint32_t   o0;
440  /** This will contain the contents of the o1 register. */
441  uint32_t   o1;
442  /** This will contain the contents of the o2 register. */
443  uint32_t   o2;
444  /** This will contain the contents of the o3 register. */
445  uint32_t   o3;
446  /** This will contain the contents of the o4 register. */
447  uint32_t   o4;
448  /** This will contain the contents of the o5 register. */
449  uint32_t   o5;
450  /** This will contain the contents of the o6 (e.g. frame pointer) register. */
451  uint32_t   o6_sp;
452  /** This will contain the contents of the o7 register. */
453  uint32_t   o7;
454
455  /** This will contain the contents of the processor status register. */
456  uint32_t   psr;
457  /**
458   * This field is used to prevent heavy nesting of calls to _Thread_Dispatch
459   * on an interrupted  task's stack.  This is problematic on the slower
460   * SPARC CPU models at high interrupt rates.
461   */
462  uint32_t   isr_dispatch_disable;
463} Context_Control;
464
465/**
466 * This macro provides a CPU independent way for RTEMS to access the
467 * stack pointer in a context structure. The actual name and offset is
468 * CPU architecture dependent.
469 */
470#define _CPU_Context_Get_SP( _context ) \
471  (_context)->o6_sp
472
473#endif /* ASM */
474
475/*
476 *  Offsets of fields with Context_Control for assembly routines.
477 */
478
479/** This macro defines an offset into the context for use in assembly. */
480#define G0_OFFSET    0x00
481/** This macro defines an offset into the context for use in assembly. */
482#define G1_OFFSET    0x04
483/** This macro defines an offset into the context for use in assembly. */
484#define G2_OFFSET    0x08
485/** This macro defines an offset into the context for use in assembly. */
486#define G3_OFFSET    0x0C
487/** This macro defines an offset into the context for use in assembly. */
488#define G4_OFFSET    0x10
489/** This macro defines an offset into the context for use in assembly. */
490#define G5_OFFSET    0x14
491/** This macro defines an offset into the context for use in assembly. */
492#define G6_OFFSET    0x18
493/** This macro defines an offset into the context for use in assembly. */
494#define G7_OFFSET    0x1C
495
496/** This macro defines an offset into the context for use in assembly. */
497#define L0_OFFSET    0x20
498/** This macro defines an offset into the context for use in assembly. */
499#define L1_OFFSET    0x24
500/** This macro defines an offset into the context for use in assembly. */
501#define L2_OFFSET    0x28
502/** This macro defines an offset into the context for use in assembly. */
503#define L3_OFFSET    0x2C
504/** This macro defines an offset into the context for use in assembly. */
505#define L4_OFFSET    0x30
506/** This macro defines an offset into the context for use in assembly. */
507#define L5_OFFSET    0x34
508/** This macro defines an offset into the context for use in assembly. */
509#define L6_OFFSET    0x38
510/** This macro defines an offset into the context for use in assembly. */
511#define L7_OFFSET    0x3C
512
513/** This macro defines an offset into the context for use in assembly. */
514#define I0_OFFSET    0x40
515/** This macro defines an offset into the context for use in assembly. */
516#define I1_OFFSET    0x44
517/** This macro defines an offset into the context for use in assembly. */
518#define I2_OFFSET    0x48
519/** This macro defines an offset into the context for use in assembly. */
520#define I3_OFFSET    0x4C
521/** This macro defines an offset into the context for use in assembly. */
522#define I4_OFFSET    0x50
523/** This macro defines an offset into the context for use in assembly. */
524#define I5_OFFSET    0x54
525/** This macro defines an offset into the context for use in assembly. */
526#define I6_FP_OFFSET 0x58
527/** This macro defines an offset into the context for use in assembly. */
528#define I7_OFFSET    0x5C
529
530/** This macro defines an offset into the context for use in assembly. */
531#define O0_OFFSET    0x60
532/** This macro defines an offset into the context for use in assembly. */
533#define O1_OFFSET    0x64
534/** This macro defines an offset into the context for use in assembly. */
535#define O2_OFFSET    0x68
536/** This macro defines an offset into the context for use in assembly. */
537#define O3_OFFSET    0x6C
538/** This macro defines an offset into the context for use in assembly. */
539#define O4_OFFSET    0x70
540/** This macro defines an offset into the context for use in assembly. */
541#define O5_OFFSET    0x74
542/** This macro defines an offset into the context for use in assembly. */
543#define O6_SP_OFFSET 0x78
544/** This macro defines an offset into the context for use in assembly. */
545#define O7_OFFSET    0x7C
546
547/** This macro defines an offset into the context for use in assembly. */
548#define PSR_OFFSET   0x80
549/** This macro defines an offset into the context for use in assembly. */
550#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
551
552/** This defines the size of the context area for use in assembly. */
553#define CONTEXT_CONTROL_SIZE 0x88
554
555#ifndef ASM
556/**
557 * @brief SPARC basic context.
558 *
559 * This structure defines floating point context area.
560 */
561typedef struct {
562  /** This will contain the contents of the f0 and f1 register. */
563  double      f0_f1;
564  /** This will contain the contents of the f2 and f3 register. */
565  double      f2_f3;
566  /** This will contain the contents of the f4 and f5 register. */
567  double      f4_f5;
568  /** This will contain the contents of the f6 and f7 register. */
569  double      f6_f7;
570  /** This will contain the contents of the f8 and f9 register. */
571  double      f8_f9;
572  /** This will contain the contents of the f10 and f11 register. */
573  double      f10_f11;
574  /** This will contain the contents of the f12 and f13 register. */
575  double      f12_f13;
576  /** This will contain the contents of the f14 and f15 register. */
577  double      f14_f15;
578  /** This will contain the contents of the f16 and f17 register. */
579  double      f16_f17;
580  /** This will contain the contents of the f18 and f19 register. */
581  double      f18_f19;
582  /** This will contain the contents of the f20 and f21 register. */
583  double      f20_f21;
584  /** This will contain the contents of the f22 and f23 register. */
585  double      f22_f23;
586  /** This will contain the contents of the f24 and f25 register. */
587  double      f24_f25;
588  /** This will contain the contents of the f26 and f27 register. */
589  double      f26_f27;
590  /** This will contain the contents of the f28 and f29 register. */
591  double      f28_f29;
592  /** This will contain the contents of the f30 and f31 register. */
593  double      f30_f31;
594  /** This will contain the contents of the floating point status register. */
595  uint32_t    fsr;
596} Context_Control_fp;
597
598#endif /* ASM */
599
600/*
601 *  Offsets of fields with Context_Control_fp for assembly routines.
602 */
603
604/** This macro defines an offset into the FPU context for use in assembly. */
605#define FO_F1_OFFSET     0x00
606/** This macro defines an offset into the FPU context for use in assembly. */
607#define F2_F3_OFFSET     0x08
608/** This macro defines an offset into the FPU context for use in assembly. */
609#define F4_F5_OFFSET     0x10
610/** This macro defines an offset into the FPU context for use in assembly. */
611#define F6_F7_OFFSET     0x18
612/** This macro defines an offset into the FPU context for use in assembly. */
613#define F8_F9_OFFSET     0x20
614/** This macro defines an offset into the FPU context for use in assembly. */
615#define F1O_F11_OFFSET   0x28
616/** This macro defines an offset into the FPU context for use in assembly. */
617#define F12_F13_OFFSET   0x30
618/** This macro defines an offset into the FPU context for use in assembly. */
619#define F14_F15_OFFSET   0x38
620/** This macro defines an offset into the FPU context for use in assembly. */
621#define F16_F17_OFFSET   0x40
622/** This macro defines an offset into the FPU context for use in assembly. */
623#define F18_F19_OFFSET   0x48
624/** This macro defines an offset into the FPU context for use in assembly. */
625#define F2O_F21_OFFSET   0x50
626/** This macro defines an offset into the FPU context for use in assembly. */
627#define F22_F23_OFFSET   0x58
628/** This macro defines an offset into the FPU context for use in assembly. */
629#define F24_F25_OFFSET   0x60
630/** This macro defines an offset into the FPU context for use in assembly. */
631#define F26_F27_OFFSET   0x68
632/** This macro defines an offset into the FPU context for use in assembly. */
633#define F28_F29_OFFSET   0x70
634/** This macro defines an offset into the FPU context for use in assembly. */
635#define F3O_F31_OFFSET   0x78
636/** This macro defines an offset into the FPU context for use in assembly. */
637#define FSR_OFFSET       0x80
638
639/** This defines the size of the FPU context area for use in assembly. */
640#define CONTEXT_CONTROL_FP_SIZE 0x84
641
642#ifndef ASM
643
644/** @} */
645
646/**
647 * @brief Interrupt stack frame (ISF).
648 *
649 * Context saved on stack for an interrupt.
650 *
651 * NOTE: The PSR, PC, and NPC are only saved in this structure for the
652 *       benefit of the user's handler.
653 */
654typedef struct {
655  /** On an interrupt, we must save the minimum stack frame. */
656  CPU_Minimum_stack_frame  Stack_frame;
657  /** This is the offset of the PSR on an ISF. */
658  uint32_t                 psr;
659  /** This is the offset of the XXX on an ISF. */
660  uint32_t                 pc;
661  /** This is the offset of the XXX on an ISF. */
662  uint32_t                 npc;
663  /** This is the offset of the g1 register on an ISF. */
664  uint32_t                 g1;
665  /** This is the offset of the g2 register on an ISF. */
666  uint32_t                 g2;
667  /** This is the offset of the g3 register on an ISF. */
668  uint32_t                 g3;
669  /** This is the offset of the g4 register on an ISF. */
670  uint32_t                 g4;
671  /** This is the offset of the g5 register on an ISF. */
672  uint32_t                 g5;
673  /** This is the offset of the g6 register on an ISF. */
674  uint32_t                 g6;
675  /** This is the offset of the g7 register on an ISF. */
676  uint32_t                 g7;
677  /** This is the offset of the i0 register on an ISF. */
678  uint32_t                 i0;
679  /** This is the offset of the i1 register on an ISF. */
680  uint32_t                 i1;
681  /** This is the offset of the i2 register on an ISF. */
682  uint32_t                 i2;
683  /** This is the offset of the i3 register on an ISF. */
684  uint32_t                 i3;
685  /** This is the offset of the i4 register on an ISF. */
686  uint32_t                 i4;
687  /** This is the offset of the i5 register on an ISF. */
688  uint32_t                 i5;
689  /** This is the offset of the i6 register on an ISF. */
690  uint32_t                 i6_fp;
691  /** This is the offset of the i7 register on an ISF. */
692  uint32_t                 i7;
693  /** This is the offset of the y register on an ISF. */
694  uint32_t                 y;
695  /** This is the offset of the tpc register on an ISF. */
696  uint32_t                 tpc;
697} CPU_Interrupt_frame;
698
699#endif /* ASM */
700
701/*
702 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
703 */
704
705/** This macro defines an offset into the ISF for use in assembly. */
706#define ISF_STACK_FRAME_OFFSET 0x00
707/** This macro defines an offset into the ISF for use in assembly. */
708#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
709/** This macro defines an offset into the ISF for use in assembly. */
710#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
711/** This macro defines an offset into the ISF for use in assembly. */
712#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
713/** This macro defines an offset into the ISF for use in assembly. */
714#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
715/** This macro defines an offset into the ISF for use in assembly. */
716#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
717/** This macro defines an offset into the ISF for use in assembly. */
718#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
719/** This macro defines an offset into the ISF for use in assembly. */
720#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
721/** This macro defines an offset into the ISF for use in assembly. */
722#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
723/** This macro defines an offset into the ISF for use in assembly. */
724#define ISF_G6_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
725/** This macro defines an offset into the ISF for use in assembly. */
726#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
727/** This macro defines an offset into the ISF for use in assembly. */
728#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
729/** This macro defines an offset into the ISF for use in assembly. */
730#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
731/** This macro defines an offset into the ISF for use in assembly. */
732#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
733/** This macro defines an offset into the ISF for use in assembly. */
734#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
735/** This macro defines an offset into the ISF for use in assembly. */
736#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
737/** This macro defines an offset into the ISF for use in assembly. */
738#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
739/** This macro defines an offset into the ISF for use in assembly. */
740#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
741/** This macro defines an offset into the ISF for use in assembly. */
742#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
743/** This macro defines an offset into the ISF for use in assembly. */
744#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
745/** This macro defines an offset into the ISF for use in assembly. */
746#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
747
748/** This defines the size of the ISF area for use in assembly. */
749#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \
750        CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
751
752#ifndef ASM
753/**
754 * This variable is contains the initialize context for the FP unit.
755 * It is filled in by _CPU_Initialize and copied into the task's FP
756 * context area during _CPU_Context_Initialize.
757 */
758SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
759
760/**
761 * This flag is context switched with each thread.  It indicates
762 * that THIS thread has an _ISR_Dispatch stack frame on its stack.
763 * By using this flag, we can avoid nesting more interrupt dispatching
764 * attempts on a previously interrupted thread's stack.
765 */
766SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
767
768/**
769 * The following type defines an entry in the SPARC's trap table.
770 *
771 * NOTE: The instructions chosen are RTEMS dependent although one is
772 *       obligated to use two of the four instructions to perform a
773 *       long jump.  The other instructions load one register with the
774 *       trap type (a.k.a. vector) and another with the psr.
775 */
776typedef struct {
777  /** This will contain a "mov %psr, %l0" instruction. */
778  uint32_t     mov_psr_l0;
779  /** This will contain a "sethi %hi(_handler), %l4" instruction. */
780  uint32_t     sethi_of_handler_to_l4;
781  /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */
782  uint32_t     jmp_to_low_of_handler_plus_l4;
783  /** This will contain a " mov _vector, %l3" instruction. */
784  uint32_t     mov_vector_l3;
785} CPU_Trap_table_entry;
786
787/**
788 * This is the set of opcodes for the instructions loaded into a trap
789 * table entry.  The routine which installs a handler is responsible
790 * for filling in the fields for the _handler address and the _vector
791 * trap type.
792 *
793 * The constants following this structure are masks for the fields which
794 * must be filled in when the handler is installed.
795 */
796extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
797
798/**
799 * The size of the floating point context area.
800 */
801#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
802
803#endif
804
805/**
806 * Amount of extra stack (above minimum stack size) required by
807 * MPCI receive server thread.  Remember that in a multiprocessor
808 * system this thread must exist and be able to process all directives.
809 */
810#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
811
812/**
813 * This defines the number of entries in the ISR_Vector_table managed
814 * by the executive.
815 *
816 * On the SPARC, there are really only 256 vectors.  However, the executive
817 * has no easy, fast, reliable way to determine which traps are synchronous
818 * and which are asynchronous.  By default, synchronous traps return to the
819 * instruction which caused the interrupt.  So if you install a software
820 * trap handler as an executive interrupt handler (which is desirable since
821 * RTEMS takes care of window and register issues), then the executive needs
822 * to know that the return address is to the trap rather than the instruction
823 * following the trap.
824 *
825 * So vectors 0 through 255 are treated as regular asynchronous traps which
826 * provide the "correct" return address.  Vectors 256 through 512 are assumed
827 * by the executive to be synchronous and to require that the return address
828 * be fudged.
829 *
830 * If you use this mechanism to install a trap handler which must reexecute
831 * the instruction which caused the trap, then it should be installed as
832 * an asynchronous trap.  This will avoid the executive changing the return
833 * address.
834 */
835#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
836
837/**
838 * The SPARC has 256 vectors but the port treats 256-512 as synchronous
839 * traps.
840 */
841#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
842
843/**
844 * This is the bit step in a vector number to indicate it is being installed
845 * as a synchronous trap.
846 */
847#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
848
849/**
850 * This macro indicates that @a _trap as an asynchronous trap.
851 */
852#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
853
854/**
855 * This macro indicates that @a _trap as a synchronous trap.
856 */
857#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
858
859/**
860 * This macro returns the real hardware vector number associated with @a _trap.
861 */
862#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
863
864/**
865 * This is defined if the port has a special way to report the ISR nesting
866 * level.  Most ports maintain the variable _ISR_Nest_level.
867 */
868#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
869
870/**
871 * Should be large enough to run all tests.  This ensures
872 * that a "reasonable" small application should not have any problems.
873 *
874 * This appears to be a fairly generous number for the SPARC since
875 * represents a call depth of about 20 routines based on the minimum
876 * stack frame.
877 */
878#define CPU_STACK_MINIMUM_SIZE  (1024*4)
879
880/**
881 * What is the size of a pointer on this architecture?
882 */
883#define CPU_SIZEOF_POINTER 4
884
885/**
886 * CPU's worst alignment requirement for data types on a byte boundary.  This
887 * alignment does not take into account the requirements for the stack.
888 *
889 * On the SPARC, this is required for double word loads and stores.
890 */
891#define CPU_ALIGNMENT      8
892
893/**
894 * This number corresponds to the byte alignment requirement for the
895 * heap handler.  This alignment requirement may be stricter than that
896 * for the data types alignment specified by CPU_ALIGNMENT.  It is
897 * common for the heap to follow the same alignment requirement as
898 * CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
899 * then this should be set to CPU_ALIGNMENT.
900 *
901 * NOTE:  This does not have to be a power of 2.  It does have to
902 *        be greater or equal to than CPU_ALIGNMENT.
903 */
904#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
905
906/**
907 * This number corresponds to the byte alignment requirement for memory
908 * buffers allocated by the partition manager.  This alignment requirement
909 * may be stricter than that for the data types alignment specified by
910 * CPU_ALIGNMENT.  It is common for the partition to follow the same
911 * alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
912 * enough for the partition, then this should be set to CPU_ALIGNMENT.
913 *
914 * NOTE:  This does not have to be a power of 2.  It does have to
915 *        be greater or equal to than CPU_ALIGNMENT.
916 */
917#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
918
919/**
920 * This number corresponds to the byte alignment requirement for the
921 * stack.  This alignment requirement may be stricter than that for the
922 * data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
923 * is strict enough for the stack, then this should be set to 0.
924 *
925 * NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
926 *
927 * The alignment restrictions for the SPARC are not that strict but this
928 * should unsure that the stack is always sufficiently alignment that the
929 * window overflow, underflow, and flush routines can use double word loads
930 * and stores.
931 */
932#define CPU_STACK_ALIGNMENT        16
933
934#ifndef ASM
935
936/*
937 *  ISR handler macros
938 */
939
940/**
941 * Support routine to initialize the RTEMS vector table after it is allocated.
942 */
943#define _CPU_Initialize_vectors()
944
945/**
946 * Disable all interrupts for a critical section.  The previous
947 * level is returned in _level.
948 */
949#define _CPU_ISR_Disable( _level ) \
950  (_level) = sparc_disable_interrupts()
951
952/**
953 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
954 * This indicates the end of a critical section.  The parameter
955 * _level is not modified.
956 */
957#define _CPU_ISR_Enable( _level ) \
958  sparc_enable_interrupts( _level )
959
960/**
961 * This temporarily restores the interrupt to _level before immediately
962 * disabling them again.  This is used to divide long critical
963 * sections into two or more parts.  The parameter _level is not
964 * modified.
965 */
966#define _CPU_ISR_Flash( _level ) \
967  sparc_flash_interrupts( _level )
968
969/**
970 * Map interrupt level in task mode onto the hardware that the CPU
971 * actually provides.  Currently, interrupt levels which do not
972 * map onto the CPU in a straight fashion are undefined.
973 */
974#define _CPU_ISR_Set_level( _newlevel ) \
975   sparc_enable_interrupts( _newlevel << 8)
976
977/**
978 * @brief Obtain the current interrupt disable level.
979 *
980 * This method is invoked to return the current interrupt disable level.
981 *
982 * @return This method returns the current interrupt disable level.
983 */
984uint32_t   _CPU_ISR_Get_level( void );
985
986/* end of ISR handler macros */
987
988/* Context handler macros */
989
990/**
991 * Initialize the context to a state suitable for starting a
992 * task after a context restore operation.  Generally, this
993 * involves:
994 *
995 * - setting a starting address
996 * - preparing the stack
997 * - preparing the stack and frame pointers
998 * - setting the proper interrupt level in the context
999 * - initializing the floating point context
1000 *
1001 * @param[in] the_context points to the context area
1002 * @param[in] stack_base is the low address of the allocated stack area
1003 * @param[in] size is the size of the stack area in bytes
1004 * @param[in] new_level is the interrupt level for the task
1005 * @param[in] entry_point is the task's entry point
1006 * @param[in] is_fp is set to TRUE if the task is a floating point task
1007 *
1008 * NOTE:  Implemented as a subroutine for the SPARC port.
1009 */
1010void _CPU_Context_Initialize(
1011  Context_Control  *the_context,
1012  uint32_t         *stack_base,
1013  uint32_t          size,
1014  uint32_t          new_level,
1015  void             *entry_point,
1016  bool              is_fp
1017);
1018
1019/**
1020 * This macro is invoked from _Thread_Handler to do whatever CPU
1021 * specific magic is required that must be done in the context of
1022 * the thread when it starts.
1023 *
1024 * On the SPARC, this is setting the frame pointer so GDB is happy.
1025 * Make GDB stop unwinding at _Thread_Handler, previous register window
1026 * Frame pointer is 0 and calling address must be a function with starting
1027 * with a SAVE instruction. If return address is leaf-function (no SAVE)
1028 * GDB will not look at prev reg window fp.
1029 *
1030 * _Thread_Handler is known to start with SAVE.
1031 */
1032#define _CPU_Context_Initialization_at_thread_begin() \
1033  do { \
1034    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
1035  } while (0)
1036
1037/**
1038 * This routine is responsible for somehow restarting the currently
1039 * executing task.
1040 *
1041 * On the SPARC, this is is relatively painless but requires a small
1042 * amount of wrapper code before using the regular restore code in
1043 * of the context switch.
1044 */
1045#define _CPU_Context_Restart_self( _the_context ) \
1046   _CPU_Context_restore( (_the_context) );
1047
1048/**
1049 * The FP context area for the SPARC is a simple structure and nothing
1050 * special is required to find the "starting load point"
1051 */
1052#define _CPU_Context_Fp_start( _base, _offset ) \
1053   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
1054
1055/**
1056 * This routine initializes the FP context area passed to it to.
1057 *
1058 * The SPARC allows us to use the simple initialization model
1059 * in which an "initial" FP context was saved into _CPU_Null_fp_context
1060 * at CPU initialization and it is simply copied into the destination
1061 * context.
1062 */
1063#define _CPU_Context_Initialize_fp( _destination ) \
1064  do { \
1065   *(*(_destination)) = _CPU_Null_fp_context; \
1066  } while (0)
1067
1068/* end of Context handler macros */
1069
1070/* Fatal Error manager macros */
1071
1072/**
1073 * This routine copies _error into a known place -- typically a stack
1074 * location or a register, optionally disables interrupts, and
1075 * halts/stops the CPU.
1076 */
1077#define _CPU_Fatal_halt( _error ) \
1078  do { \
1079    uint32_t   level; \
1080    \
1081    level = sparc_disable_interrupts(); \
1082    __asm__ volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
1083    while (1); /* loop forever */ \
1084  } while (0)
1085
1086/* end of Fatal Error manager macros */
1087
1088/* Bitfield handler macros */
1089
1090#if ( SPARC_HAS_BITSCAN == 0 )
1091  /**
1092   * The SPARC port uses the generic C algorithm for bitfield scan if the
1093   * CPU model does not have a scan instruction.
1094   */
1095  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1096  /**
1097   * The SPARC port uses the generic C algorithm for bitfield scan if the
1098   * CPU model does not have a scan instruction.  Thus is needs the generic
1099   * data table used by that algorithm.
1100   */
1101  #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1102#else
1103  #error "scan instruction not currently supported by RTEMS!!"
1104#endif
1105
1106/* end of Bitfield handler macros */
1107
1108/* functions */
1109
1110/**
1111 * @brief SPARC specific initialization.
1112 *
1113 * This routine performs CPU dependent initialization.
1114 */
1115void _CPU_Initialize(void);
1116
1117/**
1118 * @brief SPARC specific raw ISR installer.
1119 *
1120 * This routine installs @a new_handler to be directly called from the trap
1121 * table.
1122 *
1123 * @param[in] vector is the vector number
1124 * @param[in] new_handler is the new ISR handler
1125 * @param[in] old_handler will contain the old ISR handler
1126 */
1127void _CPU_ISR_install_raw_handler(
1128  uint32_t    vector,
1129  proc_ptr    new_handler,
1130  proc_ptr   *old_handler
1131);
1132
1133/**
1134 * @brief SPARC specific RTEMS ISR installer.
1135 *
1136 * This routine installs an interrupt vector.
1137 *
1138 * @param[in] vector is the vector number
1139 * @param[in] new_handler is the new ISR handler
1140 * @param[in] old_handler will contain the old ISR handler
1141 */
1142
1143void _CPU_ISR_install_vector(
1144  uint32_t    vector,
1145  proc_ptr    new_handler,
1146  proc_ptr   *old_handler
1147);
1148
1149/**
1150 * @brief SPARC specific context switch.
1151 *
1152 * This routine switches from the run context to the heir context.
1153 *
1154 * @param[in] run is the currently executing thread
1155 * @param[in] heir will become the currently executing thread
1156 */
1157void _CPU_Context_switch(
1158  Context_Control  *run,
1159  Context_Control  *heir
1160);
1161
1162/**
1163 * @brief SPARC specific context restore.
1164 *
1165 * This routine is generally used only to restart self in an
1166 * efficient manner.
1167 *
1168 * @param[in] new_context is the context to restore
1169 */
1170void _CPU_Context_restore(
1171  Context_Control *new_context
1172) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1173
1174#if defined(RTEMS_SMP)
1175  /**
1176   * @brief SPARC specific method to switch to first task.
1177   *
1178   * This routine is only used to switch to the first task on a
1179   * secondary core in an SMP configuration.  We do not need to
1180   * flush all the windows and, in fact, this can be dangerous
1181   * as they may or may not be initialized properly.
1182   *
1183   * @param[in] new_context is the context to restore
1184   */
1185  void _CPU_Context_switch_to_first_task_smp(
1186    Context_Control *new_context
1187  );
1188
1189  /**
1190   * Macro to access memory and bypass the cache.
1191   *
1192   * NOTE: address space 1 is uncacheable
1193   */
1194  #define SMP_CPU_SWAP( _address, _value, _previous ) \
1195    do { \
1196      register unsigned int _val = _value; \
1197      asm volatile( \
1198        "swapa [%2] %3, %0" : \
1199        "=r" (_val) : \
1200        "0" (_val), \
1201        "r" (_address), \
1202        "i" (1) \
1203      ); \
1204      _previous = _val; \
1205    } while (0)
1206
1207  static inline void _CPU_Processor_event_broadcast( void )
1208  {
1209    __asm__ volatile ( "" : : : "memory" );
1210  }
1211
1212  static inline void _CPU_Processor_event_receive( void )
1213  {
1214    __asm__ volatile ( "" : : : "memory" );
1215  }
1216#endif
1217
1218/**
1219 * @brief SPARC specific save FPU method.
1220 *
1221 * This routine saves the floating point context passed to it.
1222 *
1223 * @param[in] fp_context_ptr is the area to save into
1224 */
1225void _CPU_Context_save_fp(
1226  Context_Control_fp **fp_context_ptr
1227);
1228
1229/**
1230 * @brief SPARC specific restore FPU method.
1231 *
1232 * This routine restores the floating point context passed to it.
1233 *
1234 * @param[in] fp_context_ptr is the area to restore from
1235 */
1236void _CPU_Context_restore_fp(
1237  Context_Control_fp **fp_context_ptr
1238);
1239
1240static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1241{
1242  /* TODO */
1243}
1244
1245static inline void _CPU_Context_validate( uintptr_t pattern )
1246{
1247  while (1) {
1248    /* TODO */
1249  }
1250}
1251
1252typedef struct {
1253  uint32_t trap;
1254  CPU_Interrupt_frame *isf;
1255} CPU_Exception_frame;
1256
1257void _BSP_Exception_frame_print( const CPU_Exception_frame *frame );
1258
1259static inline void _CPU_Exception_frame_print(
1260  const CPU_Exception_frame *frame
1261)
1262{
1263  _BSP_Exception_frame_print( frame );
1264}
1265
1266/**
1267 * @brief SPARC specific method to endian swap an uint32_t.
1268 *
1269 * The following routine swaps the endian format of an unsigned int.
1270 * It must be static because it is referenced indirectly.
1271 *
1272 * @param[in] value is the value to endian swap
1273 *
1274 * This version will work on any processor, but if you come across a better
1275 * way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
1276 * entity as shown below is not any more efficient on the SPARC.
1277 *
1278 *    - swap least significant two bytes with 16-bit rotate
1279 *    - swap upper and lower 16-bits
1280 *    - swap most significant two bytes with 16-bit rotate
1281 *
1282 * It is not obvious how the SPARC can do significantly better than the
1283 * generic code.  gcc 2.7.0 only generates about 12 instructions for the
1284 * following code at optimization level four (i.e. -O4).
1285 */
1286static inline uint32_t CPU_swap_u32(
1287  uint32_t value
1288)
1289{
1290  uint32_t   byte1, byte2, byte3, byte4, swapped;
1291
1292  byte4 = (value >> 24) & 0xff;
1293  byte3 = (value >> 16) & 0xff;
1294  byte2 = (value >> 8)  & 0xff;
1295  byte1 =  value        & 0xff;
1296
1297  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1298  return( swapped );
1299}
1300
1301/**
1302 * @brief SPARC specific method to endian swap an uint16_t.
1303 *
1304 * The following routine swaps the endian format of a uint16_t.
1305 *
1306 * @param[in] value is the value to endian swap
1307 */
1308#define CPU_swap_u16( value ) \
1309  (((value&0xff) << 8) | ((value >> 8)&0xff))
1310
1311#endif /* ASM */
1312
1313#ifdef __cplusplus
1314}
1315#endif
1316
1317#endif
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