source: rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h @ 27bfcd8

5
Last change on this file since 27bfcd8 was 27bfcd8, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 25, 2017 at 1:32:02 PM

score: Delete _CPU_Context_Fp_start()

Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().

Close #1400.

  • Property mode set to 100644
File size: 40.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief SPARC CPU Department Source
5 *
6 * This include file contains information pertaining to the port of
7 * the executive to the SPARC processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/sparc.h>
28
29/* conditional compilation parameters */
30
31#if defined(RTEMS_SMP)
32  /*
33   * The SPARC ABI is a bit special with respect to the floating point context.
34   * The complete floating point context is volatile.  Thus from an ABI point
35   * of view nothing needs to be saved and restored during a context switch.
36   * Instead the floating point context must be saved and restored during
37   * interrupt processing.  Historically the deferred floating point switch is
38   * used for SPARC and the complete floating point context is saved and
39   * restored during a context switch to the new floating point unit owner.
40   * This is a bit dangerous since post-switch actions (e.g. signal handlers)
41   * and context switch extensions may silently corrupt the floating point
42   * context.  The floating point unit is disabled for interrupt handlers.
43   * Thus in case an interrupt handler uses the floating point unit then this
44   * will result in a trap.
45   *
46   * On SMP configurations the deferred floating point switch is not
47   * supported in principle.  So use here a safe floating point support.  Safe
48   * means that the volatile floating point context is saved and restored
49   * around a thread dispatch issued during interrupt processing.  Thus
50   * post-switch actions and context switch extensions may safely use the
51   * floating point unit.
52   */
53  #define SPARC_USE_SAFE_FP_SUPPORT
54#endif
55
56/**
57 * Does the executive manage a dedicated interrupt stack in software?
58 *
59 * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
60 * If FALSE, nothing is done.
61 *
62 * The SPARC does not have a dedicated HW interrupt stack and one has
63 * been implemented in SW.
64 */
65#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
66
67/**
68 * Does the CPU follow the simple vectored interrupt model?
69 *
70 * - If TRUE, then RTEMS allocates the vector table it internally manages.
71 * - If FALSE, then the BSP is assumed to allocate and manage the vector
72 *   table
73 *
74 * THe SPARC is a simple vectored architecture.  Usually there is no
75 * PIC and the CPU directly vectors the interrupts.
76 */
77#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
78
79/**
80 * Does this CPU have hardware support for a dedicated interrupt stack?
81 *
82 * - If TRUE, then it must be installed during initialization.
83 * - If FALSE, then no installation is performed.
84 *
85 * The SPARC does not have a dedicated HW interrupt stack.
86 */
87#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
88
89/**
90 * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
91 *
92 * - If TRUE, then the memory is allocated during initialization.
93 * - If FALSE, then the memory is allocated during initialization.
94 *
95 * The SPARC does not have hardware support for switching to a
96 * dedicated interrupt stack.  The port includes support for doing this
97 * in software.
98 *
99 */
100#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
101
102/**
103 * Does the RTEMS invoke the user's ISR with the vector number and
104 * a pointer to the saved interrupt frame (1) or just the vector
105 * number (0)?
106 *
107 * The SPARC port does not pass an Interrupt Stack Frame pointer to
108 * interrupt handlers.
109 */
110#define CPU_ISR_PASSES_FRAME_POINTER FALSE
111
112/**
113 * Does the CPU have hardware floating point?
114 *
115 * - If TRUE, then the FLOATING_POINT task attribute is supported.
116 * - If FALSE, then the FLOATING_POINT task attribute is ignored.
117 *
118 * This is set based upon the multilib settings.
119 */
120#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SAFE_FP_SUPPORT)
121  #define CPU_HARDWARE_FP     TRUE
122#else
123  #define CPU_HARDWARE_FP     FALSE
124#endif
125
126/**
127 * The SPARC GCC port does not have a software floating point library
128 * that requires RTEMS assistance.
129 */
130#define CPU_SOFTWARE_FP     FALSE
131
132/**
133 * Are all tasks FLOATING_POINT tasks implicitly?
134 *
135 * - If TRUE, then the FLOATING_POINT task attribute is assumed.
136 * - If FALSE, then the FLOATING_POINT task attribute is followed.
137 *
138 * The SPARC GCC port does not implicitly use floating point registers.
139 */
140#define CPU_ALL_TASKS_ARE_FP     FALSE
141
142/**
143 * Should the IDLE task have a floating point context?
144 *
145 * - If TRUE, then the IDLE task is created as a FLOATING_POINT task
146 *   and it has a floating point context which is switched in and out.
147 * - If FALSE, then the IDLE task does not have a floating point context.
148 *
149 * The IDLE task does not have to be floating point on the SPARC.
150 */
151#define CPU_IDLE_TASK_IS_FP      FALSE
152
153/**
154 * Should the saving of the floating point registers be deferred
155 * until a context switch is made to another different floating point
156 * task?
157 *
158 * - If TRUE, then the floating point context will not be stored until
159 * necessary.  It will remain in the floating point registers and not
160 * disturned until another floating point task is switched to.
161 *
162 * - If FALSE, then the floating point context is saved when a floating
163 * point task is switched out and restored when the next floating point
164 * task is restored.  The state of the floating point registers between
165 * those two operations is not specified.
166 *
167 * On the SPARC, we can disable the FPU for integer only tasks so
168 * it is safe to defer floating point context switches.
169 */
170#if defined(SPARC_USE_SAFE_FP_SUPPORT)
171  #define CPU_USE_DEFERRED_FP_SWITCH FALSE
172#else
173  #define CPU_USE_DEFERRED_FP_SWITCH TRUE
174#endif
175
176#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
177
178/**
179 * Does this port provide a CPU dependent IDLE task implementation?
180 *
181 * - If TRUE, then the routine _CPU_Thread_Idle_body
182 * must be provided and is the default IDLE thread body instead of
183 * _CPU_Thread_Idle_body.
184 *
185 * - If FALSE, then use the generic IDLE thread body if the BSP does
186 * not provide one.
187 *
188 * The SPARC architecture does not have a low power or halt instruction.
189 * It is left to the BSP and/or CPU specific code to provide an IDLE
190 * thread body which is aware of low power modes.
191 */
192#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
193
194/**
195 * Does the stack grow up (toward higher addresses) or down
196 * (toward lower addresses)?
197 *
198 * - If TRUE, then the grows upward.
199 * - If FALSE, then the grows toward smaller addresses.
200 *
201 * The stack grows to lower addresses on the SPARC.
202 */
203#define CPU_STACK_GROWS_UP               FALSE
204
205/* LEON3 systems may use a cache line size of 64 */
206#define CPU_CACHE_LINE_BYTES 64
207
208#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
209
210/**
211 * The following defines the number of bits actually used in the
212 * interrupt field of the task mode.  How those bits map to the
213 * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
214 *
215 * The SPARC has 16 interrupt levels in the PIL field of the PSR.
216 */
217#define CPU_MODES_INTERRUPT_MASK   0x0000000F
218
219#ifndef ASM
220/**
221 * This structure represents the organization of the minimum stack frame
222 * for the SPARC.  More framing information is required in certain situaions
223 * such as when there are a large number of out parameters or when the callee
224 * must save floating point registers.
225 */
226typedef struct {
227  /** This is the offset of the l0 register. */
228  uint32_t    l0;
229  /** This is the offset of the l1 register. */
230  uint32_t    l1;
231  /** This is the offset of the l2 register. */
232  uint32_t    l2;
233  /** This is the offset of the l3 register. */
234  uint32_t    l3;
235  /** This is the offset of the l4 register. */
236  uint32_t    l4;
237  /** This is the offset of the l5 register. */
238  uint32_t    l5;
239  /** This is the offset of the l6 register. */
240  uint32_t    l6;
241  /** This is the offset of the l7 register. */
242  uint32_t    l7;
243  /** This is the offset of the l0 register. */
244  uint32_t    i0;
245  /** This is the offset of the i1 register. */
246  uint32_t    i1;
247  /** This is the offset of the i2 register. */
248  uint32_t    i2;
249  /** This is the offset of the i3 register. */
250  uint32_t    i3;
251  /** This is the offset of the i4 register. */
252  uint32_t    i4;
253  /** This is the offset of the i5 register. */
254  uint32_t    i5;
255  /** This is the offset of the i6 register. */
256  uint32_t    i6_fp;
257  /** This is the offset of the i7 register. */
258  uint32_t    i7;
259  /** This is the offset of the register used to return structures. */
260  void       *structure_return_address;
261
262  /*
263   * The following are for the callee to save the register arguments in
264   * should this be necessary.
265   */
266  /** This is the offset of the register for saved argument 0. */
267  uint32_t    saved_arg0;
268  /** This is the offset of the register for saved argument 1. */
269  uint32_t    saved_arg1;
270  /** This is the offset of the register for saved argument 2. */
271  uint32_t    saved_arg2;
272  /** This is the offset of the register for saved argument 3. */
273  uint32_t    saved_arg3;
274  /** This is the offset of the register for saved argument 4. */
275  uint32_t    saved_arg4;
276  /** This is the offset of the register for saved argument 5. */
277  uint32_t    saved_arg5;
278  /** This field pads the structure so ldd and std instructions can be used. */
279  uint32_t    pad0;
280} SPARC_Minimum_stack_frame;
281
282#endif /* ASM */
283
284/** This macro defines an offset into the stack frame for use in assembly. */
285#define CPU_STACK_FRAME_L0_OFFSET             0x00
286/** This macro defines an offset into the stack frame for use in assembly. */
287#define CPU_STACK_FRAME_L1_OFFSET             0x04
288/** This macro defines an offset into the stack frame for use in assembly. */
289#define CPU_STACK_FRAME_L2_OFFSET             0x08
290/** This macro defines an offset into the stack frame for use in assembly. */
291#define CPU_STACK_FRAME_L3_OFFSET             0x0c
292/** This macro defines an offset into the stack frame for use in assembly. */
293#define CPU_STACK_FRAME_L4_OFFSET             0x10
294/** This macro defines an offset into the stack frame for use in assembly. */
295#define CPU_STACK_FRAME_L5_OFFSET             0x14
296/** This macro defines an offset into the stack frame for use in assembly. */
297#define CPU_STACK_FRAME_L6_OFFSET             0x18
298/** This macro defines an offset into the stack frame for use in assembly. */
299#define CPU_STACK_FRAME_L7_OFFSET             0x1c
300/** This macro defines an offset into the stack frame for use in assembly. */
301#define CPU_STACK_FRAME_I0_OFFSET             0x20
302/** This macro defines an offset into the stack frame for use in assembly. */
303#define CPU_STACK_FRAME_I1_OFFSET             0x24
304/** This macro defines an offset into the stack frame for use in assembly. */
305#define CPU_STACK_FRAME_I2_OFFSET             0x28
306/** This macro defines an offset into the stack frame for use in assembly. */
307#define CPU_STACK_FRAME_I3_OFFSET             0x2c
308/** This macro defines an offset into the stack frame for use in assembly. */
309#define CPU_STACK_FRAME_I4_OFFSET             0x30
310/** This macro defines an offset into the stack frame for use in assembly. */
311#define CPU_STACK_FRAME_I5_OFFSET             0x34
312/** This macro defines an offset into the stack frame for use in assembly. */
313#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38
314/** This macro defines an offset into the stack frame for use in assembly. */
315#define CPU_STACK_FRAME_I7_OFFSET             0x3c
316/** This macro defines an offset into the stack frame for use in assembly. */
317#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40
318/** This macro defines an offset into the stack frame for use in assembly. */
319#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44
320/** This macro defines an offset into the stack frame for use in assembly. */
321#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48
322/** This macro defines an offset into the stack frame for use in assembly. */
323#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c
324/** This macro defines an offset into the stack frame for use in assembly. */
325#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50
326/** This macro defines an offset into the stack frame for use in assembly. */
327#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54
328/** This macro defines an offset into the stack frame for use in assembly. */
329#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58
330/** This macro defines an offset into the stack frame for use in assembly. */
331#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c
332
333#define CPU_MAXIMUM_PROCESSORS 32
334
335/**
336 * @defgroup Contexts SPARC Context Structures
337 *
338 * @ingroup Score
339 *
340 * Generally there are 2 types of context to save.
341 *    + Interrupt registers to save
342 *    + Task level registers to save
343 *
344 * This means we have the following 3 context items:
345 *    + task level context stuff::  Context_Control
346 *    + floating point task stuff:: Context_Control_fp
347 *    + special interrupt level context :: Context_Control_interrupt
348 *
349 * On the SPARC, we are relatively conservative in that we save most
350 * of the CPU state in the context area.  The ET (enable trap) bit and
351 * the CWP (current window pointer) fields of the PSR are considered
352 * system wide resources and are not maintained on a per-thread basis.
353 */
354/**@{**/
355
356#ifndef ASM
357
358/**
359 * @brief SPARC basic context.
360 *
361 * This structure defines the non-volatile integer and processor state context
362 * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY
363 * INTERFACE - SPARC Processor Supplement", Third Edition.
364 *
365 * The registers g2 through g4 are reserved for applications.  GCC uses them as
366 * volatile registers by default.  So they are treated like volatile registers
367 * in RTEMS as well.
368 *
369 * The register g6 contains the per-CPU control of the current processor.  It
370 * is an invariant of the processor context.  This register must not be saved
371 * and restored during context switches or interrupt services.
372 */
373typedef struct {
374  /** This will contain the contents of the g5 register. */
375  uint32_t   g5;
376  /** This will contain the contents of the g7 register. */
377  uint32_t   g7;
378
379  /**
380   * This will contain the contents of the l0 and l1 registers.
381   *
382   * Using a double l0_and_l1 will put everything in this structure on a double
383   * word boundary which allows us to use double word loads and stores safely
384   * in the context switch.
385   */
386  double     l0_and_l1;
387  /** This will contain the contents of the l2 register. */
388  uint32_t   l2;
389  /** This will contain the contents of the l3 register. */
390  uint32_t   l3;
391  /** This will contain the contents of the l4 register. */
392  uint32_t   l4;
393  /** This will contain the contents of the l5 registeer.*/
394  uint32_t   l5;
395  /** This will contain the contents of the l6 register. */
396  uint32_t   l6;
397  /** This will contain the contents of the l7 register. */
398  uint32_t   l7;
399
400  /** This will contain the contents of the i0 register. */
401  uint32_t   i0;
402  /** This will contain the contents of the i1 register. */
403  uint32_t   i1;
404  /** This will contain the contents of the i2 register. */
405  uint32_t   i2;
406  /** This will contain the contents of the i3 register. */
407  uint32_t   i3;
408  /** This will contain the contents of the i4 register. */
409  uint32_t   i4;
410  /** This will contain the contents of the i5 register. */
411  uint32_t   i5;
412  /** This will contain the contents of the i6 (e.g. frame pointer) register. */
413  uint32_t   i6_fp;
414  /** This will contain the contents of the i7 register. */
415  uint32_t   i7;
416
417  /** This will contain the contents of the o6 (e.g. frame pointer) register. */
418  uint32_t   o6_sp;
419  /**
420   * This will contain the contents of the o7 (e.g. address of CALL
421   * instruction) register.
422   */
423  uint32_t   o7;
424
425  /** This will contain the contents of the processor status register. */
426  uint32_t   psr;
427  /**
428   * This field is used to prevent heavy nesting of calls to _Thread_Dispatch
429   * on an interrupted  task's stack.  This is problematic on the slower
430   * SPARC CPU models at high interrupt rates.
431   */
432  uint32_t   isr_dispatch_disable;
433
434#if defined(RTEMS_SMP)
435  volatile uint32_t is_executing;
436#endif
437} Context_Control;
438
439/**
440 * This macro provides a CPU independent way for RTEMS to access the
441 * stack pointer in a context structure. The actual name and offset is
442 * CPU architecture dependent.
443 */
444#define _CPU_Context_Get_SP( _context ) \
445  (_context)->o6_sp
446
447#ifdef RTEMS_SMP
448  static inline bool _CPU_Context_Get_is_executing(
449    const Context_Control *context
450  )
451  {
452    return context->is_executing;
453  }
454
455  static inline void _CPU_Context_Set_is_executing(
456    Context_Control *context,
457    bool is_executing
458  )
459  {
460    context->is_executing = is_executing;
461  }
462#endif
463
464#endif /* ASM */
465
466/*
467 *  Offsets of fields with Context_Control for assembly routines.
468 */
469
470/** This macro defines an offset into the context for use in assembly. */
471#define G5_OFFSET    0x00
472/** This macro defines an offset into the context for use in assembly. */
473#define G7_OFFSET    0x04
474
475/** This macro defines an offset into the context for use in assembly. */
476#define L0_OFFSET    0x08
477/** This macro defines an offset into the context for use in assembly. */
478#define L1_OFFSET    0x0C
479/** This macro defines an offset into the context for use in assembly. */
480#define L2_OFFSET    0x10
481/** This macro defines an offset into the context for use in assembly. */
482#define L3_OFFSET    0x14
483/** This macro defines an offset into the context for use in assembly. */
484#define L4_OFFSET    0x18
485/** This macro defines an offset into the context for use in assembly. */
486#define L5_OFFSET    0x1C
487/** This macro defines an offset into the context for use in assembly. */
488#define L6_OFFSET    0x20
489/** This macro defines an offset into the context for use in assembly. */
490#define L7_OFFSET    0x24
491
492/** This macro defines an offset into the context for use in assembly. */
493#define I0_OFFSET    0x28
494/** This macro defines an offset into the context for use in assembly. */
495#define I1_OFFSET    0x2C
496/** This macro defines an offset into the context for use in assembly. */
497#define I2_OFFSET    0x30
498/** This macro defines an offset into the context for use in assembly. */
499#define I3_OFFSET    0x34
500/** This macro defines an offset into the context for use in assembly. */
501#define I4_OFFSET    0x38
502/** This macro defines an offset into the context for use in assembly. */
503#define I5_OFFSET    0x3C
504/** This macro defines an offset into the context for use in assembly. */
505#define I6_FP_OFFSET 0x40
506/** This macro defines an offset into the context for use in assembly. */
507#define I7_OFFSET    0x44
508
509/** This macro defines an offset into the context for use in assembly. */
510#define O6_SP_OFFSET 0x48
511/** This macro defines an offset into the context for use in assembly. */
512#define O7_OFFSET    0x4C
513
514/** This macro defines an offset into the context for use in assembly. */
515#define PSR_OFFSET   0x50
516/** This macro defines an offset into the context for use in assembly. */
517#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54
518
519#if defined(RTEMS_SMP)
520  #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
521#endif
522
523#ifndef ASM
524/**
525 * @brief SPARC basic context.
526 *
527 * This structure defines floating point context area.
528 */
529typedef struct {
530  /** This will contain the contents of the f0 and f1 register. */
531  double      f0_f1;
532  /** This will contain the contents of the f2 and f3 register. */
533  double      f2_f3;
534  /** This will contain the contents of the f4 and f5 register. */
535  double      f4_f5;
536  /** This will contain the contents of the f6 and f7 register. */
537  double      f6_f7;
538  /** This will contain the contents of the f8 and f9 register. */
539  double      f8_f9;
540  /** This will contain the contents of the f10 and f11 register. */
541  double      f10_f11;
542  /** This will contain the contents of the f12 and f13 register. */
543  double      f12_f13;
544  /** This will contain the contents of the f14 and f15 register. */
545  double      f14_f15;
546  /** This will contain the contents of the f16 and f17 register. */
547  double      f16_f17;
548  /** This will contain the contents of the f18 and f19 register. */
549  double      f18_f19;
550  /** This will contain the contents of the f20 and f21 register. */
551  double      f20_f21;
552  /** This will contain the contents of the f22 and f23 register. */
553  double      f22_f23;
554  /** This will contain the contents of the f24 and f25 register. */
555  double      f24_f25;
556  /** This will contain the contents of the f26 and f27 register. */
557  double      f26_f27;
558  /** This will contain the contents of the f28 and f29 register. */
559  double      f28_f29;
560  /** This will contain the contents of the f30 and f31 register. */
561  double      f30_f31;
562  /** This will contain the contents of the floating point status register. */
563  uint32_t    fsr;
564} Context_Control_fp;
565
566#endif /* ASM */
567
568/*
569 *  Offsets of fields with Context_Control_fp for assembly routines.
570 */
571
572/** This macro defines an offset into the FPU context for use in assembly. */
573#define FO_F1_OFFSET     0x00
574/** This macro defines an offset into the FPU context for use in assembly. */
575#define F2_F3_OFFSET     0x08
576/** This macro defines an offset into the FPU context for use in assembly. */
577#define F4_F5_OFFSET     0x10
578/** This macro defines an offset into the FPU context for use in assembly. */
579#define F6_F7_OFFSET     0x18
580/** This macro defines an offset into the FPU context for use in assembly. */
581#define F8_F9_OFFSET     0x20
582/** This macro defines an offset into the FPU context for use in assembly. */
583#define F1O_F11_OFFSET   0x28
584/** This macro defines an offset into the FPU context for use in assembly. */
585#define F12_F13_OFFSET   0x30
586/** This macro defines an offset into the FPU context for use in assembly. */
587#define F14_F15_OFFSET   0x38
588/** This macro defines an offset into the FPU context for use in assembly. */
589#define F16_F17_OFFSET   0x40
590/** This macro defines an offset into the FPU context for use in assembly. */
591#define F18_F19_OFFSET   0x48
592/** This macro defines an offset into the FPU context for use in assembly. */
593#define F2O_F21_OFFSET   0x50
594/** This macro defines an offset into the FPU context for use in assembly. */
595#define F22_F23_OFFSET   0x58
596/** This macro defines an offset into the FPU context for use in assembly. */
597#define F24_F25_OFFSET   0x60
598/** This macro defines an offset into the FPU context for use in assembly. */
599#define F26_F27_OFFSET   0x68
600/** This macro defines an offset into the FPU context for use in assembly. */
601#define F28_F29_OFFSET   0x70
602/** This macro defines an offset into the FPU context for use in assembly. */
603#define F3O_F31_OFFSET   0x78
604/** This macro defines an offset into the FPU context for use in assembly. */
605#define FSR_OFFSET       0x80
606
607/** This defines the size of the FPU context area for use in assembly. */
608#define CONTEXT_CONTROL_FP_SIZE 0x84
609
610#ifndef ASM
611
612/** @} */
613
614/**
615 * @brief Interrupt stack frame (ISF).
616 *
617 * Context saved on stack for an interrupt.
618 *
619 * NOTE: The PSR, PC, and NPC are only saved in this structure for the
620 *       benefit of the user's handler.
621 */
622typedef struct {
623  /** On an interrupt, we must save the minimum stack frame. */
624  SPARC_Minimum_stack_frame Stack_frame;
625  /** This is the offset of the PSR on an ISF. */
626  uint32_t                 psr;
627  /** This is the offset of the XXX on an ISF. */
628  uint32_t                 pc;
629  /** This is the offset of the XXX on an ISF. */
630  uint32_t                 npc;
631  /** This is the offset of the g1 register on an ISF. */
632  uint32_t                 g1;
633  /** This is the offset of the g2 register on an ISF. */
634  uint32_t                 g2;
635  /** This is the offset of the g3 register on an ISF. */
636  uint32_t                 g3;
637  /** This is the offset of the g4 register on an ISF. */
638  uint32_t                 g4;
639  /** This is the offset of the g5 register on an ISF. */
640  uint32_t                 g5;
641  /** This is the offset is reserved for alignment on an ISF. */
642  uint32_t                 reserved_for_alignment;
643  /** This is the offset of the g7 register on an ISF. */
644  uint32_t                 g7;
645  /** This is the offset of the i0 register on an ISF. */
646  uint32_t                 i0;
647  /** This is the offset of the i1 register on an ISF. */
648  uint32_t                 i1;
649  /** This is the offset of the i2 register on an ISF. */
650  uint32_t                 i2;
651  /** This is the offset of the i3 register on an ISF. */
652  uint32_t                 i3;
653  /** This is the offset of the i4 register on an ISF. */
654  uint32_t                 i4;
655  /** This is the offset of the i5 register on an ISF. */
656  uint32_t                 i5;
657  /** This is the offset of the i6 register on an ISF. */
658  uint32_t                 i6_fp;
659  /** This is the offset of the i7 register on an ISF. */
660  uint32_t                 i7;
661  /** This is the offset of the y register on an ISF. */
662  uint32_t                 y;
663  /** This is the offset of the tpc register on an ISF. */
664  uint32_t                 tpc;
665} CPU_Interrupt_frame;
666
667#endif /* ASM */
668
669#ifndef ASM
670/**
671 * This variable is contains the initialize context for the FP unit.
672 * It is filled in by _CPU_Initialize and copied into the task's FP
673 * context area during _CPU_Context_Initialize.
674 */
675extern Context_Control_fp _CPU_Null_fp_context;
676
677/**
678 * The following type defines an entry in the SPARC's trap table.
679 *
680 * NOTE: The instructions chosen are RTEMS dependent although one is
681 *       obligated to use two of the four instructions to perform a
682 *       long jump.  The other instructions load one register with the
683 *       trap type (a.k.a. vector) and another with the psr.
684 */
685typedef struct {
686  /** This will contain a "mov %psr, %l0" instruction. */
687  uint32_t     mov_psr_l0;
688  /** This will contain a "sethi %hi(_handler), %l4" instruction. */
689  uint32_t     sethi_of_handler_to_l4;
690  /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */
691  uint32_t     jmp_to_low_of_handler_plus_l4;
692  /** This will contain a " mov _vector, %l3" instruction. */
693  uint32_t     mov_vector_l3;
694} CPU_Trap_table_entry;
695
696/**
697 * This is the set of opcodes for the instructions loaded into a trap
698 * table entry.  The routine which installs a handler is responsible
699 * for filling in the fields for the _handler address and the _vector
700 * trap type.
701 *
702 * The constants following this structure are masks for the fields which
703 * must be filled in when the handler is installed.
704 */
705extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
706
707/**
708 * The size of the floating point context area.
709 */
710#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
711
712#endif
713
714/**
715 * Amount of extra stack (above minimum stack size) required by
716 * MPCI receive server thread.  Remember that in a multiprocessor
717 * system this thread must exist and be able to process all directives.
718 */
719#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
720
721/**
722 * This defines the number of entries in the ISR_Vector_table managed
723 * by the executive.
724 *
725 * On the SPARC, there are really only 256 vectors.  However, the executive
726 * has no easy, fast, reliable way to determine which traps are synchronous
727 * and which are asynchronous.  By default, synchronous traps return to the
728 * instruction which caused the interrupt.  So if you install a software
729 * trap handler as an executive interrupt handler (which is desirable since
730 * RTEMS takes care of window and register issues), then the executive needs
731 * to know that the return address is to the trap rather than the instruction
732 * following the trap.
733 *
734 * So vectors 0 through 255 are treated as regular asynchronous traps which
735 * provide the "correct" return address.  Vectors 256 through 512 are assumed
736 * by the executive to be synchronous and to require that the return address
737 * be fudged.
738 *
739 * If you use this mechanism to install a trap handler which must reexecute
740 * the instruction which caused the trap, then it should be installed as
741 * an asynchronous trap.  This will avoid the executive changing the return
742 * address.
743 */
744#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
745
746/**
747 * The SPARC has 256 vectors but the port treats 256-512 as synchronous
748 * traps.
749 */
750#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
751
752/**
753 * This is the bit step in a vector number to indicate it is being installed
754 * as a synchronous trap.
755 */
756#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
757
758/**
759 * This macro indicates that @a _trap as an asynchronous trap.
760 */
761#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
762
763/**
764 * This macro indicates that @a _trap as a synchronous trap.
765 */
766#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
767
768/**
769 * This macro returns the real hardware vector number associated with @a _trap.
770 */
771#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
772
773/**
774 * This is defined if the port has a special way to report the ISR nesting
775 * level.  Most ports maintain the variable _ISR_Nest_level.
776 */
777#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
778
779/**
780 * Should be large enough to run all tests.  This ensures
781 * that a "reasonable" small application should not have any problems.
782 *
783 * This appears to be a fairly generous number for the SPARC since
784 * represents a call depth of about 20 routines based on the minimum
785 * stack frame.
786 */
787#define CPU_STACK_MINIMUM_SIZE  (1024*4)
788
789/**
790 * What is the size of a pointer on this architecture?
791 */
792#define CPU_SIZEOF_POINTER 4
793
794/**
795 * CPU's worst alignment requirement for data types on a byte boundary.  This
796 * alignment does not take into account the requirements for the stack.
797 *
798 * On the SPARC, this is required for double word loads and stores.
799 */
800#define CPU_ALIGNMENT      8
801
802/**
803 * This number corresponds to the byte alignment requirement for the
804 * heap handler.  This alignment requirement may be stricter than that
805 * for the data types alignment specified by CPU_ALIGNMENT.  It is
806 * common for the heap to follow the same alignment requirement as
807 * CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
808 * then this should be set to CPU_ALIGNMENT.
809 *
810 * NOTE:  This does not have to be a power of 2.  It does have to
811 *        be greater or equal to than CPU_ALIGNMENT.
812 */
813#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
814
815/**
816 * This number corresponds to the byte alignment requirement for memory
817 * buffers allocated by the partition manager.  This alignment requirement
818 * may be stricter than that for the data types alignment specified by
819 * CPU_ALIGNMENT.  It is common for the partition to follow the same
820 * alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
821 * enough for the partition, then this should be set to CPU_ALIGNMENT.
822 *
823 * NOTE:  This does not have to be a power of 2.  It does have to
824 *        be greater or equal to than CPU_ALIGNMENT.
825 */
826#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
827
828/**
829 * Stack frames must be doubleword aligned according to the System V ABI for
830 * SPARC.
831 */
832#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
833
834#ifndef ASM
835
836/*
837 *  ISR handler macros
838 */
839
840/**
841 * Support routine to initialize the RTEMS vector table after it is allocated.
842 */
843#define _CPU_Initialize_vectors()
844
845/**
846 * Disable all interrupts for a critical section.  The previous
847 * level is returned in _level.
848 */
849#define _CPU_ISR_Disable( _level ) \
850  (_level) = sparc_disable_interrupts()
851
852/**
853 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
854 * This indicates the end of a critical section.  The parameter
855 * _level is not modified.
856 */
857#define _CPU_ISR_Enable( _level ) \
858  sparc_enable_interrupts( _level )
859
860/**
861 * This temporarily restores the interrupt to _level before immediately
862 * disabling them again.  This is used to divide long critical
863 * sections into two or more parts.  The parameter _level is not
864 * modified.
865 */
866#define _CPU_ISR_Flash( _level ) \
867  sparc_flash_interrupts( _level )
868
869#define _CPU_ISR_Is_enabled( _isr_cookie ) \
870  sparc_interrupt_is_enabled( _isr_cookie )
871
872RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
873{
874  return ( level & SPARC_PSR_PIL_MASK ) == 0;
875}
876
877/**
878 * Map interrupt level in task mode onto the hardware that the CPU
879 * actually provides.  Currently, interrupt levels which do not
880 * map onto the CPU in a straight fashion are undefined.
881 */
882#define _CPU_ISR_Set_level( _newlevel ) \
883   sparc_enable_interrupts( _newlevel << 8)
884
885/**
886 * @brief Obtain the current interrupt disable level.
887 *
888 * This method is invoked to return the current interrupt disable level.
889 *
890 * @return This method returns the current interrupt disable level.
891 */
892uint32_t   _CPU_ISR_Get_level( void );
893
894/* end of ISR handler macros */
895
896/* Context handler macros */
897
898/**
899 * Initialize the context to a state suitable for starting a
900 * task after a context restore operation.  Generally, this
901 * involves:
902 *
903 * - setting a starting address
904 * - preparing the stack
905 * - preparing the stack and frame pointers
906 * - setting the proper interrupt level in the context
907 * - initializing the floating point context
908 *
909 * @param[in] the_context points to the context area
910 * @param[in] stack_base is the low address of the allocated stack area
911 * @param[in] size is the size of the stack area in bytes
912 * @param[in] new_level is the interrupt level for the task
913 * @param[in] entry_point is the task's entry point
914 * @param[in] is_fp is set to TRUE if the task is a floating point task
915 * @param[in] tls_area is the thread-local storage (TLS) area
916 *
917 * NOTE:  Implemented as a subroutine for the SPARC port.
918 */
919void _CPU_Context_Initialize(
920  Context_Control  *the_context,
921  uint32_t         *stack_base,
922  uint32_t          size,
923  uint32_t          new_level,
924  void             *entry_point,
925  bool              is_fp,
926  void             *tls_area
927);
928
929/**
930 * This macro is invoked from _Thread_Handler to do whatever CPU
931 * specific magic is required that must be done in the context of
932 * the thread when it starts.
933 *
934 * On the SPARC, this is setting the frame pointer so GDB is happy.
935 * Make GDB stop unwinding at _Thread_Handler, previous register window
936 * Frame pointer is 0 and calling address must be a function with starting
937 * with a SAVE instruction. If return address is leaf-function (no SAVE)
938 * GDB will not look at prev reg window fp.
939 *
940 * _Thread_Handler is known to start with SAVE.
941 */
942#define _CPU_Context_Initialization_at_thread_begin() \
943  do { \
944    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
945  } while (0)
946
947/**
948 * This routine is responsible for somehow restarting the currently
949 * executing task.
950 *
951 * On the SPARC, this is is relatively painless but requires a small
952 * amount of wrapper code before using the regular restore code in
953 * of the context switch.
954 */
955#define _CPU_Context_Restart_self( _the_context ) \
956   _CPU_Context_restore( (_the_context) );
957
958/**
959 * This routine initializes the FP context area passed to it to.
960 *
961 * The SPARC allows us to use the simple initialization model
962 * in which an "initial" FP context was saved into _CPU_Null_fp_context
963 * at CPU initialization and it is simply copied into the destination
964 * context.
965 */
966#define _CPU_Context_Initialize_fp( _destination ) \
967  do { \
968   *(*(_destination)) = _CPU_Null_fp_context; \
969  } while (0)
970
971/* end of Context handler macros */
972
973/* Fatal Error manager macros */
974
975/**
976 * This routine copies _error into a known place -- typically a stack
977 * location or a register, optionally disables interrupts, and
978 * halts/stops the CPU.
979 */
980extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
981  RTEMS_NO_RETURN;
982
983/* end of Fatal Error manager macros */
984
985/* Bitfield handler macros */
986
987#if ( SPARC_HAS_BITSCAN == 0 )
988  /**
989   * The SPARC port uses the generic C algorithm for bitfield scan if the
990   * CPU model does not have a scan instruction.
991   */
992  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
993#else
994  #error "scan instruction not currently supported by RTEMS!!"
995#endif
996
997/* end of Bitfield handler macros */
998
999/* functions */
1000
1001/**
1002 * @brief SPARC specific initialization.
1003 *
1004 * This routine performs CPU dependent initialization.
1005 */
1006void _CPU_Initialize(void);
1007
1008/**
1009 * @brief SPARC specific raw ISR installer.
1010 *
1011 * This routine installs @a new_handler to be directly called from the trap
1012 * table.
1013 *
1014 * @param[in] vector is the vector number
1015 * @param[in] new_handler is the new ISR handler
1016 * @param[in] old_handler will contain the old ISR handler
1017 */
1018void _CPU_ISR_install_raw_handler(
1019  uint32_t    vector,
1020  proc_ptr    new_handler,
1021  proc_ptr   *old_handler
1022);
1023
1024/**
1025 * @brief SPARC specific RTEMS ISR installer.
1026 *
1027 * This routine installs an interrupt vector.
1028 *
1029 * @param[in] vector is the vector number
1030 * @param[in] new_handler is the new ISR handler
1031 * @param[in] old_handler will contain the old ISR handler
1032 */
1033
1034void _CPU_ISR_install_vector(
1035  uint32_t    vector,
1036  proc_ptr    new_handler,
1037  proc_ptr   *old_handler
1038);
1039
1040/**
1041 * @brief SPARC specific context switch.
1042 *
1043 * This routine switches from the run context to the heir context.
1044 *
1045 * @param[in] run is the currently executing thread
1046 * @param[in] heir will become the currently executing thread
1047 */
1048void _CPU_Context_switch(
1049  Context_Control  *run,
1050  Context_Control  *heir
1051);
1052
1053/**
1054 * @brief SPARC specific context restore.
1055 *
1056 * This routine is generally used only to restart self in an
1057 * efficient manner.
1058 *
1059 * @param[in] new_context is the context to restore
1060 */
1061void _CPU_Context_restore(
1062  Context_Control *new_context
1063) RTEMS_NO_RETURN;
1064
1065#if defined(RTEMS_SMP)
1066  uint32_t _CPU_SMP_Initialize( void );
1067
1068  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1069
1070  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1071
1072  void _CPU_SMP_Prepare_start_multitasking( void );
1073
1074  #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
1075    static inline uint32_t _CPU_SMP_Get_current_processor( void )
1076    {
1077      return _LEON3_Get_current_processor();
1078    }
1079  #else
1080    uint32_t _CPU_SMP_Get_current_processor( void );
1081  #endif
1082
1083  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1084
1085  static inline void _CPU_SMP_Processor_event_broadcast( void )
1086  {
1087    __asm__ volatile ( "" : : : "memory" );
1088  }
1089
1090  static inline void _CPU_SMP_Processor_event_receive( void )
1091  {
1092    __asm__ volatile ( "" : : : "memory" );
1093  }
1094#endif
1095
1096/**
1097 * @brief SPARC specific save FPU method.
1098 *
1099 * This routine saves the floating point context passed to it.
1100 *
1101 * @param[in] fp_context_ptr is the area to save into
1102 */
1103void _CPU_Context_save_fp(
1104  Context_Control_fp **fp_context_ptr
1105);
1106
1107/**
1108 * @brief SPARC specific restore FPU method.
1109 *
1110 * This routine restores the floating point context passed to it.
1111 *
1112 * @param[in] fp_context_ptr is the area to restore from
1113 */
1114void _CPU_Context_restore_fp(
1115  Context_Control_fp **fp_context_ptr
1116);
1117
1118void _CPU_Context_volatile_clobber( uintptr_t pattern );
1119
1120void _CPU_Context_validate( uintptr_t pattern );
1121
1122typedef struct {
1123  uint32_t trap;
1124  CPU_Interrupt_frame *isf;
1125} CPU_Exception_frame;
1126
1127void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1128
1129/**
1130 * @brief SPARC specific method to endian swap an uint32_t.
1131 *
1132 * The following routine swaps the endian format of an unsigned int.
1133 * It must be static because it is referenced indirectly.
1134 *
1135 * @param[in] value is the value to endian swap
1136 *
1137 * This version will work on any processor, but if you come across a better
1138 * way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
1139 * entity as shown below is not any more efficient on the SPARC.
1140 *
1141 *    - swap least significant two bytes with 16-bit rotate
1142 *    - swap upper and lower 16-bits
1143 *    - swap most significant two bytes with 16-bit rotate
1144 *
1145 * It is not obvious how the SPARC can do significantly better than the
1146 * generic code.  gcc 2.7.0 only generates about 12 instructions for the
1147 * following code at optimization level four (i.e. -O4).
1148 */
1149static inline uint32_t CPU_swap_u32(
1150  uint32_t value
1151)
1152{
1153  uint32_t   byte1, byte2, byte3, byte4, swapped;
1154
1155  byte4 = (value >> 24) & 0xff;
1156  byte3 = (value >> 16) & 0xff;
1157  byte2 = (value >> 8)  & 0xff;
1158  byte1 =  value        & 0xff;
1159
1160  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1161  return( swapped );
1162}
1163
1164/**
1165 * @brief SPARC specific method to endian swap an uint16_t.
1166 *
1167 * The following routine swaps the endian format of a uint16_t.
1168 *
1169 * @param[in] value is the value to endian swap
1170 */
1171#define CPU_swap_u16( value ) \
1172  (((value&0xff) << 8) | ((value >> 8)&0xff))
1173
1174typedef uint32_t CPU_Counter_ticks;
1175
1176typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void );
1177
1178typedef CPU_Counter_ticks ( *SPARC_Counter_difference )(
1179  CPU_Counter_ticks second,
1180  CPU_Counter_ticks first
1181);
1182
1183/*
1184 * The SPARC processors supported by RTEMS have no built-in CPU counter
1185 * support.  We have to use some hardware counter module for this purpose, for
1186 * example the GPTIMER instance used by the clock driver.  The BSP must provide
1187 * an implementation of the CPU counter read and difference functions.  This
1188 * allows the use of dynamic hardware enumeration.
1189 */
1190typedef struct {
1191  SPARC_Counter_read                counter_read;
1192  SPARC_Counter_difference          counter_difference;
1193  volatile const CPU_Counter_ticks *counter_address;
1194} SPARC_Counter;
1195
1196extern const SPARC_Counter _SPARC_Counter;
1197
1198static inline CPU_Counter_ticks _CPU_Counter_read( void )
1199{
1200  return ( *_SPARC_Counter.counter_read )();
1201}
1202
1203static inline CPU_Counter_ticks _CPU_Counter_difference(
1204  CPU_Counter_ticks second,
1205  CPU_Counter_ticks first
1206)
1207{
1208  return ( *_SPARC_Counter.counter_difference )( second, first );
1209}
1210
1211#endif /* ASM */
1212
1213#ifdef __cplusplus
1214}
1215#endif
1216
1217#endif
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