[f4ae0c5] | 1 | /** |
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[1362b7a] | 2 | * @file |
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[4bafde5] | 3 | * |
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[1362b7a] | 4 | * @brief SPARC CPU Department Source |
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| 5 | * |
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| 6 | * This include file contains information pertaining to the port of |
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| 7 | * the executive to the SPARC processor. |
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[f4ae0c5] | 8 | */ |
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| 9 | |
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| 10 | /* |
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[06dcaf0] | 11 | * COPYRIGHT (c) 1989-2011. |
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[7908ba5b] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_CPU_H |
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| 20 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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[22ed9d0f] | 26 | #include <rtems/score/types.h> |
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[89b85e51] | 27 | #include <rtems/score/sparc.h> |
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[7908ba5b] | 28 | |
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| 29 | /* conditional compilation parameters */ |
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| 30 | |
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[4bafde5] | 31 | /** |
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[1362b7a] | 32 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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[7908ba5b] | 33 | * |
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[1362b7a] | 34 | * - If TRUE, then they are inlined. |
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| 35 | * - If FALSE, then a subroutine call is made. |
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[4bafde5] | 36 | * |
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[1362b7a] | 37 | * On this port, it is faster to inline _Thread_Enable_dispatch. |
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[7908ba5b] | 38 | */ |
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| 39 | #define CPU_INLINE_ENABLE_DISPATCH TRUE |
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| 40 | |
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[4bafde5] | 41 | /** |
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[1362b7a] | 42 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 43 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 44 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 45 | * is examined per iteration. |
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[7908ba5b] | 46 | * |
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[1362b7a] | 47 | * - If TRUE, then the loops are unrolled. |
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| 48 | * - If FALSE, then the loops are not unrolled. |
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[7908ba5b] | 49 | * |
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[1362b7a] | 50 | * This parameter could go either way on the SPARC. The interrupt flash |
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| 51 | * code is relatively lengthy given the requirements for nops following |
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| 52 | * writes to the psr. But if the clock speed were high enough, this would |
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| 53 | * not represent a great deal of time. |
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[7908ba5b] | 54 | */ |
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| 55 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 56 | |
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[4bafde5] | 57 | /** |
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[1362b7a] | 58 | * Does the executive manage a dedicated interrupt stack in software? |
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[7908ba5b] | 59 | * |
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[1362b7a] | 60 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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| 61 | * If FALSE, nothing is done. |
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[7908ba5b] | 62 | * |
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[1362b7a] | 63 | * The SPARC does not have a dedicated HW interrupt stack and one has |
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| 64 | * been implemented in SW. |
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[7908ba5b] | 65 | */ |
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| 66 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 67 | |
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[4bafde5] | 68 | /** |
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[1362b7a] | 69 | * Does the CPU follow the simple vectored interrupt model? |
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[2fd427c] | 70 | * |
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[1362b7a] | 71 | * - If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 72 | * - If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 73 | * table |
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[2fd427c] | 74 | * |
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[1362b7a] | 75 | * THe SPARC is a simple vectored architecture. Usually there is no |
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| 76 | * PIC and the CPU directly vectors the interrupts. |
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[2fd427c] | 77 | */ |
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| 78 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 79 | |
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[1362b7a] | 80 | /** |
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| 81 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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[7908ba5b] | 82 | * |
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[1362b7a] | 83 | * - If TRUE, then it must be installed during initialization. |
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| 84 | * - If FALSE, then no installation is performed. |
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[7908ba5b] | 85 | * |
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[1362b7a] | 86 | * The SPARC does not have a dedicated HW interrupt stack. |
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[7908ba5b] | 87 | */ |
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| 88 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 89 | |
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[4bafde5] | 90 | /** |
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[1362b7a] | 91 | * Do we allocate a dedicated interrupt stack in the Interrupt Manager? |
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[7908ba5b] | 92 | * |
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[1362b7a] | 93 | * - If TRUE, then the memory is allocated during initialization. |
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| 94 | * - If FALSE, then the memory is allocated during initialization. |
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[4bafde5] | 95 | * |
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[1362b7a] | 96 | * The SPARC does not have hardware support for switching to a |
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| 97 | * dedicated interrupt stack. The port includes support for doing this |
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| 98 | * in software. |
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[4bafde5] | 99 | * |
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[7908ba5b] | 100 | */ |
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| 101 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 102 | |
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[4bafde5] | 103 | /** |
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[1362b7a] | 104 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 105 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 106 | * number (0)? |
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[4bafde5] | 107 | * |
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[1362b7a] | 108 | * The SPARC port does not pass an Interrupt Stack Frame pointer to |
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| 109 | * interrupt handlers. |
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[7908ba5b] | 110 | */ |
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| 111 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 112 | |
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[4bafde5] | 113 | /** |
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[1362b7a] | 114 | * Does the CPU have hardware floating point? |
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[7908ba5b] | 115 | * |
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[1362b7a] | 116 | * - If TRUE, then the FLOATING_POINT task attribute is supported. |
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| 117 | * - If FALSE, then the FLOATING_POINT task attribute is ignored. |
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[4bafde5] | 118 | * |
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[1362b7a] | 119 | * This is set based upon the multilib settings. |
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[7908ba5b] | 120 | */ |
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| 121 | #if ( SPARC_HAS_FPU == 1 ) |
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[4bafde5] | 122 | #define CPU_HARDWARE_FP TRUE |
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[7908ba5b] | 123 | #else |
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[4bafde5] | 124 | #define CPU_HARDWARE_FP FALSE |
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[7908ba5b] | 125 | #endif |
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[4bafde5] | 126 | |
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| 127 | /** |
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[1362b7a] | 128 | * The SPARC GCC port does not have a software floating point library |
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| 129 | * that requires RTEMS assistance. |
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[4bafde5] | 130 | */ |
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[17508d02] | 131 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 132 | |
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[4bafde5] | 133 | /** |
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[1362b7a] | 134 | * Are all tasks FLOATING_POINT tasks implicitly? |
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[7908ba5b] | 135 | * |
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[1362b7a] | 136 | * - If TRUE, then the FLOATING_POINT task attribute is assumed. |
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| 137 | * - If FALSE, then the FLOATING_POINT task attribute is followed. |
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[4bafde5] | 138 | * |
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[1362b7a] | 139 | * The SPARC GCC port does not implicitly use floating point registers. |
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[7908ba5b] | 140 | */ |
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| 141 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 142 | |
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[4bafde5] | 143 | /** |
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[1362b7a] | 144 | * Should the IDLE task have a floating point context? |
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[7908ba5b] | 145 | * |
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[1362b7a] | 146 | * - If TRUE, then the IDLE task is created as a FLOATING_POINT task |
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| 147 | * and it has a floating point context which is switched in and out. |
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| 148 | * - If FALSE, then the IDLE task does not have a floating point context. |
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[4bafde5] | 149 | * |
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[1362b7a] | 150 | * The IDLE task does not have to be floating point on the SPARC. |
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[7908ba5b] | 151 | */ |
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| 152 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 153 | |
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[4bafde5] | 154 | /** |
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[1362b7a] | 155 | * Should the saving of the floating point registers be deferred |
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| 156 | * until a context switch is made to another different floating point |
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| 157 | * task? |
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[7908ba5b] | 158 | * |
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[1362b7a] | 159 | * - If TRUE, then the floating point context will not be stored until |
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| 160 | * necessary. It will remain in the floating point registers and not |
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| 161 | * disturned until another floating point task is switched to. |
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[7908ba5b] | 162 | * |
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[1362b7a] | 163 | * - If FALSE, then the floating point context is saved when a floating |
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| 164 | * point task is switched out and restored when the next floating point |
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| 165 | * task is restored. The state of the floating point registers between |
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| 166 | * those two operations is not specified. |
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[4bafde5] | 167 | * |
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[1362b7a] | 168 | * On the SPARC, we can disable the FPU for integer only tasks so |
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| 169 | * it is safe to defer floating point context switches. |
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[7908ba5b] | 170 | */ |
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[965ef82] | 171 | #if defined(RTEMS_SMP) |
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| 172 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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| 173 | #else |
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| 174 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 175 | #endif |
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[7908ba5b] | 176 | |
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[4bafde5] | 177 | /** |
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[1362b7a] | 178 | * Does this port provide a CPU dependent IDLE task implementation? |
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[7908ba5b] | 179 | * |
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[1362b7a] | 180 | * - If TRUE, then the routine _CPU_Thread_Idle_body |
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| 181 | * must be provided and is the default IDLE thread body instead of |
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| 182 | * _CPU_Thread_Idle_body. |
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[7908ba5b] | 183 | * |
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[1362b7a] | 184 | * - If FALSE, then use the generic IDLE thread body if the BSP does |
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| 185 | * not provide one. |
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[4bafde5] | 186 | * |
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[1362b7a] | 187 | * The SPARC architecture does not have a low power or halt instruction. |
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| 188 | * It is left to the BSP and/or CPU specific code to provide an IDLE |
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| 189 | * thread body which is aware of low power modes. |
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[7908ba5b] | 190 | */ |
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| 191 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 192 | |
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[4bafde5] | 193 | /** |
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[1362b7a] | 194 | * Does the stack grow up (toward higher addresses) or down |
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| 195 | * (toward lower addresses)? |
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[7908ba5b] | 196 | * |
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[1362b7a] | 197 | * - If TRUE, then the grows upward. |
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| 198 | * - If FALSE, then the grows toward smaller addresses. |
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[7908ba5b] | 199 | * |
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[1362b7a] | 200 | * The stack grows to lower addresses on the SPARC. |
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[7908ba5b] | 201 | */ |
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| 202 | #define CPU_STACK_GROWS_UP FALSE |
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| 203 | |
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[4bafde5] | 204 | /** |
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[1362b7a] | 205 | * The following is the variable attribute used to force alignment |
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| 206 | * of critical data structures. On some processors it may make |
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| 207 | * sense to have these aligned on tighter boundaries than |
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| 208 | * the minimum requirements of the compiler in order to have as |
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| 209 | * much of the critical data area as possible in a cache line. |
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[7908ba5b] | 210 | * |
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[1362b7a] | 211 | * The SPARC does not appear to have particularly strict alignment |
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| 212 | * requirements. This value was chosen to take advantages of caches. |
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[7908ba5b] | 213 | */ |
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[ece9754] | 214 | #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) |
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[7908ba5b] | 215 | |
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[9c121991] | 216 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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| 217 | |
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[4bafde5] | 218 | /** |
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[1362b7a] | 219 | * Define what is required to specify how the network to host conversion |
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| 220 | * routines are handled. |
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[4bafde5] | 221 | * |
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[1362b7a] | 222 | * The SPARC is big endian. |
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[7908ba5b] | 223 | */ |
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| 224 | #define CPU_BIG_ENDIAN TRUE |
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[4bafde5] | 225 | |
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| 226 | /** |
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[1362b7a] | 227 | * Define what is required to specify how the network to host conversion |
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| 228 | * routines are handled. |
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[4bafde5] | 229 | * |
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[1362b7a] | 230 | * The SPARC is NOT little endian. |
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[4bafde5] | 231 | */ |
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[7908ba5b] | 232 | #define CPU_LITTLE_ENDIAN FALSE |
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| 233 | |
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[4bafde5] | 234 | /** |
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[1362b7a] | 235 | * The following defines the number of bits actually used in the |
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| 236 | * interrupt field of the task mode. How those bits map to the |
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| 237 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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[7908ba5b] | 238 | * |
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[1362b7a] | 239 | * The SPARC has 16 interrupt levels in the PIL field of the PSR. |
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[7908ba5b] | 240 | */ |
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| 241 | #define CPU_MODES_INTERRUPT_MASK 0x0000000F |
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| 242 | |
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[4bafde5] | 243 | #ifndef ASM |
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| 244 | /** |
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[1362b7a] | 245 | * This structure represents the organization of the minimum stack frame |
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| 246 | * for the SPARC. More framing information is required in certain situaions |
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| 247 | * such as when there are a large number of out parameters or when the callee |
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| 248 | * must save floating point registers. |
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[7908ba5b] | 249 | */ |
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| 250 | typedef struct { |
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[4bafde5] | 251 | /** This is the offset of the l0 register. */ |
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[2a0a6851] | 252 | uint32_t l0; |
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[4bafde5] | 253 | /** This is the offset of the l1 register. */ |
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[2a0a6851] | 254 | uint32_t l1; |
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[4bafde5] | 255 | /** This is the offset of the l2 register. */ |
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[2a0a6851] | 256 | uint32_t l2; |
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[4bafde5] | 257 | /** This is the offset of the l3 register. */ |
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[2a0a6851] | 258 | uint32_t l3; |
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[4bafde5] | 259 | /** This is the offset of the l4 register. */ |
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[2a0a6851] | 260 | uint32_t l4; |
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[4bafde5] | 261 | /** This is the offset of the l5 register. */ |
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[2a0a6851] | 262 | uint32_t l5; |
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[4bafde5] | 263 | /** This is the offset of the l6 register. */ |
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[2a0a6851] | 264 | uint32_t l6; |
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[4bafde5] | 265 | /** This is the offset of the l7 register. */ |
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[2a0a6851] | 266 | uint32_t l7; |
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[4bafde5] | 267 | /** This is the offset of the l0 register. */ |
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[2a0a6851] | 268 | uint32_t i0; |
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[4bafde5] | 269 | /** This is the offset of the i1 register. */ |
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[2a0a6851] | 270 | uint32_t i1; |
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[4bafde5] | 271 | /** This is the offset of the i2 register. */ |
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[2a0a6851] | 272 | uint32_t i2; |
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[4bafde5] | 273 | /** This is the offset of the i3 register. */ |
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[2a0a6851] | 274 | uint32_t i3; |
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[4bafde5] | 275 | /** This is the offset of the i4 register. */ |
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[2a0a6851] | 276 | uint32_t i4; |
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[4bafde5] | 277 | /** This is the offset of the i5 register. */ |
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[2a0a6851] | 278 | uint32_t i5; |
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[4bafde5] | 279 | /** This is the offset of the i6 register. */ |
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[2a0a6851] | 280 | uint32_t i6_fp; |
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[4bafde5] | 281 | /** This is the offset of the i7 register. */ |
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[2a0a6851] | 282 | uint32_t i7; |
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[4bafde5] | 283 | /** This is the offset of the register used to return structures. */ |
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[7908ba5b] | 284 | void *structure_return_address; |
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[4bafde5] | 285 | |
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[7908ba5b] | 286 | /* |
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[1362b7a] | 287 | * The following are for the callee to save the register arguments in |
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| 288 | * should this be necessary. |
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[7908ba5b] | 289 | */ |
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[4bafde5] | 290 | /** This is the offset of the register for saved argument 0. */ |
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[2a0a6851] | 291 | uint32_t saved_arg0; |
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[4bafde5] | 292 | /** This is the offset of the register for saved argument 1. */ |
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[2a0a6851] | 293 | uint32_t saved_arg1; |
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[4bafde5] | 294 | /** This is the offset of the register for saved argument 2. */ |
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[2a0a6851] | 295 | uint32_t saved_arg2; |
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[4bafde5] | 296 | /** This is the offset of the register for saved argument 3. */ |
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[2a0a6851] | 297 | uint32_t saved_arg3; |
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[4bafde5] | 298 | /** This is the offset of the register for saved argument 4. */ |
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[2a0a6851] | 299 | uint32_t saved_arg4; |
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[4bafde5] | 300 | /** This is the offset of the register for saved argument 5. */ |
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[2a0a6851] | 301 | uint32_t saved_arg5; |
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[4bafde5] | 302 | /** This field pads the structure so ldd and std instructions can be used. */ |
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[2a0a6851] | 303 | uint32_t pad0; |
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[7908ba5b] | 304 | } CPU_Minimum_stack_frame; |
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| 305 | |
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| 306 | #endif /* ASM */ |
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| 307 | |
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[4bafde5] | 308 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 309 | #define CPU_STACK_FRAME_L0_OFFSET 0x00 |
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[4bafde5] | 310 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 311 | #define CPU_STACK_FRAME_L1_OFFSET 0x04 |
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[4bafde5] | 312 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 313 | #define CPU_STACK_FRAME_L2_OFFSET 0x08 |
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[4bafde5] | 314 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 315 | #define CPU_STACK_FRAME_L3_OFFSET 0x0c |
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[4bafde5] | 316 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 317 | #define CPU_STACK_FRAME_L4_OFFSET 0x10 |
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[4bafde5] | 318 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 319 | #define CPU_STACK_FRAME_L5_OFFSET 0x14 |
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[4bafde5] | 320 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 321 | #define CPU_STACK_FRAME_L6_OFFSET 0x18 |
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[4bafde5] | 322 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 323 | #define CPU_STACK_FRAME_L7_OFFSET 0x1c |
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[4bafde5] | 324 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 325 | #define CPU_STACK_FRAME_I0_OFFSET 0x20 |
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[4bafde5] | 326 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 327 | #define CPU_STACK_FRAME_I1_OFFSET 0x24 |
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[4bafde5] | 328 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 329 | #define CPU_STACK_FRAME_I2_OFFSET 0x28 |
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[4bafde5] | 330 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 331 | #define CPU_STACK_FRAME_I3_OFFSET 0x2c |
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[4bafde5] | 332 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 333 | #define CPU_STACK_FRAME_I4_OFFSET 0x30 |
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[4bafde5] | 334 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 335 | #define CPU_STACK_FRAME_I5_OFFSET 0x34 |
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[4bafde5] | 336 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 337 | #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 |
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[4bafde5] | 338 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 339 | #define CPU_STACK_FRAME_I7_OFFSET 0x3c |
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[4bafde5] | 340 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 341 | #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 |
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[4bafde5] | 342 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 343 | #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 |
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[4bafde5] | 344 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 345 | #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 |
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[4bafde5] | 346 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 347 | #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c |
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[4bafde5] | 348 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 349 | #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 |
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[4bafde5] | 350 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 351 | #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 |
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[4bafde5] | 352 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 353 | #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 |
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[4bafde5] | 354 | /** This macro defines an offset into the stack frame for use in assembly. */ |
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[7908ba5b] | 355 | #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c |
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| 356 | |
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[4bafde5] | 357 | /** This defines the size of the minimum stack frame. */ |
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[7908ba5b] | 358 | #define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 |
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| 359 | |
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[f8ad6c6f] | 360 | #define CPU_PER_CPU_CONTROL_SIZE 4 |
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| 361 | |
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| 362 | /** |
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| 363 | * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field |
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| 364 | * relative to the Per_CPU_Control begin. |
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| 365 | */ |
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| 366 | #define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 |
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[10fd4aac] | 367 | |
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[4bafde5] | 368 | /** |
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| 369 | * @defgroup Contexts SPARC Context Structures |
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[7908ba5b] | 370 | * |
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[1362b7a] | 371 | * @ingroup Score |
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| 372 | * |
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| 373 | * Generally there are 2 types of context to save. |
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| 374 | * + Interrupt registers to save |
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| 375 | * + Task level registers to save |
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[b8fc260f] | 376 | * |
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[1362b7a] | 377 | * This means we have the following 3 context items: |
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| 378 | * + task level context stuff:: Context_Control |
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| 379 | * + floating point task stuff:: Context_Control_fp |
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| 380 | * + special interrupt level context :: Context_Control_interrupt |
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[7908ba5b] | 381 | * |
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[1362b7a] | 382 | * On the SPARC, we are relatively conservative in that we save most |
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| 383 | * of the CPU state in the context area. The ET (enable trap) bit and |
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| 384 | * the CWP (current window pointer) fields of the PSR are considered |
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| 385 | * system wide resources and are not maintained on a per-thread basis. |
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[7908ba5b] | 386 | */ |
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[b697bc6] | 387 | /**@{**/ |
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[7908ba5b] | 388 | |
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| 389 | #ifndef ASM |
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[10fd4aac] | 390 | |
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| 391 | typedef struct { |
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[f8ad6c6f] | 392 | /** |
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| 393 | * This flag is context switched with each thread. It indicates |
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| 394 | * that THIS thread has an _ISR_Dispatch stack frame on its stack. |
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| 395 | * By using this flag, we can avoid nesting more interrupt dispatching |
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| 396 | * attempts on a previously interrupted thread's stack. |
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| 397 | */ |
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| 398 | uint32_t isr_dispatch_disable; |
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[10fd4aac] | 399 | } CPU_Per_CPU_control; |
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| 400 | |
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[4bafde5] | 401 | /** |
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[1362b7a] | 402 | * @brief SPARC basic context. |
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[4bafde5] | 403 | * |
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[97cf623d] | 404 | * This structure defines the non-volatile integer and processor state context |
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| 405 | * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY |
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| 406 | * INTERFACE - SPARC Processor Supplement", Third Edition. |
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[b2ec2d15] | 407 | * |
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| 408 | * The registers g2 through g4 are reserved for applications. GCC uses them as |
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| 409 | * volatile registers by default. So they are treated like volatile registers |
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| 410 | * in RTEMS as well. |
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[7c0bd74] | 411 | * |
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| 412 | * The register g6 contains the per-CPU control of the current processor. It |
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| 413 | * is an invariant of the processor context. This register must not be saved |
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| 414 | * and restored during context switches or interrupt services. |
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[4bafde5] | 415 | */ |
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[7908ba5b] | 416 | typedef struct { |
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[4bafde5] | 417 | /** This will contain the contents of the g5 register. */ |
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| 418 | uint32_t g5; |
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| 419 | /** This will contain the contents of the g7 register. */ |
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| 420 | uint32_t g7; |
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| 421 | |
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[b2ec2d15] | 422 | /** |
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| 423 | * This will contain the contents of the l0 and l1 registers. |
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| 424 | * |
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| 425 | * Using a double l0_and_l1 will put everything in this structure on a double |
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| 426 | * word boundary which allows us to use double word loads and stores safely |
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| 427 | * in the context switch. |
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| 428 | */ |
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| 429 | double l0_and_l1; |
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[4bafde5] | 430 | /** This will contain the contents of the l2 register. */ |
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| 431 | uint32_t l2; |
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| 432 | /** This will contain the contents of the l3 register. */ |
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| 433 | uint32_t l3; |
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| 434 | /** This will contain the contents of the l4 register. */ |
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| 435 | uint32_t l4; |
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| 436 | /** This will contain the contents of the l5 registeer.*/ |
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| 437 | uint32_t l5; |
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| 438 | /** This will contain the contents of the l6 register. */ |
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| 439 | uint32_t l6; |
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| 440 | /** This will contain the contents of the l7 register. */ |
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| 441 | uint32_t l7; |
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| 442 | |
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| 443 | /** This will contain the contents of the i0 register. */ |
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| 444 | uint32_t i0; |
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| 445 | /** This will contain the contents of the i1 register. */ |
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| 446 | uint32_t i1; |
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| 447 | /** This will contain the contents of the i2 register. */ |
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| 448 | uint32_t i2; |
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| 449 | /** This will contain the contents of the i3 register. */ |
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| 450 | uint32_t i3; |
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| 451 | /** This will contain the contents of the i4 register. */ |
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| 452 | uint32_t i4; |
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| 453 | /** This will contain the contents of the i5 register. */ |
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| 454 | uint32_t i5; |
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| 455 | /** This will contain the contents of the i6 (e.g. frame pointer) register. */ |
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| 456 | uint32_t i6_fp; |
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| 457 | /** This will contain the contents of the i7 register. */ |
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| 458 | uint32_t i7; |
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| 459 | |
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| 460 | /** This will contain the contents of the o6 (e.g. frame pointer) register. */ |
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| 461 | uint32_t o6_sp; |
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[97cf623d] | 462 | /** |
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| 463 | * This will contain the contents of the o7 (e.g. address of CALL |
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| 464 | * instruction) register. |
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| 465 | */ |
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[4bafde5] | 466 | uint32_t o7; |
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| 467 | |
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| 468 | /** This will contain the contents of the processor status register. */ |
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| 469 | uint32_t psr; |
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| 470 | /** |
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| 471 | * This field is used to prevent heavy nesting of calls to _Thread_Dispatch |
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| 472 | * on an interrupted task's stack. This is problematic on the slower |
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| 473 | * SPARC CPU models at high interrupt rates. |
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| 474 | */ |
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| 475 | uint32_t isr_dispatch_disable; |
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[38b59a6] | 476 | |
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| 477 | #if defined(RTEMS_SMP) |
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[fbda4a8] | 478 | volatile uint32_t is_executing; |
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[38b59a6] | 479 | #endif |
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[7908ba5b] | 480 | } Context_Control; |
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| 481 | |
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[4bafde5] | 482 | /** |
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[1362b7a] | 483 | * This macro provides a CPU independent way for RTEMS to access the |
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| 484 | * stack pointer in a context structure. The actual name and offset is |
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| 485 | * CPU architecture dependent. |
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[4bafde5] | 486 | */ |
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[0ca6d0d9] | 487 | #define _CPU_Context_Get_SP( _context ) \ |
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| 488 | (_context)->o6_sp |
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| 489 | |
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[38b59a6] | 490 | #ifdef RTEMS_SMP |
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[11b05f1] | 491 | static inline bool _CPU_Context_Get_is_executing( |
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| 492 | const Context_Control *context |
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| 493 | ) |
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| 494 | { |
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| 495 | return context->is_executing; |
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| 496 | } |
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| 497 | |
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| 498 | static inline void _CPU_Context_Set_is_executing( |
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| 499 | Context_Control *context, |
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| 500 | bool is_executing |
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| 501 | ) |
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| 502 | { |
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| 503 | context->is_executing = is_executing; |
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| 504 | } |
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[38b59a6] | 505 | #endif |
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| 506 | |
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[7908ba5b] | 507 | #endif /* ASM */ |
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| 508 | |
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| 509 | /* |
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| 510 | * Offsets of fields with Context_Control for assembly routines. |
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| 511 | */ |
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| 512 | |
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[4bafde5] | 513 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 514 | #define G5_OFFSET 0x00 |
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[4bafde5] | 515 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 516 | #define G7_OFFSET 0x04 |
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[7908ba5b] | 517 | |
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[4bafde5] | 518 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 519 | #define L0_OFFSET 0x08 |
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[4bafde5] | 520 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 521 | #define L1_OFFSET 0x0C |
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[4bafde5] | 522 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 523 | #define L2_OFFSET 0x10 |
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[4bafde5] | 524 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 525 | #define L3_OFFSET 0x14 |
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[4bafde5] | 526 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 527 | #define L4_OFFSET 0x18 |
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[4bafde5] | 528 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 529 | #define L5_OFFSET 0x1C |
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[4bafde5] | 530 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 531 | #define L6_OFFSET 0x20 |
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[4bafde5] | 532 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 533 | #define L7_OFFSET 0x24 |
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[7908ba5b] | 534 | |
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[4bafde5] | 535 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 536 | #define I0_OFFSET 0x28 |
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[4bafde5] | 537 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 538 | #define I1_OFFSET 0x2C |
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[4bafde5] | 539 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 540 | #define I2_OFFSET 0x30 |
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[4bafde5] | 541 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 542 | #define I3_OFFSET 0x34 |
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[4bafde5] | 543 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 544 | #define I4_OFFSET 0x38 |
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[4bafde5] | 545 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 546 | #define I5_OFFSET 0x3C |
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[4bafde5] | 547 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 548 | #define I6_FP_OFFSET 0x40 |
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[4bafde5] | 549 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 550 | #define I7_OFFSET 0x44 |
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[7908ba5b] | 551 | |
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[4bafde5] | 552 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 553 | #define O6_SP_OFFSET 0x48 |
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[4bafde5] | 554 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 555 | #define O7_OFFSET 0x4C |
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[7908ba5b] | 556 | |
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[4bafde5] | 557 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 558 | #define PSR_OFFSET 0x50 |
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[4bafde5] | 559 | /** This macro defines an offset into the context for use in assembly. */ |
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[7c0bd74] | 560 | #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 |
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[7908ba5b] | 561 | |
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[38b59a6] | 562 | #if defined(RTEMS_SMP) |
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| 563 | #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 |
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| 564 | #endif |
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| 565 | |
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[4bafde5] | 566 | /** This defines the size of the context area for use in assembly. */ |
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[97cf623d] | 567 | #define CONTEXT_CONTROL_SIZE 0x68 |
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[7908ba5b] | 568 | |
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| 569 | #ifndef ASM |
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[4bafde5] | 570 | /** |
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[1362b7a] | 571 | * @brief SPARC basic context. |
---|
[4bafde5] | 572 | * |
---|
[1362b7a] | 573 | * This structure defines floating point context area. |
---|
[4bafde5] | 574 | */ |
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[7908ba5b] | 575 | typedef struct { |
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[4bafde5] | 576 | /** This will contain the contents of the f0 and f1 register. */ |
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| 577 | double f0_f1; |
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| 578 | /** This will contain the contents of the f2 and f3 register. */ |
---|
| 579 | double f2_f3; |
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| 580 | /** This will contain the contents of the f4 and f5 register. */ |
---|
| 581 | double f4_f5; |
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| 582 | /** This will contain the contents of the f6 and f7 register. */ |
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| 583 | double f6_f7; |
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| 584 | /** This will contain the contents of the f8 and f9 register. */ |
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| 585 | double f8_f9; |
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| 586 | /** This will contain the contents of the f10 and f11 register. */ |
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| 587 | double f10_f11; |
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| 588 | /** This will contain the contents of the f12 and f13 register. */ |
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| 589 | double f12_f13; |
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| 590 | /** This will contain the contents of the f14 and f15 register. */ |
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| 591 | double f14_f15; |
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| 592 | /** This will contain the contents of the f16 and f17 register. */ |
---|
| 593 | double f16_f17; |
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| 594 | /** This will contain the contents of the f18 and f19 register. */ |
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| 595 | double f18_f19; |
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| 596 | /** This will contain the contents of the f20 and f21 register. */ |
---|
| 597 | double f20_f21; |
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| 598 | /** This will contain the contents of the f22 and f23 register. */ |
---|
| 599 | double f22_f23; |
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| 600 | /** This will contain the contents of the f24 and f25 register. */ |
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| 601 | double f24_f25; |
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| 602 | /** This will contain the contents of the f26 and f27 register. */ |
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| 603 | double f26_f27; |
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| 604 | /** This will contain the contents of the f28 and f29 register. */ |
---|
| 605 | double f28_f29; |
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| 606 | /** This will contain the contents of the f30 and f31 register. */ |
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| 607 | double f30_f31; |
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| 608 | /** This will contain the contents of the floating point status register. */ |
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| 609 | uint32_t fsr; |
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[7908ba5b] | 610 | } Context_Control_fp; |
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| 611 | |
---|
| 612 | #endif /* ASM */ |
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| 613 | |
---|
| 614 | /* |
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| 615 | * Offsets of fields with Context_Control_fp for assembly routines. |
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| 616 | */ |
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| 617 | |
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[4bafde5] | 618 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 619 | #define FO_F1_OFFSET 0x00 |
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[4bafde5] | 620 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
[7908ba5b] | 621 | #define F2_F3_OFFSET 0x08 |
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[4bafde5] | 622 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 623 | #define F4_F5_OFFSET 0x10 |
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[4bafde5] | 624 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 625 | #define F6_F7_OFFSET 0x18 |
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[4bafde5] | 626 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 627 | #define F8_F9_OFFSET 0x20 |
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[4bafde5] | 628 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 629 | #define F1O_F11_OFFSET 0x28 |
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[4bafde5] | 630 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 631 | #define F12_F13_OFFSET 0x30 |
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[4bafde5] | 632 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 633 | #define F14_F15_OFFSET 0x38 |
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[4bafde5] | 634 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 635 | #define F16_F17_OFFSET 0x40 |
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[4bafde5] | 636 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 637 | #define F18_F19_OFFSET 0x48 |
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[4bafde5] | 638 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 639 | #define F2O_F21_OFFSET 0x50 |
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[4bafde5] | 640 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 641 | #define F22_F23_OFFSET 0x58 |
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[4bafde5] | 642 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
[7908ba5b] | 643 | #define F24_F25_OFFSET 0x60 |
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[4bafde5] | 644 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 645 | #define F26_F27_OFFSET 0x68 |
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[4bafde5] | 646 | /** This macro defines an offset into the FPU context for use in assembly. */ |
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[7908ba5b] | 647 | #define F28_F29_OFFSET 0x70 |
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[4bafde5] | 648 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
[7908ba5b] | 649 | #define F3O_F31_OFFSET 0x78 |
---|
[4bafde5] | 650 | /** This macro defines an offset into the FPU context for use in assembly. */ |
---|
[7908ba5b] | 651 | #define FSR_OFFSET 0x80 |
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| 652 | |
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[4bafde5] | 653 | /** This defines the size of the FPU context area for use in assembly. */ |
---|
[7908ba5b] | 654 | #define CONTEXT_CONTROL_FP_SIZE 0x84 |
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| 655 | |
---|
| 656 | #ifndef ASM |
---|
| 657 | |
---|
[1362b7a] | 658 | /** @} */ |
---|
| 659 | |
---|
[4bafde5] | 660 | /** |
---|
[1362b7a] | 661 | * @brief Interrupt stack frame (ISF). |
---|
[4bafde5] | 662 | * |
---|
[1362b7a] | 663 | * Context saved on stack for an interrupt. |
---|
[7908ba5b] | 664 | * |
---|
[1362b7a] | 665 | * NOTE: The PSR, PC, and NPC are only saved in this structure for the |
---|
| 666 | * benefit of the user's handler. |
---|
[7908ba5b] | 667 | */ |
---|
| 668 | typedef struct { |
---|
[4bafde5] | 669 | /** On an interrupt, we must save the minimum stack frame. */ |
---|
[7908ba5b] | 670 | CPU_Minimum_stack_frame Stack_frame; |
---|
[4bafde5] | 671 | /** This is the offset of the PSR on an ISF. */ |
---|
[2a0a6851] | 672 | uint32_t psr; |
---|
[4bafde5] | 673 | /** This is the offset of the XXX on an ISF. */ |
---|
[2a0a6851] | 674 | uint32_t pc; |
---|
[4bafde5] | 675 | /** This is the offset of the XXX on an ISF. */ |
---|
[2a0a6851] | 676 | uint32_t npc; |
---|
[4bafde5] | 677 | /** This is the offset of the g1 register on an ISF. */ |
---|
[2a0a6851] | 678 | uint32_t g1; |
---|
[4bafde5] | 679 | /** This is the offset of the g2 register on an ISF. */ |
---|
[2a0a6851] | 680 | uint32_t g2; |
---|
[4bafde5] | 681 | /** This is the offset of the g3 register on an ISF. */ |
---|
[2a0a6851] | 682 | uint32_t g3; |
---|
[4bafde5] | 683 | /** This is the offset of the g4 register on an ISF. */ |
---|
[2a0a6851] | 684 | uint32_t g4; |
---|
[4bafde5] | 685 | /** This is the offset of the g5 register on an ISF. */ |
---|
[2a0a6851] | 686 | uint32_t g5; |
---|
[7c0bd74] | 687 | /** This is the offset is reserved for alignment on an ISF. */ |
---|
| 688 | uint32_t reserved_for_alignment; |
---|
[4bafde5] | 689 | /** This is the offset of the g7 register on an ISF. */ |
---|
[2a0a6851] | 690 | uint32_t g7; |
---|
[4bafde5] | 691 | /** This is the offset of the i0 register on an ISF. */ |
---|
[2a0a6851] | 692 | uint32_t i0; |
---|
[4bafde5] | 693 | /** This is the offset of the i1 register on an ISF. */ |
---|
[2a0a6851] | 694 | uint32_t i1; |
---|
[4bafde5] | 695 | /** This is the offset of the i2 register on an ISF. */ |
---|
[2a0a6851] | 696 | uint32_t i2; |
---|
[4bafde5] | 697 | /** This is the offset of the i3 register on an ISF. */ |
---|
[2a0a6851] | 698 | uint32_t i3; |
---|
[4bafde5] | 699 | /** This is the offset of the i4 register on an ISF. */ |
---|
[2a0a6851] | 700 | uint32_t i4; |
---|
[4bafde5] | 701 | /** This is the offset of the i5 register on an ISF. */ |
---|
[2a0a6851] | 702 | uint32_t i5; |
---|
[4bafde5] | 703 | /** This is the offset of the i6 register on an ISF. */ |
---|
[2a0a6851] | 704 | uint32_t i6_fp; |
---|
[4bafde5] | 705 | /** This is the offset of the i7 register on an ISF. */ |
---|
[2a0a6851] | 706 | uint32_t i7; |
---|
[4bafde5] | 707 | /** This is the offset of the y register on an ISF. */ |
---|
[2a0a6851] | 708 | uint32_t y; |
---|
[4bafde5] | 709 | /** This is the offset of the tpc register on an ISF. */ |
---|
[2a0a6851] | 710 | uint32_t tpc; |
---|
[7908ba5b] | 711 | } CPU_Interrupt_frame; |
---|
| 712 | |
---|
| 713 | #endif /* ASM */ |
---|
| 714 | |
---|
| 715 | /* |
---|
| 716 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
---|
| 717 | */ |
---|
| 718 | |
---|
[4bafde5] | 719 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 720 | #define ISF_STACK_FRAME_OFFSET 0x00 |
---|
[4bafde5] | 721 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 722 | #define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 |
---|
[4bafde5] | 723 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 724 | #define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 |
---|
[4bafde5] | 725 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 726 | #define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 |
---|
[4bafde5] | 727 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 728 | #define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c |
---|
[4bafde5] | 729 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 730 | #define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 |
---|
[4bafde5] | 731 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 732 | #define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 |
---|
[4bafde5] | 733 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 734 | #define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 |
---|
[4bafde5] | 735 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 736 | #define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c |
---|
[4bafde5] | 737 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 738 | #define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 |
---|
[4bafde5] | 739 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 740 | #define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 |
---|
[4bafde5] | 741 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 742 | #define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c |
---|
[4bafde5] | 743 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 744 | #define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 |
---|
[4bafde5] | 745 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 746 | #define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 |
---|
[4bafde5] | 747 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 748 | #define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 |
---|
[4bafde5] | 749 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 750 | #define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c |
---|
[4bafde5] | 751 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 752 | #define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 |
---|
[4bafde5] | 753 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 754 | #define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 |
---|
[4bafde5] | 755 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 756 | #define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 |
---|
[4bafde5] | 757 | /** This macro defines an offset into the ISF for use in assembly. */ |
---|
[7908ba5b] | 758 | #define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c |
---|
| 759 | |
---|
[4bafde5] | 760 | /** This defines the size of the ISF area for use in assembly. */ |
---|
| 761 | #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ |
---|
| 762 | CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 |
---|
| 763 | |
---|
[7908ba5b] | 764 | #ifndef ASM |
---|
[4bafde5] | 765 | /** |
---|
[1362b7a] | 766 | * This variable is contains the initialize context for the FP unit. |
---|
| 767 | * It is filled in by _CPU_Initialize and copied into the task's FP |
---|
| 768 | * context area during _CPU_Context_Initialize. |
---|
[7908ba5b] | 769 | */ |
---|
| 770 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; |
---|
| 771 | |
---|
[4bafde5] | 772 | /** |
---|
[1362b7a] | 773 | * The following type defines an entry in the SPARC's trap table. |
---|
[7908ba5b] | 774 | * |
---|
[1362b7a] | 775 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
| 776 | * obligated to use two of the four instructions to perform a |
---|
| 777 | * long jump. The other instructions load one register with the |
---|
| 778 | * trap type (a.k.a. vector) and another with the psr. |
---|
[7908ba5b] | 779 | */ |
---|
| 780 | typedef struct { |
---|
[4bafde5] | 781 | /** This will contain a "mov %psr, %l0" instruction. */ |
---|
| 782 | uint32_t mov_psr_l0; |
---|
| 783 | /** This will contain a "sethi %hi(_handler), %l4" instruction. */ |
---|
| 784 | uint32_t sethi_of_handler_to_l4; |
---|
| 785 | /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ |
---|
| 786 | uint32_t jmp_to_low_of_handler_plus_l4; |
---|
| 787 | /** This will contain a " mov _vector, %l3" instruction. */ |
---|
| 788 | uint32_t mov_vector_l3; |
---|
[7908ba5b] | 789 | } CPU_Trap_table_entry; |
---|
[80f7732] | 790 | |
---|
[4bafde5] | 791 | /** |
---|
[1362b7a] | 792 | * This is the set of opcodes for the instructions loaded into a trap |
---|
| 793 | * table entry. The routine which installs a handler is responsible |
---|
| 794 | * for filling in the fields for the _handler address and the _vector |
---|
| 795 | * trap type. |
---|
[7908ba5b] | 796 | * |
---|
[1362b7a] | 797 | * The constants following this structure are masks for the fields which |
---|
| 798 | * must be filled in when the handler is installed. |
---|
[7908ba5b] | 799 | */ |
---|
| 800 | extern const CPU_Trap_table_entry _CPU_Trap_slot_template; |
---|
| 801 | |
---|
[4bafde5] | 802 | /** |
---|
[1362b7a] | 803 | * The size of the floating point context area. |
---|
[7908ba5b] | 804 | */ |
---|
| 805 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 806 | |
---|
| 807 | #endif |
---|
| 808 | |
---|
[4bafde5] | 809 | /** |
---|
[1362b7a] | 810 | * Amount of extra stack (above minimum stack size) required by |
---|
| 811 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 812 | * system this thread must exist and be able to process all directives. |
---|
[7908ba5b] | 813 | */ |
---|
| 814 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
---|
| 815 | |
---|
[4bafde5] | 816 | /** |
---|
[1362b7a] | 817 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 818 | * by the executive. |
---|
| 819 | * |
---|
| 820 | * On the SPARC, there are really only 256 vectors. However, the executive |
---|
| 821 | * has no easy, fast, reliable way to determine which traps are synchronous |
---|
| 822 | * and which are asynchronous. By default, synchronous traps return to the |
---|
| 823 | * instruction which caused the interrupt. So if you install a software |
---|
| 824 | * trap handler as an executive interrupt handler (which is desirable since |
---|
| 825 | * RTEMS takes care of window and register issues), then the executive needs |
---|
| 826 | * to know that the return address is to the trap rather than the instruction |
---|
| 827 | * following the trap. |
---|
| 828 | * |
---|
| 829 | * So vectors 0 through 255 are treated as regular asynchronous traps which |
---|
| 830 | * provide the "correct" return address. Vectors 256 through 512 are assumed |
---|
| 831 | * by the executive to be synchronous and to require that the return address |
---|
| 832 | * be fudged. |
---|
| 833 | * |
---|
| 834 | * If you use this mechanism to install a trap handler which must reexecute |
---|
| 835 | * the instruction which caused the trap, then it should be installed as |
---|
| 836 | * an asynchronous trap. This will avoid the executive changing the return |
---|
| 837 | * address. |
---|
[7908ba5b] | 838 | */ |
---|
| 839 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
---|
[4bafde5] | 840 | |
---|
| 841 | /** |
---|
| 842 | * The SPARC has 256 vectors but the port treats 256-512 as synchronous |
---|
| 843 | * traps. |
---|
| 844 | */ |
---|
[7908ba5b] | 845 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 |
---|
| 846 | |
---|
[4bafde5] | 847 | /** |
---|
[1362b7a] | 848 | * This is the bit step in a vector number to indicate it is being installed |
---|
| 849 | * as a synchronous trap. |
---|
[4bafde5] | 850 | */ |
---|
[7908ba5b] | 851 | #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
---|
[4bafde5] | 852 | |
---|
| 853 | /** |
---|
[1362b7a] | 854 | * This macro indicates that @a _trap as an asynchronous trap. |
---|
[4bafde5] | 855 | */ |
---|
[7908ba5b] | 856 | #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
---|
[4bafde5] | 857 | |
---|
| 858 | /** |
---|
[1362b7a] | 859 | * This macro indicates that @a _trap as a synchronous trap. |
---|
[4bafde5] | 860 | */ |
---|
[7908ba5b] | 861 | #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) |
---|
| 862 | |
---|
[4bafde5] | 863 | /** |
---|
| 864 | * This macro returns the real hardware vector number associated with @a _trap. |
---|
| 865 | */ |
---|
[7908ba5b] | 866 | #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) |
---|
| 867 | |
---|
[4bafde5] | 868 | /** |
---|
[1362b7a] | 869 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 870 | * level. Most ports maintain the variable _ISR_Nest_level. |
---|
[4db30283] | 871 | */ |
---|
| 872 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 873 | |
---|
[4bafde5] | 874 | /** |
---|
[1362b7a] | 875 | * Should be large enough to run all tests. This ensures |
---|
| 876 | * that a "reasonable" small application should not have any problems. |
---|
[7908ba5b] | 877 | * |
---|
[1362b7a] | 878 | * This appears to be a fairly generous number for the SPARC since |
---|
| 879 | * represents a call depth of about 20 routines based on the minimum |
---|
| 880 | * stack frame. |
---|
[7908ba5b] | 881 | */ |
---|
[20385957] | 882 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
[7908ba5b] | 883 | |
---|
[af99ec25] | 884 | /** |
---|
| 885 | * What is the size of a pointer on this architecture? |
---|
| 886 | */ |
---|
[f1738ed] | 887 | #define CPU_SIZEOF_POINTER 4 |
---|
| 888 | |
---|
[4bafde5] | 889 | /** |
---|
[1362b7a] | 890 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 891 | * alignment does not take into account the requirements for the stack. |
---|
[7908ba5b] | 892 | * |
---|
[1362b7a] | 893 | * On the SPARC, this is required for double word loads and stores. |
---|
[7908ba5b] | 894 | */ |
---|
| 895 | #define CPU_ALIGNMENT 8 |
---|
| 896 | |
---|
[4bafde5] | 897 | /** |
---|
[1362b7a] | 898 | * This number corresponds to the byte alignment requirement for the |
---|
| 899 | * heap handler. This alignment requirement may be stricter than that |
---|
| 900 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 901 | * common for the heap to follow the same alignment requirement as |
---|
| 902 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 903 | * then this should be set to CPU_ALIGNMENT. |
---|
[7908ba5b] | 904 | * |
---|
[1362b7a] | 905 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 906 | * be greater or equal to than CPU_ALIGNMENT. |
---|
[7908ba5b] | 907 | */ |
---|
| 908 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 909 | |
---|
[4bafde5] | 910 | /** |
---|
[1362b7a] | 911 | * This number corresponds to the byte alignment requirement for memory |
---|
| 912 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 913 | * may be stricter than that for the data types alignment specified by |
---|
| 914 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 915 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 916 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
[7908ba5b] | 917 | * |
---|
[1362b7a] | 918 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 919 | * be greater or equal to than CPU_ALIGNMENT. |
---|
[7908ba5b] | 920 | */ |
---|
| 921 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 922 | |
---|
[4bafde5] | 923 | /** |
---|
[1362b7a] | 924 | * This number corresponds to the byte alignment requirement for the |
---|
| 925 | * stack. This alignment requirement may be stricter than that for the |
---|
| 926 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 927 | * is strict enough for the stack, then this should be set to 0. |
---|
[7908ba5b] | 928 | * |
---|
[1362b7a] | 929 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
[7908ba5b] | 930 | * |
---|
[1362b7a] | 931 | * The alignment restrictions for the SPARC are not that strict but this |
---|
| 932 | * should unsure that the stack is always sufficiently alignment that the |
---|
| 933 | * window overflow, underflow, and flush routines can use double word loads |
---|
| 934 | * and stores. |
---|
[7908ba5b] | 935 | */ |
---|
| 936 | #define CPU_STACK_ALIGNMENT 16 |
---|
| 937 | |
---|
| 938 | #ifndef ASM |
---|
| 939 | |
---|
[fe7acdcf] | 940 | /* |
---|
| 941 | * ISR handler macros |
---|
| 942 | */ |
---|
| 943 | |
---|
[4bafde5] | 944 | /** |
---|
[1362b7a] | 945 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
[fe7acdcf] | 946 | */ |
---|
| 947 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 948 | |
---|
[4bafde5] | 949 | /** |
---|
[1362b7a] | 950 | * Disable all interrupts for a critical section. The previous |
---|
| 951 | * level is returned in _level. |
---|
[7908ba5b] | 952 | */ |
---|
| 953 | #define _CPU_ISR_Disable( _level ) \ |
---|
[b73e57b] | 954 | (_level) = sparc_disable_interrupts() |
---|
[80f7732] | 955 | |
---|
[4bafde5] | 956 | /** |
---|
[1362b7a] | 957 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 958 | * This indicates the end of a critical section. The parameter |
---|
| 959 | * _level is not modified. |
---|
[7908ba5b] | 960 | */ |
---|
| 961 | #define _CPU_ISR_Enable( _level ) \ |
---|
| 962 | sparc_enable_interrupts( _level ) |
---|
[e9dba243] | 963 | |
---|
[4bafde5] | 964 | /** |
---|
[1362b7a] | 965 | * This temporarily restores the interrupt to _level before immediately |
---|
| 966 | * disabling them again. This is used to divide long critical |
---|
| 967 | * sections into two or more parts. The parameter _level is not |
---|
| 968 | * modified. |
---|
[7908ba5b] | 969 | */ |
---|
| 970 | #define _CPU_ISR_Flash( _level ) \ |
---|
| 971 | sparc_flash_interrupts( _level ) |
---|
[80f7732] | 972 | |
---|
[4bafde5] | 973 | /** |
---|
[1362b7a] | 974 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 975 | * actually provides. Currently, interrupt levels which do not |
---|
| 976 | * map onto the CPU in a straight fashion are undefined. |
---|
[7908ba5b] | 977 | */ |
---|
| 978 | #define _CPU_ISR_Set_level( _newlevel ) \ |
---|
[b73e57b] | 979 | sparc_enable_interrupts( _newlevel << 8) |
---|
[80f7732] | 980 | |
---|
[4bafde5] | 981 | /** |
---|
[1362b7a] | 982 | * @brief Obtain the current interrupt disable level. |
---|
[4bafde5] | 983 | * |
---|
[1362b7a] | 984 | * This method is invoked to return the current interrupt disable level. |
---|
[4bafde5] | 985 | * |
---|
[1362b7a] | 986 | * @return This method returns the current interrupt disable level. |
---|
| 987 | */ |
---|
[2a0a6851] | 988 | uint32_t _CPU_ISR_Get_level( void ); |
---|
[80f7732] | 989 | |
---|
[7908ba5b] | 990 | /* end of ISR handler macros */ |
---|
| 991 | |
---|
| 992 | /* Context handler macros */ |
---|
| 993 | |
---|
[4bafde5] | 994 | /** |
---|
[1362b7a] | 995 | * Initialize the context to a state suitable for starting a |
---|
| 996 | * task after a context restore operation. Generally, this |
---|
| 997 | * involves: |
---|
[7908ba5b] | 998 | * |
---|
[1362b7a] | 999 | * - setting a starting address |
---|
| 1000 | * - preparing the stack |
---|
| 1001 | * - preparing the stack and frame pointers |
---|
| 1002 | * - setting the proper interrupt level in the context |
---|
| 1003 | * - initializing the floating point context |
---|
[4bafde5] | 1004 | * |
---|
| 1005 | * @param[in] the_context points to the context area |
---|
| 1006 | * @param[in] stack_base is the low address of the allocated stack area |
---|
| 1007 | * @param[in] size is the size of the stack area in bytes |
---|
| 1008 | * @param[in] new_level is the interrupt level for the task |
---|
| 1009 | * @param[in] entry_point is the task's entry point |
---|
| 1010 | * @param[in] is_fp is set to TRUE if the task is a floating point task |
---|
[022851a] | 1011 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
[7908ba5b] | 1012 | * |
---|
[1362b7a] | 1013 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
[7908ba5b] | 1014 | */ |
---|
| 1015 | void _CPU_Context_Initialize( |
---|
| 1016 | Context_Control *the_context, |
---|
[2a0a6851] | 1017 | uint32_t *stack_base, |
---|
| 1018 | uint32_t size, |
---|
| 1019 | uint32_t new_level, |
---|
[7908ba5b] | 1020 | void *entry_point, |
---|
[022851a] | 1021 | bool is_fp, |
---|
| 1022 | void *tls_area |
---|
[7908ba5b] | 1023 | ); |
---|
| 1024 | |
---|
[4bafde5] | 1025 | /** |
---|
[1362b7a] | 1026 | * This macro is invoked from _Thread_Handler to do whatever CPU |
---|
| 1027 | * specific magic is required that must be done in the context of |
---|
| 1028 | * the thread when it starts. |
---|
[48816d7] | 1029 | * |
---|
[1362b7a] | 1030 | * On the SPARC, this is setting the frame pointer so GDB is happy. |
---|
| 1031 | * Make GDB stop unwinding at _Thread_Handler, previous register window |
---|
| 1032 | * Frame pointer is 0 and calling address must be a function with starting |
---|
| 1033 | * with a SAVE instruction. If return address is leaf-function (no SAVE) |
---|
| 1034 | * GDB will not look at prev reg window fp. |
---|
[48816d7] | 1035 | * |
---|
[1362b7a] | 1036 | * _Thread_Handler is known to start with SAVE. |
---|
[48816d7] | 1037 | */ |
---|
| 1038 | #define _CPU_Context_Initialization_at_thread_begin() \ |
---|
| 1039 | do { \ |
---|
[e4a2a21f] | 1040 | __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ |
---|
[48816d7] | 1041 | } while (0) |
---|
| 1042 | |
---|
[4bafde5] | 1043 | /** |
---|
[1362b7a] | 1044 | * This routine is responsible for somehow restarting the currently |
---|
| 1045 | * executing task. |
---|
[7908ba5b] | 1046 | * |
---|
[1362b7a] | 1047 | * On the SPARC, this is is relatively painless but requires a small |
---|
| 1048 | * amount of wrapper code before using the regular restore code in |
---|
| 1049 | * of the context switch. |
---|
[7908ba5b] | 1050 | */ |
---|
| 1051 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 1052 | _CPU_Context_restore( (_the_context) ); |
---|
| 1053 | |
---|
[4bafde5] | 1054 | /** |
---|
[1362b7a] | 1055 | * The FP context area for the SPARC is a simple structure and nothing |
---|
| 1056 | * special is required to find the "starting load point" |
---|
[7908ba5b] | 1057 | */ |
---|
| 1058 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 1059 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 1060 | |
---|
[4bafde5] | 1061 | /** |
---|
[1362b7a] | 1062 | * This routine initializes the FP context area passed to it to. |
---|
[7908ba5b] | 1063 | * |
---|
[1362b7a] | 1064 | * The SPARC allows us to use the simple initialization model |
---|
| 1065 | * in which an "initial" FP context was saved into _CPU_Null_fp_context |
---|
| 1066 | * at CPU initialization and it is simply copied into the destination |
---|
| 1067 | * context. |
---|
[7908ba5b] | 1068 | */ |
---|
| 1069 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 1070 | do { \ |
---|
[ada7b9e] | 1071 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
[7908ba5b] | 1072 | } while (0) |
---|
| 1073 | |
---|
| 1074 | /* end of Context handler macros */ |
---|
| 1075 | |
---|
| 1076 | /* Fatal Error manager macros */ |
---|
| 1077 | |
---|
[4bafde5] | 1078 | /** |
---|
[1362b7a] | 1079 | * This routine copies _error into a known place -- typically a stack |
---|
| 1080 | * location or a register, optionally disables interrupts, and |
---|
| 1081 | * halts/stops the CPU. |
---|
[7908ba5b] | 1082 | */ |
---|
[f82752a4] | 1083 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
[7908ba5b] | 1084 | do { \ |
---|
[2a0a6851] | 1085 | uint32_t level; \ |
---|
[7908ba5b] | 1086 | \ |
---|
[b73e57b] | 1087 | level = sparc_disable_interrupts(); \ |
---|
[e4a2a21f] | 1088 | __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ |
---|
[7908ba5b] | 1089 | while (1); /* loop forever */ \ |
---|
| 1090 | } while (0) |
---|
| 1091 | |
---|
| 1092 | /* end of Fatal Error manager macros */ |
---|
| 1093 | |
---|
| 1094 | /* Bitfield handler macros */ |
---|
| 1095 | |
---|
| 1096 | #if ( SPARC_HAS_BITSCAN == 0 ) |
---|
[4bafde5] | 1097 | /** |
---|
[1362b7a] | 1098 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
| 1099 | * CPU model does not have a scan instruction. |
---|
[4bafde5] | 1100 | */ |
---|
| 1101 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 1102 | /** |
---|
[1362b7a] | 1103 | * The SPARC port uses the generic C algorithm for bitfield scan if the |
---|
| 1104 | * CPU model does not have a scan instruction. Thus is needs the generic |
---|
| 1105 | * data table used by that algorithm. |
---|
[4bafde5] | 1106 | */ |
---|
| 1107 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
[7908ba5b] | 1108 | #else |
---|
[4bafde5] | 1109 | #error "scan instruction not currently supported by RTEMS!!" |
---|
[7908ba5b] | 1110 | #endif |
---|
| 1111 | |
---|
| 1112 | /* end of Bitfield handler macros */ |
---|
| 1113 | |
---|
| 1114 | /* functions */ |
---|
| 1115 | |
---|
[4bafde5] | 1116 | /** |
---|
[1362b7a] | 1117 | * @brief SPARC specific initialization. |
---|
[7908ba5b] | 1118 | * |
---|
[1362b7a] | 1119 | * This routine performs CPU dependent initialization. |
---|
[7908ba5b] | 1120 | */ |
---|
[c03e2bc] | 1121 | void _CPU_Initialize(void); |
---|
[7908ba5b] | 1122 | |
---|
[4bafde5] | 1123 | /** |
---|
[1362b7a] | 1124 | * @brief SPARC specific raw ISR installer. |
---|
[7908ba5b] | 1125 | * |
---|
[1362b7a] | 1126 | * This routine installs @a new_handler to be directly called from the trap |
---|
| 1127 | * table. |
---|
[4bafde5] | 1128 | * |
---|
[1362b7a] | 1129 | * @param[in] vector is the vector number |
---|
| 1130 | * @param[in] new_handler is the new ISR handler |
---|
| 1131 | * @param[in] old_handler will contain the old ISR handler |
---|
[7908ba5b] | 1132 | */ |
---|
| 1133 | void _CPU_ISR_install_raw_handler( |
---|
[2a0a6851] | 1134 | uint32_t vector, |
---|
[7908ba5b] | 1135 | proc_ptr new_handler, |
---|
| 1136 | proc_ptr *old_handler |
---|
| 1137 | ); |
---|
| 1138 | |
---|
[4bafde5] | 1139 | /** |
---|
[1362b7a] | 1140 | * @brief SPARC specific RTEMS ISR installer. |
---|
[7908ba5b] | 1141 | * |
---|
[1362b7a] | 1142 | * This routine installs an interrupt vector. |
---|
[4bafde5] | 1143 | * |
---|
[1362b7a] | 1144 | * @param[in] vector is the vector number |
---|
| 1145 | * @param[in] new_handler is the new ISR handler |
---|
| 1146 | * @param[in] old_handler will contain the old ISR handler |
---|
[7908ba5b] | 1147 | */ |
---|
| 1148 | |
---|
| 1149 | void _CPU_ISR_install_vector( |
---|
[2a0a6851] | 1150 | uint32_t vector, |
---|
[7908ba5b] | 1151 | proc_ptr new_handler, |
---|
| 1152 | proc_ptr *old_handler |
---|
| 1153 | ); |
---|
| 1154 | |
---|
[4bafde5] | 1155 | /** |
---|
[1362b7a] | 1156 | * @brief SPARC specific context switch. |
---|
[7908ba5b] | 1157 | * |
---|
[1362b7a] | 1158 | * This routine switches from the run context to the heir context. |
---|
[4bafde5] | 1159 | * |
---|
[1362b7a] | 1160 | * @param[in] run is the currently executing thread |
---|
| 1161 | * @param[in] heir will become the currently executing thread |
---|
[7908ba5b] | 1162 | */ |
---|
| 1163 | void _CPU_Context_switch( |
---|
| 1164 | Context_Control *run, |
---|
| 1165 | Context_Control *heir |
---|
| 1166 | ); |
---|
| 1167 | |
---|
[4bafde5] | 1168 | /** |
---|
[1362b7a] | 1169 | * @brief SPARC specific context restore. |
---|
[7908ba5b] | 1170 | * |
---|
[1362b7a] | 1171 | * This routine is generally used only to restart self in an |
---|
| 1172 | * efficient manner. |
---|
[4bafde5] | 1173 | * |
---|
[1362b7a] | 1174 | * @param[in] new_context is the context to restore |
---|
[7908ba5b] | 1175 | */ |
---|
| 1176 | void _CPU_Context_restore( |
---|
| 1177 | Context_Control *new_context |
---|
[479cbaf8] | 1178 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
[7908ba5b] | 1179 | |
---|
[7c0bd74] | 1180 | /** |
---|
| 1181 | * @brief The pointer to the current per-CPU control is available via register |
---|
| 1182 | * g6. |
---|
| 1183 | */ |
---|
[774ee002] | 1184 | register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); |
---|
[7c0bd74] | 1185 | |
---|
| 1186 | #define _CPU_Get_current_per_CPU_control() ( _SPARC_Per_CPU_current ) |
---|
| 1187 | |
---|
[06dcaf0] | 1188 | #if defined(RTEMS_SMP) |
---|
[53e008b] | 1189 | uint32_t _CPU_SMP_Initialize( void ); |
---|
| 1190 | |
---|
| 1191 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
| 1192 | |
---|
| 1193 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
[4627fcd] | 1194 | |
---|
[8df1f408] | 1195 | #if defined(__leon__) && !defined(RTEMS_PARAVIRT) |
---|
[67a7a2c] | 1196 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
| 1197 | { |
---|
| 1198 | return _LEON3_Get_current_processor(); |
---|
| 1199 | } |
---|
| 1200 | #else |
---|
| 1201 | uint32_t _CPU_SMP_Get_current_processor( void ); |
---|
| 1202 | #endif |
---|
[39e51758] | 1203 | |
---|
[ca63ae2] | 1204 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
| 1205 | |
---|
[fecaeca1] | 1206 | #if defined(__leon__) |
---|
| 1207 | void _LEON3_Start_multitasking( Context_Control *heir ) |
---|
[54f3476e] | 1208 | RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
---|
[fecaeca1] | 1209 | #define _CPU_Start_multitasking _LEON3_Start_multitasking |
---|
| 1210 | #endif |
---|
[54f3476e] | 1211 | |
---|
[07f6e419] | 1212 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
[2f6108f9] | 1213 | { |
---|
| 1214 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1215 | } |
---|
| 1216 | |
---|
[f7740e97] | 1217 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
[2f6108f9] | 1218 | { |
---|
| 1219 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1220 | } |
---|
[06dcaf0] | 1221 | #endif |
---|
| 1222 | |
---|
[4bafde5] | 1223 | /** |
---|
[1362b7a] | 1224 | * @brief SPARC specific save FPU method. |
---|
[7908ba5b] | 1225 | * |
---|
[1362b7a] | 1226 | * This routine saves the floating point context passed to it. |
---|
[4bafde5] | 1227 | * |
---|
[1362b7a] | 1228 | * @param[in] fp_context_ptr is the area to save into |
---|
[7908ba5b] | 1229 | */ |
---|
| 1230 | void _CPU_Context_save_fp( |
---|
[ada7b9e] | 1231 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1232 | ); |
---|
| 1233 | |
---|
[4bafde5] | 1234 | /** |
---|
[1362b7a] | 1235 | * @brief SPARC specific restore FPU method. |
---|
[7908ba5b] | 1236 | * |
---|
[1362b7a] | 1237 | * This routine restores the floating point context passed to it. |
---|
[4bafde5] | 1238 | * |
---|
[1362b7a] | 1239 | * @param[in] fp_context_ptr is the area to restore from |
---|
[7908ba5b] | 1240 | */ |
---|
| 1241 | void _CPU_Context_restore_fp( |
---|
[ada7b9e] | 1242 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1243 | ); |
---|
| 1244 | |
---|
[39993d6] | 1245 | static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) |
---|
| 1246 | { |
---|
| 1247 | /* TODO */ |
---|
| 1248 | } |
---|
| 1249 | |
---|
| 1250 | static inline void _CPU_Context_validate( uintptr_t pattern ) |
---|
| 1251 | { |
---|
| 1252 | while (1) { |
---|
| 1253 | /* TODO */ |
---|
| 1254 | } |
---|
| 1255 | } |
---|
| 1256 | |
---|
[815994f] | 1257 | typedef struct { |
---|
| 1258 | uint32_t trap; |
---|
| 1259 | CPU_Interrupt_frame *isf; |
---|
| 1260 | } CPU_Exception_frame; |
---|
| 1261 | |
---|
| 1262 | void _BSP_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
| 1263 | |
---|
| 1264 | static inline void _CPU_Exception_frame_print( |
---|
| 1265 | const CPU_Exception_frame *frame |
---|
| 1266 | ) |
---|
| 1267 | { |
---|
| 1268 | _BSP_Exception_frame_print( frame ); |
---|
| 1269 | } |
---|
| 1270 | |
---|
[4bafde5] | 1271 | /** |
---|
[1362b7a] | 1272 | * @brief SPARC specific method to endian swap an uint32_t. |
---|
[7908ba5b] | 1273 | * |
---|
[1362b7a] | 1274 | * The following routine swaps the endian format of an unsigned int. |
---|
| 1275 | * It must be static because it is referenced indirectly. |
---|
[7908ba5b] | 1276 | * |
---|
[1362b7a] | 1277 | * @param[in] value is the value to endian swap |
---|
[4bafde5] | 1278 | * |
---|
[1362b7a] | 1279 | * This version will work on any processor, but if you come across a better |
---|
| 1280 | * way for the SPARC PLEASE use it. The most common way to swap a 32-bit |
---|
| 1281 | * entity as shown below is not any more efficient on the SPARC. |
---|
[7908ba5b] | 1282 | * |
---|
[1362b7a] | 1283 | * - swap least significant two bytes with 16-bit rotate |
---|
| 1284 | * - swap upper and lower 16-bits |
---|
| 1285 | * - swap most significant two bytes with 16-bit rotate |
---|
[7908ba5b] | 1286 | * |
---|
[1362b7a] | 1287 | * It is not obvious how the SPARC can do significantly better than the |
---|
| 1288 | * generic code. gcc 2.7.0 only generates about 12 instructions for the |
---|
| 1289 | * following code at optimization level four (i.e. -O4). |
---|
[7908ba5b] | 1290 | */ |
---|
[ec8973ed] | 1291 | static inline uint32_t CPU_swap_u32( |
---|
| 1292 | uint32_t value |
---|
[7908ba5b] | 1293 | ) |
---|
| 1294 | { |
---|
[2a0a6851] | 1295 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[80f7732] | 1296 | |
---|
[7908ba5b] | 1297 | byte4 = (value >> 24) & 0xff; |
---|
| 1298 | byte3 = (value >> 16) & 0xff; |
---|
| 1299 | byte2 = (value >> 8) & 0xff; |
---|
| 1300 | byte1 = value & 0xff; |
---|
[80f7732] | 1301 | |
---|
[7908ba5b] | 1302 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
| 1303 | return( swapped ); |
---|
| 1304 | } |
---|
| 1305 | |
---|
[4bafde5] | 1306 | /** |
---|
[1362b7a] | 1307 | * @brief SPARC specific method to endian swap an uint16_t. |
---|
[4bafde5] | 1308 | * |
---|
[1362b7a] | 1309 | * The following routine swaps the endian format of a uint16_t. |
---|
[4bafde5] | 1310 | * |
---|
[1362b7a] | 1311 | * @param[in] value is the value to endian swap |
---|
[4bafde5] | 1312 | */ |
---|
[7908ba5b] | 1313 | #define CPU_swap_u16( value ) \ |
---|
| 1314 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1315 | |
---|
[24bf11e] | 1316 | typedef uint32_t CPU_Counter_ticks; |
---|
| 1317 | |
---|
[a4bc90af] | 1318 | typedef CPU_Counter_ticks (*SPARC_Counter_difference)( |
---|
| 1319 | CPU_Counter_ticks second, |
---|
| 1320 | CPU_Counter_ticks first |
---|
| 1321 | ); |
---|
| 1322 | |
---|
| 1323 | /* |
---|
| 1324 | * The SPARC processors supported by RTEMS have no built-in CPU counter |
---|
| 1325 | * support. We have to use some hardware counter module for this purpose. The |
---|
| 1326 | * BSP must provide a 32-bit register which contains the current CPU counter |
---|
| 1327 | * value and a function for the difference calculation. It can use for example |
---|
| 1328 | * the GPTIMER instance used for the clock driver. |
---|
| 1329 | */ |
---|
| 1330 | typedef struct { |
---|
| 1331 | volatile const CPU_Counter_ticks *counter_register; |
---|
| 1332 | SPARC_Counter_difference counter_difference; |
---|
| 1333 | } SPARC_Counter; |
---|
| 1334 | |
---|
| 1335 | extern SPARC_Counter _SPARC_Counter; |
---|
| 1336 | |
---|
| 1337 | /* |
---|
| 1338 | * Returns always a value of one regardless of the parameters. This prevents |
---|
| 1339 | * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe |
---|
| 1340 | * default. |
---|
| 1341 | */ |
---|
| 1342 | CPU_Counter_ticks _SPARC_Counter_difference_default( |
---|
| 1343 | CPU_Counter_ticks second, |
---|
| 1344 | CPU_Counter_ticks first |
---|
| 1345 | ); |
---|
| 1346 | |
---|
| 1347 | static inline bool _SPARC_Counter_is_default( void ) |
---|
| 1348 | { |
---|
| 1349 | return _SPARC_Counter.counter_difference |
---|
| 1350 | == _SPARC_Counter_difference_default; |
---|
| 1351 | } |
---|
| 1352 | |
---|
| 1353 | static inline void _SPARC_Counter_initialize( |
---|
| 1354 | volatile const CPU_Counter_ticks *counter_register, |
---|
| 1355 | SPARC_Counter_difference counter_difference |
---|
| 1356 | ) |
---|
| 1357 | { |
---|
| 1358 | _SPARC_Counter.counter_register = counter_register; |
---|
| 1359 | _SPARC_Counter.counter_difference = counter_difference; |
---|
| 1360 | } |
---|
| 1361 | |
---|
| 1362 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
| 1363 | { |
---|
| 1364 | return *_SPARC_Counter.counter_register; |
---|
| 1365 | } |
---|
[24bf11e] | 1366 | |
---|
| 1367 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 1368 | CPU_Counter_ticks second, |
---|
| 1369 | CPU_Counter_ticks first |
---|
| 1370 | ) |
---|
| 1371 | { |
---|
[a4bc90af] | 1372 | return (*_SPARC_Counter.counter_difference)( second, first ); |
---|
[24bf11e] | 1373 | } |
---|
| 1374 | |
---|
[0edbe88] | 1375 | #endif /* ASM */ |
---|
[7908ba5b] | 1376 | |
---|
| 1377 | #ifdef __cplusplus |
---|
| 1378 | } |
---|
| 1379 | #endif |
---|
| 1380 | |
---|
| 1381 | #endif |
---|