source: rtems/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h @ a660e9dc

Last change on this file since a660e9dc was a660e9dc, checked in by Sebastian Huber <sebastian.huber@…>, on 09/08/22 at 08:37:05

Do not use RTEMS_INLINE_ROUTINE

Directly use "static inline" which is available in C99 and later. This brings
the RTEMS implementation closer to standard C.

Close #3935.

  • Property mode set to 100644
File size: 9.5 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 * @file
5 *
6 * @brief CPU Port Implementation API
7 */
8
9/*
10 * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR)
11 * Copyright (c) 2013, 2016 embedded brains GmbH
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_SCORE_CPUIMPL_H
36#define _RTEMS_SCORE_CPUIMPL_H
37
38#include <rtems/score/cpu.h>
39
40/**
41 * @defgroup RTEMSScoreCPUSPARC SPARC
42 *
43 * @ingroup RTEMSScoreCPU
44 *
45 * @brief SPARC Architecture Support
46 *
47 * @{
48 */
49
50/** This defines the size of the minimum stack frame. */
51#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
52
53/*
54 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
55 */
56
57/** This macro defines an offset into the ISF for use in assembly. */
58#define ISF_PSR_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
59/** This macro defines an offset into the ISF for use in assembly. */
60#define ISF_PC_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
61/** This macro defines an offset into the ISF for use in assembly. */
62#define ISF_NPC_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08
63/** This macro defines an offset into the ISF for use in assembly. */
64#define ISF_G1_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c
65/** This macro defines an offset into the ISF for use in assembly. */
66#define ISF_G2_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10
67/** This macro defines an offset into the ISF for use in assembly. */
68#define ISF_G3_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14
69/** This macro defines an offset into the ISF for use in assembly. */
70#define ISF_G4_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18
71/** This macro defines an offset into the ISF for use in assembly. */
72#define ISF_G5_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c
73/** This macro defines an offset into the ISF for use in assembly. */
74#define ISF_G7_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24
75/** This macro defines an offset into the ISF for use in assembly. */
76#define ISF_I0_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28
77/** This macro defines an offset into the ISF for use in assembly. */
78#define ISF_I1_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c
79/** This macro defines an offset into the ISF for use in assembly. */
80#define ISF_I2_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30
81/** This macro defines an offset into the ISF for use in assembly. */
82#define ISF_I3_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34
83/** This macro defines an offset into the ISF for use in assembly. */
84#define ISF_I4_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38
85/** This macro defines an offset into the ISF for use in assembly. */
86#define ISF_I5_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c
87/** This macro defines an offset into the ISF for use in assembly. */
88#define ISF_I6_FP_OFFSET       SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40
89/** This macro defines an offset into the ISF for use in assembly. */
90#define ISF_I7_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44
91/** This macro defines an offset into the ISF for use in assembly. */
92#define ISF_Y_OFFSET           SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48
93/** This macro defines an offset into the ISF for use in assembly. */
94#define ISF_TPC_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c
95
96/** This defines the size of the ISF area for use in assembly. */
97#define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50
98
99#define SPARC_FP_CONTEXT_OFFSET_F0_F1 0
100#define SPARC_FP_CONTEXT_OFFSET_F2_F3 8
101#define SPARC_FP_CONTEXT_OFFSET_F4_F5 16
102#define SPARC_FP_CONTEXT_OFFSET_F6_F7 24
103#define SPARC_FP_CONTEXT_OFFSET_F8_F9 32
104#define SPARC_FP_CONTEXT_OFFSET_F10_F11 40
105#define SPARC_FP_CONTEXT_OFFSET_F12_F13 48
106#define SPARC_FP_CONTEXT_OFFSET_F14_F15 56
107#define SPARC_FP_CONTEXT_OFFSET_F16_F17 64
108#define SPARC_FP_CONTEXT_OFFSET_F18_F19 72
109#define SPARC_FP_CONTEXT_OFFSET_F20_F21 80
110#define SPARC_FP_CONTEXT_OFFSET_F22_F23 88
111#define SPARC_FP_CONTEXT_OFFSET_F24_F25 96
112#define SPARC_FP_CONTEXT_OFFSET_F26_F27 104
113#define SPARC_FP_CONTEXT_OFFSET_F28_F29 112
114#define SPARC_FP_CONTEXT_OFFSET_F30_F31 120
115#define SPARC_FP_CONTEXT_OFFSET_FSR 128
116
117#if ( SPARC_HAS_FPU == 1 )
118  #define CPU_PER_CPU_CONTROL_SIZE 8
119#else
120  #define CPU_PER_CPU_CONTROL_SIZE 0
121#endif
122
123#if ( SPARC_HAS_FPU == 1 )
124  /**
125   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
126   * Per_CPU_Control begin.
127   */
128  #define SPARC_PER_CPU_FSR_OFFSET 0
129
130  #if defined(SPARC_USE_LAZY_FP_SWITCH)
131    /**
132     * @brief Offset of the CPU_Per_CPU_control::fp_owner field relative to the
133     * Per_CPU_Control begin.
134     */
135    #define SPARC_PER_CPU_FP_OWNER_OFFSET 4
136  #endif
137#endif
138
139#define SPARC_REGISTER_WINDOW_OFFSET_LOCAL( i ) ( ( i ) * 4 )
140#define SPARC_REGISTER_WINDOW_OFFSET_INPUT( i ) ( ( i ) * 4 + 32 )
141#define SPARC_REGISTER_WINDOW_SIZE 64
142
143#define SPARC_EXCEPTION_OFFSET_PSR 0
144#define SPARC_EXCEPTION_OFFSET_PC 4
145#define SPARC_EXCEPTION_OFFSET_NPC 8
146#define SPARC_EXCEPTION_OFFSET_TRAP 12
147#define SPARC_EXCEPTION_OFFSET_WIM 16
148#define SPARC_EXCEPTION_OFFSET_Y 20
149#define SPARC_EXCEPTION_OFFSET_GLOBAL( i ) ( ( i ) * 4 + 24 )
150#define SPARC_EXCEPTION_OFFSET_OUTPUT( i ) ( ( i ) * 4 + 56 )
151#define SPARC_EXCEPTION_OFFSET_WINDOWS( i ) ( ( i ) * 64 + 88 )
152
153#if SPARC_HAS_FPU == 1
154#define SPARC_EXCEPTION_OFFSET_FSR 536
155#define SPARC_EXCEPTION_OFFSET_FP( i ) ( ( i ) * 8 + 544 )
156#define SPARC_EXCEPTION_FRAME_SIZE 672
157#else
158#define SPARC_EXCEPTION_FRAME_SIZE 536
159#endif
160
161#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
162#define SPARC_FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
163#define SPARC_FP_FRAME_OFFSET_F2_F3 (SPARC_FP_FRAME_OFFSET_FO_F1 + 8)
164#define SPARC_FP_FRAME_OFFSET_F4_F5 (SPARC_FP_FRAME_OFFSET_F2_F3 + 8)
165#define SPARC_FP_FRAME_OFFSET_F6_F7 (SPARC_FP_FRAME_OFFSET_F4_F5 + 8)
166#define SPARC_FP_FRAME_OFFSET_F8_F9 (SPARC_FP_FRAME_OFFSET_F6_F7 + 8)
167#define SPARC_FP_FRAME_OFFSET_F1O_F11 (SPARC_FP_FRAME_OFFSET_F8_F9 + 8)
168#define SPARC_FP_FRAME_OFFSET_F12_F13 (SPARC_FP_FRAME_OFFSET_F1O_F11 + 8)
169#define SPARC_FP_FRAME_OFFSET_F14_F15 (SPARC_FP_FRAME_OFFSET_F12_F13 + 8)
170#define SPARC_FP_FRAME_OFFSET_F16_F17 (SPARC_FP_FRAME_OFFSET_F14_F15 + 8)
171#define SPARC_FP_FRAME_OFFSET_F18_F19 (SPARC_FP_FRAME_OFFSET_F16_F17 + 8)
172#define SPARC_FP_FRAME_OFFSET_F2O_F21 (SPARC_FP_FRAME_OFFSET_F18_F19 + 8)
173#define SPARC_FP_FRAME_OFFSET_F22_F23 (SPARC_FP_FRAME_OFFSET_F2O_F21 + 8)
174#define SPARC_FP_FRAME_OFFSET_F24_F25 (SPARC_FP_FRAME_OFFSET_F22_F23 + 8)
175#define SPARC_FP_FRAME_OFFSET_F26_F27 (SPARC_FP_FRAME_OFFSET_F24_F25 + 8)
176#define SPARC_FP_FRAME_OFFSET_F28_F29 (SPARC_FP_FRAME_OFFSET_F26_F27 + 8)
177#define SPARC_FP_FRAME_OFFSET_F3O_F31 (SPARC_FP_FRAME_OFFSET_F28_F29 + 8)
178#define SPARC_FP_FRAME_OFFSET_FSR (SPARC_FP_FRAME_OFFSET_F3O_F31 + 8)
179#define SPARC_FP_FRAME_SIZE (SPARC_FP_FRAME_OFFSET_FSR + 8)
180#endif
181
182#ifndef ASM
183
184#ifdef __cplusplus
185extern "C" {
186#endif
187
188typedef struct {
189#if ( SPARC_HAS_FPU == 1 )
190  /**
191   * @brief Memory location to store the FSR register during interrupt
192   * processing.
193   *
194   * This is a write-only field.  The FSR is written to force a completion of
195   * floating point operations in progress.
196   */
197  uint32_t fsr;
198
199#if defined(SPARC_USE_LAZY_FP_SWITCH)
200  /**
201   * @brief The current floating point owner.
202   */
203  struct _Thread_Control *fp_owner;
204#else
205  /* See Per_CPU_Control::Interrupt_frame */
206  uint32_t reserved_for_alignment_of_interrupt_frame;
207#endif
208#endif
209} CPU_Per_CPU_control;
210
211/**
212 * @brief The pointer to the current per-CPU control is available via register
213 * g6.
214 */
215register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" );
216
217#define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current
218
219#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing )
220
221RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
222
223void _CPU_Context_volatile_clobber( uintptr_t pattern );
224
225void _CPU_Context_validate( uintptr_t pattern );
226
227static inline void _CPU_Instruction_illegal( void )
228{
229  __asm__ volatile ( "unimp 0" );
230}
231
232static inline void _CPU_Instruction_no_operation( void )
233{
234  __asm__ volatile ( "nop" );
235}
236
237static inline void _CPU_Use_thread_local_storage(
238  const Context_Control *context
239)
240{
241   register uint32_t g7 __asm__( "g7" );
242
243   g7 = context->g7;
244
245   /* Make sure that the register assignment is not optimized away */
246   __asm__ volatile ( "" : : "r" ( g7 ) );
247}
248
249#ifdef __cplusplus
250}
251#endif
252
253#endif /* ASM */
254
255/** @} */
256
257#endif /* _RTEMS_SCORE_CPUIMPL_H */
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