source: rtems/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h @ 227b145

5
Last change on this file since 227b145 was 227b145, checked in by Daniel Hellstrom <daniel@…>, on Aug 31, 2018 at 6:56:08 AM

sparc: clang AS does no accept UNIMP without argument

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR)
9 * Copyright (c) 2013, 2016 embedded brains GmbH
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.org/license/LICENSE.
14 */
15
16#ifndef _RTEMS_SCORE_CPUIMPL_H
17#define _RTEMS_SCORE_CPUIMPL_H
18
19#include <rtems/score/cpu.h>
20
21/** This defines the size of the minimum stack frame. */
22#define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60
23
24/*
25 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
26 */
27
28/** This macro defines an offset into the ISF for use in assembly. */
29#define ISF_PSR_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00
30/** This macro defines an offset into the ISF for use in assembly. */
31#define ISF_PC_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04
32/** This macro defines an offset into the ISF for use in assembly. */
33#define ISF_NPC_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08
34/** This macro defines an offset into the ISF for use in assembly. */
35#define ISF_G1_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c
36/** This macro defines an offset into the ISF for use in assembly. */
37#define ISF_G2_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10
38/** This macro defines an offset into the ISF for use in assembly. */
39#define ISF_G3_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14
40/** This macro defines an offset into the ISF for use in assembly. */
41#define ISF_G4_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18
42/** This macro defines an offset into the ISF for use in assembly. */
43#define ISF_G5_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c
44/** This macro defines an offset into the ISF for use in assembly. */
45#define ISF_G7_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24
46/** This macro defines an offset into the ISF for use in assembly. */
47#define ISF_I0_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28
48/** This macro defines an offset into the ISF for use in assembly. */
49#define ISF_I1_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c
50/** This macro defines an offset into the ISF for use in assembly. */
51#define ISF_I2_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30
52/** This macro defines an offset into the ISF for use in assembly. */
53#define ISF_I3_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34
54/** This macro defines an offset into the ISF for use in assembly. */
55#define ISF_I4_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38
56/** This macro defines an offset into the ISF for use in assembly. */
57#define ISF_I5_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c
58/** This macro defines an offset into the ISF for use in assembly. */
59#define ISF_I6_FP_OFFSET       SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40
60/** This macro defines an offset into the ISF for use in assembly. */
61#define ISF_I7_OFFSET          SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44
62/** This macro defines an offset into the ISF for use in assembly. */
63#define ISF_Y_OFFSET           SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48
64/** This macro defines an offset into the ISF for use in assembly. */
65#define ISF_TPC_OFFSET         SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c
66
67/** This defines the size of the ISF area for use in assembly. */
68#define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50
69
70#define SPARC_FP_CONTEXT_OFFSET_F0_F1 0
71#define SPARC_FP_CONTEXT_OFFSET_F2_F3 8
72#define SPARC_FP_CONTEXT_OFFSET_F4_F5 16
73#define SPARC_FP_CONTEXT_OFFSET_F6_F7 24
74#define SPARC_FP_CONTEXT_OFFSET_F8_F9 32
75#define SPARC_FP_CONTEXT_OFFSET_F10_F11 40
76#define SPARC_FP_CONTEXT_OFFSET_F12_F13 48
77#define SPARC_FP_CONTEXT_OFFSET_F14_F15 56
78#define SPARC_FP_CONTEXT_OFFSET_F16_F17 64
79#define SPARC_FP_CONTEXT_OFFSET_F18_F19 72
80#define SPARC_FP_CONTEXT_OFFSET_F20_F21 80
81#define SPARC_FP_CONTEXT_OFFSET_F22_F23 88
82#define SPARC_FP_CONTEXT_OFFSET_F24_F25 96
83#define SPARC_FP_CONTEXT_OFFSET_F26_F27 104
84#define SPARC_FP_CONTEXT_OFFSET_F28_F29 112
85#define SPARC_FP_CONTEXT_OFFSET_F30_F31 120
86#define SPARC_FP_CONTEXT_OFFSET_FSR 128
87
88#if ( SPARC_HAS_FPU == 1 )
89  #define CPU_PER_CPU_CONTROL_SIZE 8
90#else
91  #define CPU_PER_CPU_CONTROL_SIZE 0
92#endif
93
94#if ( SPARC_HAS_FPU == 1 )
95  /**
96   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
97   * Per_CPU_Control begin.
98   */
99  #define SPARC_PER_CPU_FSR_OFFSET 0
100
101  #if defined(SPARC_USE_LAZY_FP_SWITCH)
102    /**
103     * @brief Offset of the CPU_Per_CPU_control::fp_owner field relative to the
104     * Per_CPU_Control begin.
105     */
106    #define SPARC_PER_CPU_FP_OWNER_OFFSET 4
107  #endif
108#endif
109
110#ifndef ASM
111
112#ifdef __cplusplus
113extern "C" {
114#endif
115
116typedef struct {
117#if ( SPARC_HAS_FPU == 1 )
118  /**
119   * @brief Memory location to store the FSR register during interrupt
120   * processing.
121   *
122   * This is a write-only field.  The FSR is written to force a completion of
123   * floating point operations in progress.
124   */
125  uint32_t fsr;
126
127#if defined(SPARC_USE_LAZY_FP_SWITCH)
128  /**
129   * @brief The current floating point owner.
130   */
131  struct _Thread_Control *fp_owner;
132#else
133  /* See Per_CPU_Control::Interrupt_frame */
134  uint32_t reserved_for_alignment_of_interrupt_frame;
135#endif
136#endif
137} CPU_Per_CPU_control;
138
139/**
140 * @brief The pointer to the current per-CPU control is available via register
141 * g6.
142 */
143register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" );
144
145#define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current
146
147#define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing )
148
149void _CPU_Context_volatile_clobber( uintptr_t pattern );
150
151void _CPU_Context_validate( uintptr_t pattern );
152
153RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
154{
155  __asm__ volatile ( "unimp 0" );
156}
157
158RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
159{
160  __asm__ volatile ( "nop" );
161}
162
163#ifdef __cplusplus
164}
165#endif
166
167#endif /* ASM */
168
169#endif /* _RTEMS_SCORE_CPUIMPL_H */
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