[df63fbd1] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief CPU Port Implementation API |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[c539a865] | 8 | * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR) |
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[82d30a3] | 9 | * Copyright (c) 2013, 2016 embedded brains GmbH |
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[7790d95f] | 10 | * |
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[df63fbd1] | 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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| 13 | * http://www.rtems.org/license/LICENSE. |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef _RTEMS_SCORE_CPUIMPL_H |
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| 17 | #define _RTEMS_SCORE_CPUIMPL_H |
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| 18 | |
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| 19 | #include <rtems/score/cpu.h> |
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| 20 | |
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[c539a865] | 21 | /** This defines the size of the minimum stack frame. */ |
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| 22 | #define SPARC_MINIMUM_STACK_FRAME_SIZE 0x60 |
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| 23 | |
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| 24 | /* |
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| 25 | * Offsets of fields with CPU_Interrupt_frame for assembly routines. |
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| 26 | */ |
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| 27 | |
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| 28 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 29 | #define ISF_PSR_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x00 |
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| 30 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 31 | #define ISF_PC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x04 |
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| 32 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 33 | #define ISF_NPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x08 |
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| 34 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 35 | #define ISF_G1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x0c |
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| 36 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 37 | #define ISF_G2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x10 |
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| 38 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 39 | #define ISF_G3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x14 |
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| 40 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 41 | #define ISF_G4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x18 |
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| 42 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 43 | #define ISF_G5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x1c |
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| 44 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 45 | #define ISF_G7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x24 |
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| 46 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 47 | #define ISF_I0_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x28 |
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| 48 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 49 | #define ISF_I1_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x2c |
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| 50 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 51 | #define ISF_I2_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x30 |
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| 52 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 53 | #define ISF_I3_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x34 |
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| 54 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 55 | #define ISF_I4_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x38 |
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| 56 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 57 | #define ISF_I5_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x3c |
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| 58 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 59 | #define ISF_I6_FP_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x40 |
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| 60 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 61 | #define ISF_I7_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x44 |
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| 62 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 63 | #define ISF_Y_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x48 |
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| 64 | /** This macro defines an offset into the ISF for use in assembly. */ |
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| 65 | #define ISF_TPC_OFFSET SPARC_MINIMUM_STACK_FRAME_SIZE + 0x4c |
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| 66 | |
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| 67 | /** This defines the size of the ISF area for use in assembly. */ |
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| 68 | #define CPU_INTERRUPT_FRAME_SIZE SPARC_MINIMUM_STACK_FRAME_SIZE + 0x50 |
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| 69 | |
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[146adb1] | 70 | #define SPARC_FP_CONTEXT_OFFSET_F0_F1 0 |
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| 71 | #define SPARC_FP_CONTEXT_OFFSET_F2_F3 8 |
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| 72 | #define SPARC_FP_CONTEXT_OFFSET_F4_F5 16 |
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| 73 | #define SPARC_FP_CONTEXT_OFFSET_F6_F7 24 |
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| 74 | #define SPARC_FP_CONTEXT_OFFSET_F8_F9 32 |
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| 75 | #define SPARC_FP_CONTEXT_OFFSET_F10_F11 40 |
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| 76 | #define SPARC_FP_CONTEXT_OFFSET_F12_F13 48 |
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| 77 | #define SPARC_FP_CONTEXT_OFFSET_F14_F15 56 |
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| 78 | #define SPARC_FP_CONTEXT_OFFSET_F16_F17 64 |
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| 79 | #define SPARC_FP_CONTEXT_OFFSET_F18_F19 72 |
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| 80 | #define SPARC_FP_CONTEXT_OFFSET_F20_F21 80 |
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| 81 | #define SPARC_FP_CONTEXT_OFFSET_F22_F23 88 |
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| 82 | #define SPARC_FP_CONTEXT_OFFSET_F24_F25 96 |
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| 83 | #define SPARC_FP_CONTEXT_OFFSET_F26_F27 104 |
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| 84 | #define SPARC_FP_CONTEXT_OFFSET_F28_F29 112 |
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| 85 | #define SPARC_FP_CONTEXT_OFFSET_F30_F31 120 |
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| 86 | #define SPARC_FP_CONTEXT_OFFSET_FSR 128 |
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| 87 | |
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[82d30a3] | 88 | #if ( SPARC_HAS_FPU == 1 ) |
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| 89 | #define CPU_PER_CPU_CONTROL_SIZE 8 |
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| 90 | #else |
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[c11ac2d5] | 91 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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[82d30a3] | 92 | #endif |
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| 93 | |
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| 94 | #if ( SPARC_HAS_FPU == 1 ) |
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| 95 | /** |
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| 96 | * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the |
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| 97 | * Per_CPU_Control begin. |
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| 98 | */ |
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[c11ac2d5] | 99 | #define SPARC_PER_CPU_FSR_OFFSET 0 |
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[146adb1] | 100 | |
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| 101 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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| 102 | /** |
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| 103 | * @brief Offset of the CPU_Per_CPU_control::fp_owner field relative to the |
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| 104 | * Per_CPU_Control begin. |
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| 105 | */ |
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| 106 | #define SPARC_PER_CPU_FP_OWNER_OFFSET 4 |
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| 107 | #endif |
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[82d30a3] | 108 | #endif |
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| 109 | |
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[df63fbd1] | 110 | #ifndef ASM |
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| 111 | |
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| 112 | #ifdef __cplusplus |
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| 113 | extern "C" { |
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| 114 | #endif |
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| 115 | |
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[82d30a3] | 116 | typedef struct { |
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| 117 | #if ( SPARC_HAS_FPU == 1 ) |
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| 118 | /** |
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| 119 | * @brief Memory location to store the FSR register during interrupt |
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| 120 | * processing. |
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| 121 | * |
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| 122 | * This is a write-only field. The FSR is written to force a completion of |
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| 123 | * floating point operations in progress. |
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| 124 | */ |
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| 125 | uint32_t fsr; |
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[c11ac2d5] | 126 | |
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[146adb1] | 127 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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| 128 | /** |
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| 129 | * @brief The current floating point owner. |
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| 130 | */ |
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| 131 | struct _Thread_Control *fp_owner; |
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| 132 | #else |
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[c11ac2d5] | 133 | /* See Per_CPU_Control::Interrupt_frame */ |
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| 134 | uint32_t reserved_for_alignment_of_interrupt_frame; |
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[82d30a3] | 135 | #endif |
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[146adb1] | 136 | #endif |
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[82d30a3] | 137 | } CPU_Per_CPU_control; |
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| 138 | |
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[58bced6] | 139 | /** |
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| 140 | * @brief The pointer to the current per-CPU control is available via register |
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| 141 | * g6. |
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| 142 | */ |
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| 143 | register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); |
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| 144 | |
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| 145 | #define _CPU_Get_current_per_CPU_control() _SPARC_Per_CPU_current |
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| 146 | |
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[7790d95f] | 147 | #define _CPU_Get_thread_executing() ( _SPARC_Per_CPU_current->executing ) |
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| 148 | |
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[42f2fdfd] | 149 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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| 150 | |
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| 151 | void _CPU_Context_validate( uintptr_t pattern ); |
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| 152 | |
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[3a646426] | 153 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) |
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| 154 | { |
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| 155 | __asm__ volatile ( "unimp" ); |
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| 156 | } |
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| 157 | |
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[b74353e] | 158 | RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) |
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| 159 | { |
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| 160 | __asm__ volatile ( "nop" ); |
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| 161 | } |
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| 162 | |
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[df63fbd1] | 163 | #ifdef __cplusplus |
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| 164 | } |
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| 165 | #endif |
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| 166 | |
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| 167 | #endif /* ASM */ |
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| 168 | |
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| 169 | #endif /* _RTEMS_SCORE_CPUIMPL_H */ |
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