source: rtems/cpukit/score/cpu/sparc/include/libcpu/grlib-tn-0018.h @ b2da982

Last change on this file since b2da982 was b2da982, checked in by Daniel Hellstrom <daniel@…>, on 04/21/20 at 09:57:50

leon,tn-0018: work around GRLIB-TN-0018 errata

Overview
========

The errata is worked around in the kernel without requiring toolchain
modifications. It is triggered the JMPL/RETT return from trap instruction
sequence never generated by the compiler and. There are also other
conditions that must must be true to trigger the errata, for example the
instruction that the trap returns to has to be a JMPL instruction. The
errata can only be triggered if certain data is corrected by ECC
(inflicted by radiation), thus it can not be triggered under normal
operation. For more information see:

www.gaisler.com/notes

Affected RTEMS target BSPs:

  • GR712RC
  • UT699
  • UT700/699E

The work around is enabled by defining FIX_LEON3_TN0018 at build time.
After applying the following GCC patch, GCC will set the define when
compiling for an affected multilib:

  • GR712RC (-mcpu=leon3 -mfix-gr712rc)
  • UT700/UT699E (-mpcu=leon3 -mfix-ut700)
  • UT699 (-mcpu=leon -mfix-ut699)

When building for another multilib and TN0018 is still required, it
is possible to enable it on the RTEMS kernel configure line using the
TARGET_CFLAGS (-DFIX_LEON3FT_TN0018) or other by other means.

The following GCC patch sets FIX_LEON3FT_TN0018 for the affected RTEMS
multilibs:

diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h
index 6570590..ddec98c 100644
--- a/gcc/config/sparc/rtemself.h
+++ b/gcc/config/sparc/rtemself.h
@@ -33,6 +33,8 @@

builtin_assert ("system=rtems"); \
if (sparc_fix_b2bst) \

builtin_define ("FIX_LEON3FT_B2BST"); \

+ if (sparc_fix_gr712rc

sparc_fix_ut700 sparc_fix_ut699) \
+ builtin_define ("FIX_LEON3FT_TN0018"); \

} \

while (0)

Workaround Implementation
=========================

In general there are two approaches that the workaround uses:

A) avoid ECC restarting the RETT instruction
B) avoid returning from trap to a JMPL instruction

Where A) comes at a higher performance cost than B), so B) is used
where posssible. B) can be achived for certain returns from trap
handlers if trap entry is controlled by assembly, such as system calls.

A)
A special JMPL/RETT sequence where instruction cache is disabled
temporarily to avoid RETT containing ECC errors, and reading of RETT
source registers to "clean" them from incorrect ECC just before RETT
is executed.

B)
The work around prevents JMPL after system calls (TA instruction) and
modifies assembly code on return from traps jumping back to application
code. Note that for some traps the trapped instruction is always
re-executed and can therefore not trigger the errata, for example the
SAVE instruction causing window overflow or an float instruction causing
FPU disabled trap.

RTEMS SPARC traps workaround implementation:

NAME NOTE TRAP COMMENT

  • window overflow 1 - 0x05 always returns to a SAVE
  • window underflow 1 - 0x06 always returns to a RESTORE
  • interrupt traps 2 - 0x10..1f special rett sequence workaround
  • syscall 3 - 0x80 shutdown system - never returns
  • ABI flush windows 2 - 0x83 special rett sequence workaround
  • syscall_irqdis 4 - 0x89
  • syscall_irqen 4 - 0x8A
  • syscall_irqdis_fp 1 - 0x8B always jumps back to FP instruction
  • syscall_lazy_fp_switch 5 - 0x04 A) jumps back to FP instruction, or to

B) _Internal_error() starting with SAVE

Notes:
1) no workaround needed because trap always returns to non-JMPL instruction
2) workaround implemented by special rett sequence
3) no workaround needed because system call never returns
4) workaround implemented by inserting NOP in system call generation. Thus

fall into 1) when workaround is enabled and no trap handler fix needed.

5) trap handler branches into both 1) and returning to _Internal_error()

which starts with a SAVE and besides since it shuts down the system that
RETT should never be in cache (only executed once) so fix not necessary
in this case.

Any custom trap handlers may also have to be updated. To simplify that,
helper work around assembly code in macros are available in a separate
include file <libcpu/grlib-tn-0018.h>.

Close #4155.
  • Property mode set to 100644
File size: 2.9 KB
Line 
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (C) 2020 Cobham Gailer AB
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/* NOTE: the lda should be on offset 0x18 */
29#if defined(__FIX_LEON3FT_TN0018)
30
31/* LEON3 Cache controller register accessed via ASI 2 */
32#define ASI_CTRL 0x02
33#define CCTRL_IP_BIT 15
34#define CCTRL_ICS 0x3
35
36/*
37 * l3: (out) original cctrl
38 * l4: (out) original cctrl with ics=0
39 * NOTE: This macro modifies psr.icc.
40 */
41.macro TN0018_WAIT_IFLUSH out1 out2
421:
43        ! wait for pending iflush to complete
44        lda     [%g0] ASI_CTRL, \out1
45        srl     \out1, CCTRL_IP_BIT, \out2
46        andcc   \out2, 1, %g0
47        bne     1b
48         andn   \out1, CCTRL_ICS, \out2
49.endm
50
51
52.macro TN0018_WRITE_PSR src
53        wr      \src, %psr
54.endm
55
56/* Prevent following jmp;rett sequence from "re-executing" due to cached RETT or source
57 * registers (l1 and l2) containing bit faults triggering ECC.
58 *
59 * l3: (in) original cctrl
60 * l4: (in) original cctrl with ics=0
61 * NOTE: This macro MUST be immediately followed by the "jmp;rett" pair.
62 */
63.macro TN0018_FIX in1 in2
64        .align  0x20                    ! align the sta for performance
65        sta     \in2, [%g0] ASI_CTRL    ! disable icache
66        nop                             ! delay for sta to have effect on rett
67        or      %l1, %l1, %l1           ! delay + catch rf parity error on l1
68        or      %l2, %l2, %l2           ! delay + catch rf parity error on l2
69        sta     \in1, [%g0] ASI_CTRL     ! re-enable icache after rett
70        nop                             ! delay ensures insn after gets cached
71.endm
72
73#else
74
75.macro TN0018_WAIT_IFLUSH out1 out2
76.endm
77
78.macro TN0018_WRITE_PSR src
79.endm
80
81.macro TN0018_FIX in1 in2
82.endm
83
84#endif
85
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