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cpu_asm.S @ be96cb43

Last change on this file since be96cb43 was be96cb43, checked in by Sebastian Huber <sebastian.huber@…>, on 06/18/21 at 14:44:11

sparc: Simplify trap table initialization

Move _ISR_Handler() to a separate file since it is now only used if a handler
is installed by _CPU_ISR_install_raw_handler().

Statically initialize the traps for external interrupts to use the new
_SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
installed by rtems_interrupt_handler_install() via the BSP-provided
_SPARC_Interrupt_dispatch().

Since the trap table is now fully statically initialized, there is no longer a
dependency on the Cache Manager in the default configuration.

Update #4458.

Property mode set to 100644

File size: 30.4 KB

Line
1	/* cpu_asm.s
2	*
3	* This file contains the basic algorithms for all assembly code used
4	* in an specific CPU port of RTEMS. These algorithms must be implemented
5	* in assembly language.
6	*
7	* COPYRIGHT (c) 1989-2011.
8	* On-Line Applications Research Corporation (OAR).
9	*
10	* Copyright (c) 2014, 2017 embedded brains GmbH
11	*
12	* The license and distribution terms for this file may be
13	* found in the file LICENSE in this distribution or at
14	* http://www.rtems.org/license/LICENSE.
15	*
16	* Ported to ERC32 implementation of the SPARC by On-Line Applications
17	* Research Corporation (OAR) under contract to the European Space
18	* Agency (ESA).
19	*
20	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
21	* European Space Agency.
22	*/
23
24	#include <rtems/asm.h>
25	#include <rtems/score/percpu.h>
26	#include <libcpu/grlib-tn-0018.h>
27
28	/*
29	* void _CPU_Context_switch(
30	* Context_Control *run,
31	* Context_Control *heir
32	* )
33	*
34	* This routine performs a normal non-FP context switch.
35	*/
36
37	.align 4
38	PUBLIC(_CPU_Context_switch)
39	PUBLIC(_CPU_Context_switch_no_return)
40	SYM(_CPU_Context_switch):
41	SYM(_CPU_Context_switch_no_return):
42	st %g5, [%o0 + G5_OFFSET] ! save the global registers
43
44	/*
45	* No need to save the thread pointer %g7 since it is a thread
46	* invariant. It is initialized once in _CPU_Context_Initialize().
47	*/
48
49	std %l0, [%o0 + L0_OFFSET] ! save the local registers
50	SPARC_LEON3FT_B2BST_NOP
51	std %l2, [%o0 + L2_OFFSET]
52	SPARC_LEON3FT_B2BST_NOP
53	std %l4, [%o0 + L4_OFFSET]
54	SPARC_LEON3FT_B2BST_NOP
55	std %l6, [%o0 + L6_OFFSET]
56	SPARC_LEON3FT_B2BST_NOP
57
58	std %i0, [%o0 + I0_OFFSET] ! save the input registers
59	SPARC_LEON3FT_B2BST_NOP
60	std %i2, [%o0 + I2_OFFSET]
61	SPARC_LEON3FT_B2BST_NOP
62	std %i4, [%o0 + I4_OFFSET]
63	SPARC_LEON3FT_B2BST_NOP
64	std %i6, [%o0 + I6_FP_OFFSET]
65	SPARC_LEON3FT_B2BST_NOP
66
67	std %o6, [%o0 + O6_SP_OFFSET] ! save the output registers
68
69	! load the ISR stack nesting prevention flag
70	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
71	! save it a bit later so we do not waste a couple of cycles
72
73	rd %psr, %o2
74	st %o2, [%o0 + PSR_OFFSET] ! save status register
75
76	! Now actually save ISR stack nesting prevention flag
77	st %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
78
79	/*
80	* This is entered from _CPU_Context_restore with:
81	* o1 = context to restore
82	* o2 = psr
83	*/
84
85	PUBLIC(_CPU_Context_restore_heir)
86	SYM(_CPU_Context_restore_heir):
87	/*
88	* Flush all windows with valid contents except the current one.
89	* In examining the set register windows, one may logically divide
90	* the windows into sets (some of which may be empty) based on their
91	* current status:
92	*
93	* + current (i.e. in use),
94	* + used (i.e. a restore would not trap)
95	* + invalid (i.e. 1 in corresponding bit in WIM)
96	* + unused
97	*
98	* Either the used or unused set of windows may be empty.
99	*
100	* NOTE: We assume only one bit is set in the WIM at a time.
101	*
102	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
103	* into sets as follows:
104	*
105	* + 0 - invalid
106	* + 1-4 - unused
107	* + 5 - current
108	* + 6-7 - used
109	*
110	* In this case, we only would save the used windows -- 6 and 7.
111	*
112	* Traps are disabled for the same logical period as in a
113	* flush all windows trap handler.
114	*
115	* Register Usage while saving the windows:
116	* g1 = current PSR
117	* g2 = current wim
118	* g3 = CWP
119	* g4 = wim scratch
120	* g5 = scratch
121	*/
122
123	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
124	andn %o2, SPARC_PSR_ET_MASK, %g1 ! g1 = psr with traps disabled
125	mov %g1, %psr ! ** DISABLE TRAPS **
126	mov %wim, %g2 ! g2 = wim
127	mov 1, %g4
128	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
129
130	save_frame_loop:
131	sll %g4, 1, %g5 ! rotate the "wim" left 1
132	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
133	or %g4, %g5, %g4 ! g4 = wim if we do one restore
134
135	/*
136	* If a restore would not underflow, then continue.
137	*/
138
139	andcc %g4, %g2, %g0 ! Any windows to flush?
140	bnz done_flushing ! No, then continue
141	nop
142
143	restore ! back one window
144
145	/*
146	* Now save the window just as if we overflowed to it.
147	*/
148
149	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
150	SPARC_LEON3FT_B2BST_NOP
151	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
152	SPARC_LEON3FT_B2BST_NOP
153	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
154	SPARC_LEON3FT_B2BST_NOP
155	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
156	SPARC_LEON3FT_B2BST_NOP
157
158	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
159	SPARC_LEON3FT_B2BST_NOP
160	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
161	SPARC_LEON3FT_B2BST_NOP
162	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
163	SPARC_LEON3FT_B2BST_NOP
164	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
165	SPARC_LEON3FT_B2BST_NOP
166
167	ba save_frame_loop
168	nop
169
170	done_flushing:
171
172	! Wait three instructions after the write to PSR before using
173	! non-global registers or instructions affecting the CWP
174	mov %g1, %psr ! restore cwp
175	add %g3, 1, %g2 ! calculate desired WIM
176	and %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
177	mov 1, %g4
178	sll %g4, %g2, %g4 ! g4 = new WIM
179	mov %g4, %wim
180
181	#if defined(RTEMS_SMP)
182	/*
183	* The executing thread no longer executes on this processor. Switch
184	* the stack to the temporary interrupt stack of this processor. Mark
185	* the context of the executing thread as not executing.
186	*/
187	add %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp
188	st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
189
190	! Try to update the is executing indicator of the heir context
191	mov 1, %g1
192
193	.Ltry_update_is_executing:
194
195	swap [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
196	cmp %g1, 0
197	bne .Lcheck_is_executing
198
199	! The next load is in a delay slot, which is all right
200	#endif
201
202	#if defined(SPARC_USE_LAZY_FP_SWITCH)
203	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %g2
204	#endif
205	ld [%o1 + PSR_OFFSET], %g1 ! g1 = heir psr with traps enabled
206	#if defined(SPARC_USE_LAZY_FP_SWITCH)
207	sethi %hi(SPARC_PSR_EF_MASK), %g5
208	cmp %g2, %g0
209	bne,a .Lclear_psr_ef_done
210	andn %g1, %g5, %g1 ! g1 = heir psr w/o PSR[EF]
211	.Lclear_psr_ef_done:
212	#endif
213	andn %g1, SPARC_PSR_CWP_MASK, %g1 ! g1 = heir psr w/o cwp
214	or %g1, %g3, %g1 ! g1 = heir psr with cwp
215	mov %g1, %psr ! restore status register and
216	! ** ENABLE TRAPS **
217
218	ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
219	ld [%o1 + G7_OFFSET], %g7
220
221	! Load thread specific ISR dispatch prevention flag
222	ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
223	! Store it to memory later to use the cycles
224
225	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
226	ldd [%o1 + L2_OFFSET], %l2
227	ldd [%o1 + L4_OFFSET], %l4
228	ldd [%o1 + L6_OFFSET], %l6
229
230	! Now restore thread specific ISR dispatch prevention flag
231	st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
232
233	ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers
234	ldd [%o1 + I2_OFFSET], %i2
235	ldd [%o1 + I4_OFFSET], %i4
236	ldd [%o1 + I6_FP_OFFSET], %i6
237
238	ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers
239
240	jmp %o7 + 8 ! return
241	nop ! delay slot
242
243	#if defined(RTEMS_SMP)
244	.Lcheck_is_executing:
245
246	! Check the is executing indicator of the heir context
247	ld [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
248	cmp %g1, 0
249	beq .Ltry_update_is_executing
250	mov 1, %g1
251
252	! We may have a new heir
253
254	! Read the executing and heir
255	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %g2
256	ld [%g6 + PER_CPU_OFFSET_HEIR], %g4
257
258	! Update the executing only if necessary to avoid cache line
259	! monopolization.
260	cmp %g2, %g4
261	beq .Ltry_update_is_executing
262	mov 1, %g1
263
264	! Calculate the heir context pointer
265	sub %o1, %g2, %g2
266	add %g2, %g4, %o1
267
268	! Update the executing
269	st %g4, [%g6 + PER_CPU_OFFSET_EXECUTING]
270
271	ba .Ltry_update_is_executing
272	mov 1, %g1
273	#endif
274
275	/*
276	* void _CPU_Context_restore(
277	* Context_Control *new_context
278	* )
279	*
280	* This routine is generally used only to perform restart self.
281	*
282	* NOTE: It is unnecessary to reload some registers.
283	*/
284	.align 4
285	PUBLIC(_CPU_Context_restore)
286	SYM(_CPU_Context_restore):
287	save %sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
288	rd %psr, %o2
289	#if defined(RTEMS_SMP)
290	! On SPARC the restore path needs also a valid executing context on SMP
291	! to update the is executing indicator.
292	mov %i0, %o0
293	#endif
294	ba SYM(_CPU_Context_restore_heir)
295	mov %i0, %o1 ! in the delay slot
296
297	/*
298	* void _SPARC_Interrupt_trap()
299	*
300	* This routine provides the RTEMS interrupt management.
301	*
302	* We enter this handler from the 4 instructions in the trap table with
303	* the following registers assumed to be set as shown:
304	*
305	* l0 = PSR
306	* l1 = PC
307	* l2 = nPC
308	* l3 = interrupt vector number (this is not the trap type)
309	*
310	* NOTE: This trap handler is intended to service external interrupts.
311	*/
312
313	.align 4
314	PUBLIC(_SPARC_Interrupt_trap)
315	SYM(_SPARC_Interrupt_trap):
316	/*
317	* Save the globals this block uses.
318	*
319	* These registers are not restored from the locals. Their contents
320	* are saved directly from the locals into the ISF below.
321	*/
322
323	mov %g4, %l4 ! save the globals this block uses
324	mov %g5, %l5
325
326	/*
327	* When at a "window overflow" trap, (wim == (1 << cwp)).
328	* If we get here like that, then process a window overflow.
329	*/
330
331	rd %wim, %g4
332	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
333	! are LS 5 bits ; how convenient :)
334	cmp %g5, 1 ! Is this an invalid window?
335	bne dont_do_the_window ! No, then skip all this stuff
336	! we are using the delay slot
337
338	/*
339	* The following is same as a 1 position right rotate of WIM
340	*/
341
342	srl %g4, 1, %g5 ! g5 = WIM >> 1
343	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
344	! g4 = WIM << (Number Windows - 1)
345	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
346	! (WIM << (Number Windows - 1))
347
348	/*
349	* At this point:
350	*
351	* g4 = the new WIM
352	* g5 is free
353	*/
354
355	/*
356	* Since we are tinkering with the register windows, we need to
357	* make sure that all the required information is in global registers.
358	*/
359
360	save ! Save into the window
361	wr %g4, 0, %wim ! WIM = new WIM
362	nop ! delay slots
363	nop
364	nop
365
366	/*
367	* Now save the window just as if we overflowed to it.
368	*/
369
370	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
371	SPARC_LEON3FT_B2BST_NOP
372	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
373	SPARC_LEON3FT_B2BST_NOP
374	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
375	SPARC_LEON3FT_B2BST_NOP
376	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
377	SPARC_LEON3FT_B2BST_NOP
378
379	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
380	SPARC_LEON3FT_B2BST_NOP
381	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
382	SPARC_LEON3FT_B2BST_NOP
383	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
384	SPARC_LEON3FT_B2BST_NOP
385	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
386
387	restore
388	nop
389
390	dont_do_the_window:
391	/*
392	* Global registers %g4 and %g5 are saved directly from %l4 and
393	* %l5 directly into the ISF below.
394	*/
395
396	/*
397	* Save the state of the interrupted task -- especially the global
398	* registers -- in the Interrupt Stack Frame. Note that the ISF
399	* includes a regular minimum stack frame which will be used if
400	* needed by register window overflow and underflow handlers.
401	*
402	* REGISTERS SAME AS AT _SPARC_Interrupt_trap()
403	*/
404
405	sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
406	! make space for ISF
407
408	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
409	SPARC_LEON3FT_B2BST_NOP
410	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
411	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
412	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
413	SPARC_LEON3FT_B2BST_NOP
414	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
415	SPARC_LEON3FT_B2BST_NOP
416	st %g7, [%sp + ISF_G7_OFFSET] ! save g7
417
418	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
419	SPARC_LEON3FT_B2BST_NOP
420	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
421	SPARC_LEON3FT_B2BST_NOP
422	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
423	SPARC_LEON3FT_B2BST_NOP
424	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
425
426	rd %y, %g1
427	st %g1, [%sp + ISF_Y_OFFSET] ! save y
428
429	/*
430	* Increment ISR nest level and Thread dispatch disable level.
431	*
432	* Register usage for this section:
433	*
434	* l6 = _Thread_Dispatch_disable_level value
435	* l7 = _ISR_Nest_level value
436	*
437	* NOTE: It is assumed that l6 - l7 will be preserved until the ISR
438	* nest and thread dispatch disable levels are unnested.
439	*/
440
441	ld [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
442	ld [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
443
444	add %l7, 1, %l7
445	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
446	SPARC_LEON3FT_B2BST_NOP
447
448	add %l6, 1, %l6
449	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
450
451	#if SPARC_HAS_FPU == 1
452	/*
453	* We cannot use an intermediate value for operations with the PSR[EF]
454	* bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
455	*/
456	sethi %hi(SPARC_PSR_EF_MASK), %l5
457	#endif
458
459	/*
460	* If ISR nest level was zero (now 1), then switch stack.
461	*/
462
463	mov %sp, %fp
464	subcc %l7, 1, %l7 ! outermost interrupt handler?
465	bnz dont_switch_stacks ! No, then do not switch stacks
466
467	#if defined(RTEMS_PROFILING)
468	sethi %hi(_SPARC_Counter), %o5
469	ld [%o5 + %lo(_SPARC_Counter)], %l4
470	call %l4
471	nop
472	mov %o0, %o5
473	#else
474	nop
475	#endif
476
477	ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
478
479	#if SPARC_HAS_FPU == 1
480	/*
481	* Test if the interrupted thread uses the floating point unit
482	* (PSR[EF] == 1). In case it uses the floating point unit, then store
483	* the floating point status register. This has the side-effect that
484	* all pending floating point operations complete before the store
485	* completes. The PSR[EF] bit is restored after the call to the
486	* interrupt handler. Thus post-switch actions (e.g. signal handlers)
487	* and context switch extensions may still corrupt the floating point
488	* context.
489	*/
490	andcc %l0, %l5, %g0
491	beq dont_switch_stacks
492	nop
493	st %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
494	#endif
495
496	dont_switch_stacks:
497	/*
498	* Make sure we have a place on the stack for the window overflow
499	* trap handler to write into. At this point it is safe to
500	* enable traps again.
501	*/
502
503	sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
504
505	/*
506	* Set the PIL in the %psr to mask off interrupts with lower priority.
507	* The original %psr in %l0 is not modified since it will be restored
508	* when the interrupt handler returns.
509	*/
510
511	mov %l0, %g5
512	sll %l3, 8, %g4
513	and %g4, SPARC_PSR_PIL_MASK, %g4
514	andn %l0, SPARC_PSR_PIL_MASK, %g5
515	or %g4, %g5, %g5
516
517	#if SPARC_HAS_FPU == 1
518	/*
519	* Clear the PSR[EF] bit of the interrupted context to ensure that
520	* interrupt service routines cannot corrupt the floating point context.
521	*/
522	andn %g5, %l5, %g5
523	#endif
524
525	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
526
527	/*
528	* Call _SPARC_Interrupt_dispatch( %l3 )
529	*/
530	mov %l3, %o0 ! o0 = 1st arg = vector number
531	call SYM(_SPARC_Interrupt_dispatch)
532	#if defined(RTEMS_PROFILING)
533	mov %o5, %l3 ! save interrupt entry instant
534	#else
535	nop ! delay slot
536	#endif
537
538	#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
539	mov %l0, %g1 ! PSR[EF] value of interrupted context
540	ta SPARC_SWTRAP_IRQDIS_FP ! ** DISABLE INTERRUPTS **
541	#else
542	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
543	#endif
544
545	#if defined(RTEMS_PROFILING)
546	cmp %l7, 0
547	bne profiling_not_outer_most_exit
548	nop
549	call %l4 ! Call _SPARC_Counter.counter_read
550	mov %g1, %l4 ! Save previous interrupt status
551	mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
552	mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
553	call SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
554	mov %g6, %o0 ! o0 = 1st arg = per-CPU control
555	profiling_not_outer_most_exit:
556	#endif
557
558	/*
559	* Decrement ISR nest level and Thread dispatch disable level.
560	*
561	* Register usage for this section:
562	*
563	* o2 = g6->dispatch_necessary value
564	* o3 = g6->isr_dispatch_disable value
565	* l6 = g6->thread_dispatch_disable_level value
566	* l7 = g6->isr_nest_level value
567	*/
568
569	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
570	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
571	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
572	SPARC_LEON3FT_B2BST_NOP
573	sub %l6, 1, %l6
574	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
575
576	/*
577	* Thread dispatching is necessary and allowed if and only if
578	* g6->dispatch_necessary == 1 and
579	* g6->isr_dispatch_disable == 0 and
580	* g6->thread_dispatch_disable_level == 0.
581	*
582	* Otherwise, continue with the simple return.
583	*/
584	xor %o2, 1, %o2
585	or %o2, %l6, %o2
586	orcc %o2, %o3, %o2
587	bnz simple_return
588
589	/*
590	* Switch back on the interrupted tasks stack and add enough room to
591	* invoke the dispatcher. Doing this in the delay slot causes no harm,
592	* since the stack pointer (%sp) is not used in the simple return path.
593	*/
594	sub %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
595
596	isr_dispatch:
597
598	/* Set ISR dispatch disable and thread dispatch disable level to one */
599	mov 1, %l6
600	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
601	st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
602
603	/* Call _Thread_Do_dispatch(), this function will enable interrupts */
604
605	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
606
607	#if defined(SPARC_USE_LAZY_FP_SWITCH)
608	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
609	andcc %l0, %l5, %g0
610	be .Lnon_fp_thread_dispatch
611	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %l6
612
613	/* Set new floating point unit owner to executing thread */
614	st %l6, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
615
616	call SYM(_Thread_Do_dispatch)
617	mov %g6, %o0
618
619	/*
620	* If we are still the floating point unit owner, then reset the
621	* floating point unit owner to NULL, otherwise clear PSR[EF] in the
622	* interrupt frame and let the FP disabled system call do the floating
623	* point context save/restore.
624	*/
625	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %l7
626	cmp %l6, %l7
627	bne,a .Ldisable_fp
628	andn %l0, %l5, %l0
629	st %g0, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
630	ba .Lthread_dispatch_done
631	nop
632	.Ldisable_fp:
633	st %l0, [%fp + ISF_PSR_OFFSET]
634	ba .Lthread_dispatch_done
635	nop
636	.Lnon_fp_thread_dispatch:
637	#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
638	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
639	andcc %l0, %l5, %g0
640	be .Lnon_fp_thread_dispatch
641	nop
642
643	/*
644	* Yes, this is a floating point thread, then save the floating point
645	* context to a new stack frame. Then do the thread dispatch.
646	* Post-switch actions (e.g. signal handlers) and context switch
647	* extensions may safely use the floating point unit.
648	*/
649	sub %sp, SPARC_FP_FRAME_SIZE, %sp
650	std %f0, [%sp + SPARC_FP_FRAME_OFFSET_FO_F1]
651	SPARC_LEON3FT_B2BST_NOP
652	std %f2, [%sp + SPARC_FP_FRAME_OFFSET_F2_F3]
653	SPARC_LEON3FT_B2BST_NOP
654	std %f4, [%sp + SPARC_FP_FRAME_OFFSET_F4_F5]
655	SPARC_LEON3FT_B2BST_NOP
656	std %f6, [%sp + SPARC_FP_FRAME_OFFSET_F6_F7]
657	SPARC_LEON3FT_B2BST_NOP
658	std %f8, [%sp + SPARC_FP_FRAME_OFFSET_F8_F9]
659	SPARC_LEON3FT_B2BST_NOP
660	std %f10, [%sp + SPARC_FP_FRAME_OFFSET_F1O_F11]
661	SPARC_LEON3FT_B2BST_NOP
662	std %f12, [%sp + SPARC_FP_FRAME_OFFSET_F12_F13]
663	SPARC_LEON3FT_B2BST_NOP
664	std %f14, [%sp + SPARC_FP_FRAME_OFFSET_F14_F15]
665	SPARC_LEON3FT_B2BST_NOP
666	std %f16, [%sp + SPARC_FP_FRAME_OFFSET_F16_F17]
667	SPARC_LEON3FT_B2BST_NOP
668	std %f18, [%sp + SPARC_FP_FRAME_OFFSET_F18_F19]
669	SPARC_LEON3FT_B2BST_NOP
670	std %f20, [%sp + SPARC_FP_FRAME_OFFSET_F2O_F21]
671	SPARC_LEON3FT_B2BST_NOP
672	std %f22, [%sp + SPARC_FP_FRAME_OFFSET_F22_F23]
673	SPARC_LEON3FT_B2BST_NOP
674	std %f24, [%sp + SPARC_FP_FRAME_OFFSET_F24_F25]
675	SPARC_LEON3FT_B2BST_NOP
676	std %f26, [%sp + SPARC_FP_FRAME_OFFSET_F26_F27]
677	SPARC_LEON3FT_B2BST_NOP
678	std %f28, [%sp + SPARC_FP_FRAME_OFFSET_F28_F29]
679	SPARC_LEON3FT_B2BST_NOP
680	std %f30, [%sp + SPARC_FP_FRAME_OFFSET_F3O_F31]
681	SPARC_LEON3FT_B2BST_NOP
682	st %fsr, [%sp + SPARC_FP_FRAME_OFFSET_FSR]
683	call SYM(_Thread_Do_dispatch)
684	mov %g6, %o0
685
686	/*
687	* Restore the floating point context from stack frame and release the
688	* stack frame.
689	*/
690	ldd [%sp + SPARC_FP_FRAME_OFFSET_FO_F1], %f0
691	ldd [%sp + SPARC_FP_FRAME_OFFSET_F2_F3], %f2
692	ldd [%sp + SPARC_FP_FRAME_OFFSET_F4_F5], %f4
693	ldd [%sp + SPARC_FP_FRAME_OFFSET_F6_F7], %f6
694	ldd [%sp + SPARC_FP_FRAME_OFFSET_F8_F9], %f8
695	ldd [%sp + SPARC_FP_FRAME_OFFSET_F1O_F11], %f10
696	ldd [%sp + SPARC_FP_FRAME_OFFSET_F12_F13], %f12
697	ldd [%sp + SPARC_FP_FRAME_OFFSET_F14_F15], %f14
698	ldd [%sp + SPARC_FP_FRAME_OFFSET_F16_F17], %f16
699	ldd [%sp + SPARC_FP_FRAME_OFFSET_F18_F19], %f18
700	ldd [%sp + SPARC_FP_FRAME_OFFSET_F2O_F21], %f20
701	ldd [%sp + SPARC_FP_FRAME_OFFSET_F22_F23], %f22
702	ldd [%sp + SPARC_FP_FRAME_OFFSET_F24_F25], %f24
703	ldd [%sp + SPARC_FP_FRAME_OFFSET_F26_F27], %f26
704	ldd [%sp + SPARC_FP_FRAME_OFFSET_F28_F29], %f28
705	ldd [%sp + SPARC_FP_FRAME_OFFSET_F3O_F31], %f30
706	ld [%sp + SPARC_FP_FRAME_OFFSET_FSR], %fsr
707	ba .Lthread_dispatch_done
708	add %sp, SPARC_FP_FRAME_SIZE, %sp
709
710	.Lnon_fp_thread_dispatch:
711	#endif
712
713	call SYM(_Thread_Do_dispatch)
714	mov %g6, %o0
715
716	#if SPARC_HAS_FPU == 1
717	.Lthread_dispatch_done:
718	#endif
719
720	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
721
722	/*
723	* While we had ISR dispatching disabled in this thread,
724	* did we miss anything? If so, then we need to do another
725	* _Thread_Do_dispatch() before leaving this ISR dispatch context.
726	*/
727	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
728
729	orcc %l7, %g0, %g0 ! Is a thread dispatch necessary?
730	bne isr_dispatch ! Yes, then invoke the dispatcher again.
731	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
732
733	/*
734	* No, then set the ISR dispatch disable flag to zero and continue with
735	* the simple return.
736	*/
737	st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
738
739	/*
740	* The CWP in place at this point may be different from
741	* that which was in effect at the beginning of the ISR if we
742	* have been context switched between the beginning of this invocation
743	* of _SPARC_Interrupt_trap() and this point. Thus the CWP and WIM
744	* should not be changed back to their values at ISR entry time. Any
745	* changes to the PSR must preserve the CWP.
746	*/
747
748	simple_return:
749	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
750	wr %l5, 0, %y
751
752	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
753	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
754	rd %psr, %l3
755	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
756	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
757	or %l3, %l0, %l0 ! install it later...
758	andn %l0, SPARC_PSR_ET_MASK, %l0
759
760	/*
761	* Restore tasks global and out registers
762	*/
763
764	mov %fp, %g1
765
766	! g1 is restored later
767	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
768	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
769	ld [%fp + ISF_G7_OFFSET], %g7 ! restore g7
770
771	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
772	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
773	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
774	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
775
776	/*
777	* Registers:
778	*
779	* ALL global registers EXCEPT G1 and the input registers have
780	* already been restored and thuse off limits.
781	*
782	* The following is the contents of the local registers:
783	*
784	* l0 = original psr
785	* l1 = return address (i.e. PC)
786	* l2 = nPC
787	* l3 = CWP
788	*/
789
790	/*
791	* if (CWP + 1) is an invalid window then we need to reload it.
792	*
793	* WARNING: Traps should now be disabled
794	*/
795
796	mov %l0, %psr ! ** DISABLE TRAPS **
797	nop
798	nop
799	nop
800	rd %wim, %l4
801	add %l0, 1, %l6 ! l6 = cwp + 1
802	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
803	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
804	! and CWP are conveniently LS 5 bits
805	cmp %l5, 1 ! Is tasks window invalid?
806	bne good_task_window
807
808	/*
809	* The following code is the same as a 1 position left rotate of WIM.
810	*/
811
812	sll %l4, 1, %l5 ! l5 = WIM << 1
813	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
814	! l4 = WIM >> (Number Windows - 1)
815	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
816	! (WIM >> (Number Windows - 1))
817
818	/*
819	* Now restore the window just as if we underflowed to it.
820	*/
821
822	wr %l4, 0, %wim ! WIM = new WIM
823	nop ! must delay after writing WIM
824	nop
825	nop
826	restore ! now into the tasks window
827
828	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
829	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
830	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
831	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
832	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
833	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
834	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
835	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
836	! reload of sp clobbers ISF
837	save ! Back to ISR dispatch window
838
839	good_task_window:
840	TN0018_WAIT_IFLUSH %l3,%l4 ! GRLIB-TN-0018 work around macro
841
842	mov %l0, %psr ! ** DISABLE TRAPS **
843	nop; nop; nop
844	! and restore condition codes.
845	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
846	TN0018_FIX %l3,%l4 ! GRLIB-TN-0018 work around macro
847	jmp %l1 ! transfer control and
848	rett %l2 ! go back to tasks window
849
850	/* end of file */

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