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cpu_asm.S @ 9165349d

Last change on this file since 9165349d was 2a720f4, checked in by Maksim E. Kozlov <maksim.e.kozlov@…>, on 06/06/19 at 12:57:54

sparc: Fix mistakenly cleared PSR[EF] bit.

The superfluously modified %l0 had no effect if the branch is not taken.
This change clarifies the code.

Property mode set to 100644

File size: 32.6 KB

Line
1	/* cpu_asm.s
2	*
3	* This file contains the basic algorithms for all assembly code used
4	* in an specific CPU port of RTEMS. These algorithms must be implemented
5	* in assembly language.
6	*
7	* COPYRIGHT (c) 1989-2011.
8	* On-Line Applications Research Corporation (OAR).
9	*
10	* Copyright (c) 2014, 2017 embedded brains GmbH
11	*
12	* The license and distribution terms for this file may be
13	* found in the file LICENSE in this distribution or at
14	* http://www.rtems.org/license/LICENSE.
15	*
16	* Ported to ERC32 implementation of the SPARC by On-Line Applications
17	* Research Corporation (OAR) under contract to the European Space
18	* Agency (ESA).
19	*
20	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
21	* European Space Agency.
22	*/
23
24	#include <rtems/asm.h>
25	#include <rtems/score/percpu.h>
26
27	#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
28	#define FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
29	#define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
30	#define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
31	#define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
32	#define FP_FRAME_OFFSET_F8_F9 (FP_FRAME_OFFSET_F6_F7 + 8)
33	#define FP_FRAME_OFFSET_F1O_F11 (FP_FRAME_OFFSET_F8_F9 + 8)
34	#define FP_FRAME_OFFSET_F12_F13 (FP_FRAME_OFFSET_F1O_F11 + 8)
35	#define FP_FRAME_OFFSET_F14_F15 (FP_FRAME_OFFSET_F12_F13 + 8)
36	#define FP_FRAME_OFFSET_F16_F17 (FP_FRAME_OFFSET_F14_F15 + 8)
37	#define FP_FRAME_OFFSET_F18_F19 (FP_FRAME_OFFSET_F16_F17 + 8)
38	#define FP_FRAME_OFFSET_F2O_F21 (FP_FRAME_OFFSET_F18_F19 + 8)
39	#define FP_FRAME_OFFSET_F22_F23 (FP_FRAME_OFFSET_F2O_F21 + 8)
40	#define FP_FRAME_OFFSET_F24_F25 (FP_FRAME_OFFSET_F22_F23 + 8)
41	#define FP_FRAME_OFFSET_F26_F27 (FP_FRAME_OFFSET_F24_F25 + 8)
42	#define FP_FRAME_OFFSET_F28_F29 (FP_FRAME_OFFSET_F26_F27 + 8)
43	#define FP_FRAME_OFFSET_F3O_F31 (FP_FRAME_OFFSET_F28_F29 + 8)
44	#define FP_FRAME_OFFSET_FSR (FP_FRAME_OFFSET_F3O_F31 + 8)
45	#define FP_FRAME_SIZE (FP_FRAME_OFFSET_FSR + 8)
46	#endif
47
48	/*
49	* void _CPU_Context_switch(
50	* Context_Control *run,
51	* Context_Control *heir
52	* )
53	*
54	* This routine performs a normal non-FP context switch.
55	*/
56
57	.align 4
58	PUBLIC(_CPU_Context_switch)
59	SYM(_CPU_Context_switch):
60	st %g5, [%o0 + G5_OFFSET] ! save the global registers
61
62	/*
63	* No need to save the thread pointer %g7 since it is a thread
64	* invariant. It is initialized once in _CPU_Context_Initialize().
65	*/
66
67	std %l0, [%o0 + L0_OFFSET] ! save the local registers
68	SPARC_LEON3FT_B2BST_NOP
69	std %l2, [%o0 + L2_OFFSET]
70	SPARC_LEON3FT_B2BST_NOP
71	std %l4, [%o0 + L4_OFFSET]
72	SPARC_LEON3FT_B2BST_NOP
73	std %l6, [%o0 + L6_OFFSET]
74	SPARC_LEON3FT_B2BST_NOP
75
76	std %i0, [%o0 + I0_OFFSET] ! save the input registers
77	SPARC_LEON3FT_B2BST_NOP
78	std %i2, [%o0 + I2_OFFSET]
79	SPARC_LEON3FT_B2BST_NOP
80	std %i4, [%o0 + I4_OFFSET]
81	SPARC_LEON3FT_B2BST_NOP
82	std %i6, [%o0 + I6_FP_OFFSET]
83	SPARC_LEON3FT_B2BST_NOP
84
85	std %o6, [%o0 + O6_SP_OFFSET] ! save the output registers
86
87	! load the ISR stack nesting prevention flag
88	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
89	! save it a bit later so we do not waste a couple of cycles
90
91	rd %psr, %o2
92	st %o2, [%o0 + PSR_OFFSET] ! save status register
93
94	! Now actually save ISR stack nesting prevention flag
95	st %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
96
97	/*
98	* This is entered from _CPU_Context_restore with:
99	* o1 = context to restore
100	* o2 = psr
101	*/
102
103	PUBLIC(_CPU_Context_restore_heir)
104	SYM(_CPU_Context_restore_heir):
105	/*
106	* Flush all windows with valid contents except the current one.
107	* In examining the set register windows, one may logically divide
108	* the windows into sets (some of which may be empty) based on their
109	* current status:
110	*
111	* + current (i.e. in use),
112	* + used (i.e. a restore would not trap)
113	* + invalid (i.e. 1 in corresponding bit in WIM)
114	* + unused
115	*
116	* Either the used or unused set of windows may be empty.
117	*
118	* NOTE: We assume only one bit is set in the WIM at a time.
119	*
120	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
121	* into sets as follows:
122	*
123	* + 0 - invalid
124	* + 1-4 - unused
125	* + 5 - current
126	* + 6-7 - used
127	*
128	* In this case, we only would save the used windows -- 6 and 7.
129	*
130	* Traps are disabled for the same logical period as in a
131	* flush all windows trap handler.
132	*
133	* Register Usage while saving the windows:
134	* g1 = current PSR
135	* g2 = current wim
136	* g3 = CWP
137	* g4 = wim scratch
138	* g5 = scratch
139	*/
140
141	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
142	andn %o2, SPARC_PSR_ET_MASK, %g1 ! g1 = psr with traps disabled
143	mov %g1, %psr ! ** DISABLE TRAPS **
144	mov %wim, %g2 ! g2 = wim
145	mov 1, %g4
146	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
147
148	save_frame_loop:
149	sll %g4, 1, %g5 ! rotate the "wim" left 1
150	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
151	or %g4, %g5, %g4 ! g4 = wim if we do one restore
152
153	/*
154	* If a restore would not underflow, then continue.
155	*/
156
157	andcc %g4, %g2, %g0 ! Any windows to flush?
158	bnz done_flushing ! No, then continue
159	nop
160
161	restore ! back one window
162
163	/*
164	* Now save the window just as if we overflowed to it.
165	*/
166
167	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
168	SPARC_LEON3FT_B2BST_NOP
169	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
170	SPARC_LEON3FT_B2BST_NOP
171	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
172	SPARC_LEON3FT_B2BST_NOP
173	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
174	SPARC_LEON3FT_B2BST_NOP
175
176	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
177	SPARC_LEON3FT_B2BST_NOP
178	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
179	SPARC_LEON3FT_B2BST_NOP
180	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
181	SPARC_LEON3FT_B2BST_NOP
182	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
183	SPARC_LEON3FT_B2BST_NOP
184
185	ba save_frame_loop
186	nop
187
188	done_flushing:
189
190	! Wait three instructions after the write to PSR before using
191	! non-global registers or instructions affecting the CWP
192	mov %g1, %psr ! restore cwp
193	add %g3, 1, %g2 ! calculate desired WIM
194	and %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
195	mov 1, %g4
196	sll %g4, %g2, %g4 ! g4 = new WIM
197	mov %g4, %wim
198
199	#if defined(RTEMS_SMP)
200	/*
201	* The executing thread no longer executes on this processor. Switch
202	* the stack to the temporary interrupt stack of this processor. Mark
203	* the context of the executing thread as not executing.
204	*/
205	add %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp
206	st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
207
208	! Try to update the is executing indicator of the heir context
209	mov 1, %g1
210
211	.Ltry_update_is_executing:
212
213	swap [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
214	cmp %g1, 0
215	bne .Lcheck_is_executing
216
217	! The next load is in a delay slot, which is all right
218	#endif
219
220	#if defined(SPARC_USE_LAZY_FP_SWITCH)
221	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %g2
222	#endif
223	ld [%o1 + PSR_OFFSET], %g1 ! g1 = heir psr with traps enabled
224	#if defined(SPARC_USE_LAZY_FP_SWITCH)
225	sethi %hi(SPARC_PSR_EF_MASK), %g5
226	cmp %g2, %g0
227	bne,a .Lclear_psr_ef_done
228	andn %g1, %g5, %g1 ! g1 = heir psr w/o PSR[EF]
229	.Lclear_psr_ef_done:
230	#endif
231	andn %g1, SPARC_PSR_CWP_MASK, %g1 ! g1 = heir psr w/o cwp
232	or %g1, %g3, %g1 ! g1 = heir psr with cwp
233	mov %g1, %psr ! restore status register and
234	! ** ENABLE TRAPS **
235
236	ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
237	ld [%o1 + G7_OFFSET], %g7
238
239	! Load thread specific ISR dispatch prevention flag
240	ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
241	! Store it to memory later to use the cycles
242
243	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
244	ldd [%o1 + L2_OFFSET], %l2
245	ldd [%o1 + L4_OFFSET], %l4
246	ldd [%o1 + L6_OFFSET], %l6
247
248	! Now restore thread specific ISR dispatch prevention flag
249	st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
250
251	ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers
252	ldd [%o1 + I2_OFFSET], %i2
253	ldd [%o1 + I4_OFFSET], %i4
254	ldd [%o1 + I6_FP_OFFSET], %i6
255
256	ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers
257
258	jmp %o7 + 8 ! return
259	nop ! delay slot
260
261	#if defined(RTEMS_SMP)
262	.Lcheck_is_executing:
263
264	! Check the is executing indicator of the heir context
265	ld [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
266	cmp %g1, 0
267	beq .Ltry_update_is_executing
268	mov 1, %g1
269
270	! We may have a new heir
271
272	! Read the executing and heir
273	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %g2
274	ld [%g6 + PER_CPU_OFFSET_HEIR], %g4
275
276	! Update the executing only if necessary to avoid cache line
277	! monopolization.
278	cmp %g2, %g4
279	beq .Ltry_update_is_executing
280	mov 1, %g1
281
282	! Calculate the heir context pointer
283	sub %o1, %g2, %g2
284	add %g2, %g4, %o1
285
286	! Update the executing
287	st %g4, [%g6 + PER_CPU_OFFSET_EXECUTING]
288
289	ba .Ltry_update_is_executing
290	mov 1, %g1
291	#endif
292
293	/*
294	* void _CPU_Context_restore(
295	* Context_Control *new_context
296	* )
297	*
298	* This routine is generally used only to perform restart self.
299	*
300	* NOTE: It is unnecessary to reload some registers.
301	*/
302	.align 4
303	PUBLIC(_CPU_Context_restore)
304	SYM(_CPU_Context_restore):
305	save %sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
306	rd %psr, %o2
307	#if defined(RTEMS_SMP)
308	! On SPARC the restore path needs also a valid executing context on SMP
309	! to update the is executing indicator.
310	mov %i0, %o0
311	#endif
312	ba SYM(_CPU_Context_restore_heir)
313	mov %i0, %o1 ! in the delay slot
314
315	/*
316	* void _ISR_Handler()
317	*
318	* This routine provides the RTEMS interrupt management.
319	*
320	* We enter this handler from the 4 instructions in the trap table with
321	* the following registers assumed to be set as shown:
322	*
323	* l0 = PSR
324	* l1 = PC
325	* l2 = nPC
326	* l3 = trap type
327	*
328	* NOTE: By an executive defined convention, trap type is between 0 and 255 if
329	* it is an asynchonous trap and 256 and 511 if it is synchronous.
330	*/
331
332	.align 4
333	PUBLIC(_ISR_Handler)
334	SYM(_ISR_Handler):
335	/*
336	* Fix the return address for synchronous traps.
337	*/
338
339	andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
340	! Is this a synchronous trap?
341	be,a win_ovflow ! No, then skip the adjustment
342	nop ! DELAY
343	mov %l1, %l6 ! save trapped pc for debug info
344	mov %l2, %l1 ! do not return to the instruction
345	add %l2, 4, %l2 ! indicated
346
347	win_ovflow:
348	/*
349	* Save the globals this block uses.
350	*
351	* These registers are not restored from the locals. Their contents
352	* are saved directly from the locals into the ISF below.
353	*/
354
355	mov %g4, %l4 ! save the globals this block uses
356	mov %g5, %l5
357
358	/*
359	* When at a "window overflow" trap, (wim == (1 << cwp)).
360	* If we get here like that, then process a window overflow.
361	*/
362
363	rd %wim, %g4
364	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
365	! are LS 5 bits ; how convenient :)
366	cmp %g5, 1 ! Is this an invalid window?
367	bne dont_do_the_window ! No, then skip all this stuff
368	! we are using the delay slot
369
370	/*
371	* The following is same as a 1 position right rotate of WIM
372	*/
373
374	srl %g4, 1, %g5 ! g5 = WIM >> 1
375	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
376	! g4 = WIM << (Number Windows - 1)
377	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
378	! (WIM << (Number Windows - 1))
379
380	/*
381	* At this point:
382	*
383	* g4 = the new WIM
384	* g5 is free
385	*/
386
387	/*
388	* Since we are tinkering with the register windows, we need to
389	* make sure that all the required information is in global registers.
390	*/
391
392	save ! Save into the window
393	wr %g4, 0, %wim ! WIM = new WIM
394	nop ! delay slots
395	nop
396	nop
397
398	/*
399	* Now save the window just as if we overflowed to it.
400	*/
401
402	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
403	SPARC_LEON3FT_B2BST_NOP
404	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
405	SPARC_LEON3FT_B2BST_NOP
406	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
407	SPARC_LEON3FT_B2BST_NOP
408	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
409	SPARC_LEON3FT_B2BST_NOP
410
411	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
412	SPARC_LEON3FT_B2BST_NOP
413	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
414	SPARC_LEON3FT_B2BST_NOP
415	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
416	SPARC_LEON3FT_B2BST_NOP
417	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
418
419	restore
420	nop
421
422	dont_do_the_window:
423	/*
424	* Global registers %g4 and %g5 are saved directly from %l4 and
425	* %l5 directly into the ISF below.
426	*/
427
428	/*
429	* Save the state of the interrupted task -- especially the global
430	* registers -- in the Interrupt Stack Frame. Note that the ISF
431	* includes a regular minimum stack frame which will be used if
432	* needed by register window overflow and underflow handlers.
433	*
434	* REGISTERS SAME AS AT _ISR_Handler
435	*/
436
437	sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
438	! make space for ISF
439
440	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
441	SPARC_LEON3FT_B2BST_NOP
442	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
443	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
444	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
445	SPARC_LEON3FT_B2BST_NOP
446	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
447	SPARC_LEON3FT_B2BST_NOP
448	st %g7, [%sp + ISF_G7_OFFSET] ! save g7
449
450	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
451	SPARC_LEON3FT_B2BST_NOP
452	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
453	SPARC_LEON3FT_B2BST_NOP
454	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
455	SPARC_LEON3FT_B2BST_NOP
456	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
457
458	rd %y, %g1
459	st %g1, [%sp + ISF_Y_OFFSET] ! save y
460	st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
461
462	mov %sp, %o1 ! 2nd arg to ISR Handler
463
464	/*
465	* Increment ISR nest level and Thread dispatch disable level.
466	*
467	* Register usage for this section:
468	*
469	* l6 = _Thread_Dispatch_disable_level value
470	* l7 = _ISR_Nest_level value
471	*
472	* NOTE: It is assumed that l6 - l7 will be preserved until the ISR
473	* nest and thread dispatch disable levels are unnested.
474	*/
475
476	ld [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
477	ld [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
478
479	add %l7, 1, %l7
480	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
481	SPARC_LEON3FT_B2BST_NOP
482
483	add %l6, 1, %l6
484	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
485
486	#if SPARC_HAS_FPU == 1
487	/*
488	* We cannot use an intermediate value for operations with the PSR[EF]
489	* bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
490	*/
491	sethi %hi(SPARC_PSR_EF_MASK), %l5
492	#endif
493
494	/*
495	* If ISR nest level was zero (now 1), then switch stack.
496	*/
497
498	mov %sp, %fp
499	subcc %l7, 1, %l7 ! outermost interrupt handler?
500	bnz dont_switch_stacks ! No, then do not switch stacks
501
502	#if defined(RTEMS_PROFILING)
503	sethi %hi(_SPARC_Counter), %o5
504	ld [%o5 + %lo(_SPARC_Counter)], %l4
505	call %l4
506	nop
507	mov %o0, %o5
508	#else
509	nop
510	#endif
511
512	ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
513
514	#if SPARC_HAS_FPU == 1
515	/*
516	* Test if the interrupted thread uses the floating point unit
517	* (PSR[EF] == 1). In case it uses the floating point unit, then store
518	* the floating point status register. This has the side-effect that
519	* all pending floating point operations complete before the store
520	* completes. The PSR[EF] bit is restored after the call to the
521	* interrupt handler. Thus post-switch actions (e.g. signal handlers)
522	* and context switch extensions may still corrupt the floating point
523	* context.
524	*/
525	andcc %l0, %l5, %g0
526	bne,a dont_switch_stacks
527	st %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
528	#endif
529
530	dont_switch_stacks:
531	/*
532	* Make sure we have a place on the stack for the window overflow
533	* trap handler to write into. At this point it is safe to
534	* enable traps again.
535	*/
536
537	sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
538
539	/*
540	* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
541	* set the PIL in the %psr to mask off interrupts with lower priority.
542	* The original %psr in %l0 is not modified since it will be restored
543	* when the interrupt handler returns.
544	*/
545
546	mov %l0, %g5
547	and %l3, 0x0ff, %g4
548	subcc %g4, 0x11, %g0
549	bl dont_fix_pil
550	subcc %g4, 0x1f, %g0
551	bg dont_fix_pil
552	sll %g4, 8, %g4
553	and %g4, SPARC_PSR_PIL_MASK, %g4
554	andn %l0, SPARC_PSR_PIL_MASK, %g5
555	ba pil_fixed
556	or %g4, %g5, %g5
557	dont_fix_pil:
558	or %g5, SPARC_PSR_PIL_MASK, %g5
559	pil_fixed:
560
561	#if SPARC_HAS_FPU == 1
562	/*
563	* Clear the PSR[EF] bit of the interrupted context to ensure that
564	* interrupt service routines cannot corrupt the floating point context.
565	*/
566	andn %g5, %l5, %g5
567	#endif
568
569	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
570
571	/*
572	* Vector to user's handler.
573	*
574	* NOTE: TBR may no longer have vector number in it since
575	* we just enabled traps. It is definitely in l3.
576	*/
577
578	sethi %hi(SYM(_ISR_Vector_table)), %g4
579	or %g4, %lo(SYM(_ISR_Vector_table)), %g4
580	and %l3, 0xFF, %g5 ! remove synchronous trap indicator
581	sll %g5, 2, %g5 ! g5 = offset into table
582	ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
583
584
585	! o1 = 2nd arg = address of the ISF
586	! WAS LOADED WHEN ISF WAS SAVED!!!
587	mov %l3, %o0 ! o0 = 1st arg = vector number
588	call %g4
589	#if defined(RTEMS_PROFILING)
590	mov %o5, %l3 ! save interrupt entry instant
591	#else
592	nop ! delay slot
593	#endif
594
595	#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
596	mov %l0, %g1 ! PSR[EF] value of interrupted context
597	ta SPARC_SWTRAP_IRQDIS_FP ! ** DISABLE INTERRUPTS **
598	#else
599	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
600	#endif
601
602	#if defined(RTEMS_PROFILING)
603	cmp %l7, 0
604	bne profiling_not_outer_most_exit
605	nop
606	call %l4 ! Call _SPARC_Counter.counter_read
607	mov %g1, %l4 ! Save previous interrupt status
608	mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
609	mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
610	call SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
611	mov %g6, %o0 ! o0 = 1st arg = per-CPU control
612	profiling_not_outer_most_exit:
613	#endif
614
615	/*
616	* Decrement ISR nest level and Thread dispatch disable level.
617	*
618	* Register usage for this section:
619	*
620	* o2 = g6->dispatch_necessary value
621	* o3 = g6->isr_dispatch_disable value
622	* l6 = g6->thread_dispatch_disable_level value
623	* l7 = g6->isr_nest_level value
624	*/
625
626	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
627	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
628	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
629	SPARC_LEON3FT_B2BST_NOP
630	sub %l6, 1, %l6
631	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
632
633	/*
634	* Thread dispatching is necessary and allowed if and only if
635	* g6->dispatch_necessary == 1 and
636	* g6->isr_dispatch_disable == 0 and
637	* g6->thread_dispatch_disable_level == 0.
638	*
639	* Otherwise, continue with the simple return.
640	*/
641	xor %o2, 1, %o2
642	or %o2, %l6, %o2
643	orcc %o2, %o3, %o2
644	bnz simple_return
645
646	/*
647	* Switch back on the interrupted tasks stack and add enough room to
648	* invoke the dispatcher. Doing this in the delay slot causes no harm,
649	* since the stack pointer (%sp) is not used in the simple return path.
650	*/
651	sub %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
652
653	isr_dispatch:
654
655	/* Set ISR dispatch disable and thread dispatch disable level to one */
656	mov 1, %l6
657	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
658	st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
659
660	/* Call _Thread_Do_dispatch(), this function will enable interrupts */
661
662	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
663
664	#if defined(SPARC_USE_LAZY_FP_SWITCH)
665	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
666	andcc %l0, %l5, %g0
667	be .Lnon_fp_thread_dispatch
668	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %l6
669
670	/* Set new floating point unit owner to executing thread */
671	st %l6, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
672
673	call SYM(_Thread_Do_dispatch)
674	mov %g6, %o0
675
676	/*
677	* If we are still the floating point unit owner, then reset the
678	* floating point unit owner to NULL, otherwise clear PSR[EF] in the
679	* interrupt frame and let the FP disabled system call do the floating
680	* point context save/restore.
681	*/
682	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %l7
683	cmp %l6, %l7
684	bne,a .Ldisable_fp
685	andn %l0, %l5, %l0
686	ba .Lthread_dispatch_done
687	st %g0, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
688	.Ldisable_fp:
689	ba .Lthread_dispatch_done
690	st %l0, [%fp + ISF_PSR_OFFSET]
691	.Lnon_fp_thread_dispatch:
692	#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
693	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
694	andcc %l0, %l5, %g0
695	be .Lnon_fp_thread_dispatch
696	nop
697
698	/*
699	* Yes, this is a floating point thread, then save the floating point
700	* context to a new stack frame. Then do the thread dispatch.
701	* Post-switch actions (e.g. signal handlers) and context switch
702	* extensions may safely use the floating point unit.
703	*/
704	sub %sp, FP_FRAME_SIZE, %sp
705	std %f0, [%sp + FP_FRAME_OFFSET_FO_F1]
706	SPARC_LEON3FT_B2BST_NOP
707	std %f2, [%sp + FP_FRAME_OFFSET_F2_F3]
708	SPARC_LEON3FT_B2BST_NOP
709	std %f4, [%sp + FP_FRAME_OFFSET_F4_F5]
710	SPARC_LEON3FT_B2BST_NOP
711	std %f6, [%sp + FP_FRAME_OFFSET_F6_F7]
712	SPARC_LEON3FT_B2BST_NOP
713	std %f8, [%sp + FP_FRAME_OFFSET_F8_F9]
714	SPARC_LEON3FT_B2BST_NOP
715	std %f10, [%sp + FP_FRAME_OFFSET_F1O_F11]
716	SPARC_LEON3FT_B2BST_NOP
717	std %f12, [%sp + FP_FRAME_OFFSET_F12_F13]
718	SPARC_LEON3FT_B2BST_NOP
719	std %f14, [%sp + FP_FRAME_OFFSET_F14_F15]
720	SPARC_LEON3FT_B2BST_NOP
721	std %f16, [%sp + FP_FRAME_OFFSET_F16_F17]
722	SPARC_LEON3FT_B2BST_NOP
723	std %f18, [%sp + FP_FRAME_OFFSET_F18_F19]
724	SPARC_LEON3FT_B2BST_NOP
725	std %f20, [%sp + FP_FRAME_OFFSET_F2O_F21]
726	SPARC_LEON3FT_B2BST_NOP
727	std %f22, [%sp + FP_FRAME_OFFSET_F22_F23]
728	SPARC_LEON3FT_B2BST_NOP
729	std %f24, [%sp + FP_FRAME_OFFSET_F24_F25]
730	SPARC_LEON3FT_B2BST_NOP
731	std %f26, [%sp + FP_FRAME_OFFSET_F26_F27]
732	SPARC_LEON3FT_B2BST_NOP
733	std %f28, [%sp + FP_FRAME_OFFSET_F28_F29]
734	SPARC_LEON3FT_B2BST_NOP
735	std %f30, [%sp + FP_FRAME_OFFSET_F3O_F31]
736	SPARC_LEON3FT_B2BST_NOP
737	st %fsr, [%sp + FP_FRAME_OFFSET_FSR]
738	call SYM(_Thread_Do_dispatch)
739	mov %g6, %o0
740
741	/*
742	* Restore the floating point context from stack frame and release the
743	* stack frame.
744	*/
745	ldd [%sp + FP_FRAME_OFFSET_FO_F1], %f0
746	ldd [%sp + FP_FRAME_OFFSET_F2_F3], %f2
747	ldd [%sp + FP_FRAME_OFFSET_F4_F5], %f4
748	ldd [%sp + FP_FRAME_OFFSET_F6_F7], %f6
749	ldd [%sp + FP_FRAME_OFFSET_F8_F9], %f8
750	ldd [%sp + FP_FRAME_OFFSET_F1O_F11], %f10
751	ldd [%sp + FP_FRAME_OFFSET_F12_F13], %f12
752	ldd [%sp + FP_FRAME_OFFSET_F14_F15], %f14
753	ldd [%sp + FP_FRAME_OFFSET_F16_F17], %f16
754	ldd [%sp + FP_FRAME_OFFSET_F18_F19], %f18
755	ldd [%sp + FP_FRAME_OFFSET_F2O_F21], %f20
756	ldd [%sp + FP_FRAME_OFFSET_F22_F23], %f22
757	ldd [%sp + FP_FRAME_OFFSET_F24_F25], %f24
758	ldd [%sp + FP_FRAME_OFFSET_F26_F27], %f26
759	ldd [%sp + FP_FRAME_OFFSET_F28_F29], %f28
760	ldd [%sp + FP_FRAME_OFFSET_F3O_F31], %f30
761	ld [%sp + FP_FRAME_OFFSET_FSR], %fsr
762	ba .Lthread_dispatch_done
763	add %sp, FP_FRAME_SIZE, %sp
764
765	.Lnon_fp_thread_dispatch:
766	#endif
767
768	call SYM(_Thread_Do_dispatch)
769	mov %g6, %o0
770
771	#if SPARC_HAS_FPU == 1
772	.Lthread_dispatch_done:
773	#endif
774
775	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
776
777	/*
778	* While we had ISR dispatching disabled in this thread,
779	* did we miss anything? If so, then we need to do another
780	* _Thread_Do_dispatch() before leaving this ISR dispatch context.
781	*/
782	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
783
784	orcc %l7, %g0, %g0 ! Is a thread dispatch necessary?
785	bne isr_dispatch ! Yes, then invoke the dispatcher again.
786	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
787
788	/*
789	* No, then set the ISR dispatch disable flag to zero and continue with
790	* the simple return.
791	*/
792	st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
793
794	/*
795	* The CWP in place at this point may be different from
796	* that which was in effect at the beginning of the ISR if we
797	* have been context switched between the beginning of this invocation
798	* of _ISR_Handler and this point. Thus the CWP and WIM should
799	* not be changed back to their values at ISR entry time. Any
800	* changes to the PSR must preserve the CWP.
801	*/
802
803	simple_return:
804	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
805	wr %l5, 0, %y
806
807	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
808	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
809	rd %psr, %l3
810	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
811	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
812	or %l3, %l0, %l0 ! install it later...
813	andn %l0, SPARC_PSR_ET_MASK, %l0
814
815	/*
816	* Restore tasks global and out registers
817	*/
818
819	mov %fp, %g1
820
821	! g1 is restored later
822	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
823	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
824	ld [%fp + ISF_G7_OFFSET], %g7 ! restore g7
825
826	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
827	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
828	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
829	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
830
831	/*
832	* Registers:
833	*
834	* ALL global registers EXCEPT G1 and the input registers have
835	* already been restored and thuse off limits.
836	*
837	* The following is the contents of the local registers:
838	*
839	* l0 = original psr
840	* l1 = return address (i.e. PC)
841	* l2 = nPC
842	* l3 = CWP
843	*/
844
845	/*
846	* if (CWP + 1) is an invalid window then we need to reload it.
847	*
848	* WARNING: Traps should now be disabled
849	*/
850
851	mov %l0, %psr ! ** DISABLE TRAPS **
852	nop
853	nop
854	nop
855	rd %wim, %l4
856	add %l0, 1, %l6 ! l6 = cwp + 1
857	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
858	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
859	! and CWP are conveniently LS 5 bits
860	cmp %l5, 1 ! Is tasks window invalid?
861	bne good_task_window
862
863	/*
864	* The following code is the same as a 1 position left rotate of WIM.
865	*/
866
867	sll %l4, 1, %l5 ! l5 = WIM << 1
868	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
869	! l4 = WIM >> (Number Windows - 1)
870	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
871	! (WIM >> (Number Windows - 1))
872
873	/*
874	* Now restore the window just as if we underflowed to it.
875	*/
876
877	wr %l4, 0, %wim ! WIM = new WIM
878	nop ! must delay after writing WIM
879	nop
880	nop
881	restore ! now into the tasks window
882
883	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
884	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
885	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
886	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
887	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
888	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
889	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
890	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
891	! reload of sp clobbers ISF
892	save ! Back to ISR dispatch window
893
894	good_task_window:
895
896	mov %l0, %psr ! ** DISABLE TRAPS **
897	nop; nop; nop
898	! and restore condition codes.
899	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
900	jmp %l1 ! transfer control and
901	rett %l2 ! go back to tasks window
902
903	/* end of file */

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