source: rtems/cpukit/score/cpu/sparc/cpu_asm.S @ 1549beb

5
Last change on this file since 1549beb was a51b352, checked in by Sebastian Huber <sebastian.huber@…>, on 05/30/15 at 15:48:27

sparc: Add SPARC_USE_SAFE_FP_SUPPORT

The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically the deferred floating point switch is
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context. The floating point unit is disabled for interrupt handlers.
Thus in case an interrupt handler uses the floating point unit then this
will result in a trap.

On SMP configurations the deferred floating point switch is not
supported in principle. So use here a safe floating point support. Safe
means that the volatile floating point context is saved and restored
around a thread dispatch issued during interrupt processing. Thus
post-switch actions and context switch extensions may safely use the
floating point unit.

Update #2270.
  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2011.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 *
14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
15 *  Research Corporation (OAR) under contract to the European Space
16 *  Agency (ESA).
17 *
18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19 *  European Space Agency.
20 */
21
22#ifdef HAVE_CONFIG_H
23#include "config.h"
24#endif
25
26#include <rtems/asm.h>
27#include <rtems/system.h>
28
29#if (SPARC_HAS_FPU == 1) && !defined(SPARC_USE_SAFE_FP_SUPPORT)
30
31/*
32 *  void _CPU_Context_save_fp(
33 *    void **fp_context_ptr
34 *  )
35 *
36 *  This routine is responsible for saving the FP context
37 *  at *fp_context_ptr.  If the point to load the FP context
38 *  from is changed then the pointer is modified by this routine.
39 *
40 *  NOTE: See the README in this directory for information on the
41 *        management of the "EF" bit in the PSR.
42 */
43
44        .align 4
45        PUBLIC(_CPU_Context_save_fp)
46SYM(_CPU_Context_save_fp):
47        ld      [%o0], %o1
48        std     %f0, [%o1 + FO_F1_OFFSET]
49        std     %f2, [%o1 + F2_F3_OFFSET]
50        std     %f4, [%o1 + F4_F5_OFFSET]
51        std     %f6, [%o1 + F6_F7_OFFSET]
52        std     %f8, [%o1 + F8_F9_OFFSET]
53        std     %f10, [%o1 + F1O_F11_OFFSET]
54        std     %f12, [%o1 + F12_F13_OFFSET]
55        std     %f14, [%o1 + F14_F15_OFFSET]
56        std     %f16, [%o1 + F16_F17_OFFSET]
57        std     %f18, [%o1 + F18_F19_OFFSET]
58        std     %f20, [%o1 + F2O_F21_OFFSET]
59        std     %f22, [%o1 + F22_F23_OFFSET]
60        std     %f24, [%o1 + F24_F25_OFFSET]
61        std     %f26, [%o1 + F26_F27_OFFSET]
62        std     %f28, [%o1 + F28_F29_OFFSET]
63        std     %f30, [%o1 + F3O_F31_OFFSET]
64        jmp     %o7 + 8
65         st     %fsr, [%o1 + FSR_OFFSET]
66
67/*
68 *  void _CPU_Context_restore_fp(
69 *    void **fp_context_ptr
70 *  )
71 *
72 *  This routine is responsible for restoring the FP context
73 *  at *fp_context_ptr.  If the point to load the FP context
74 *  from is changed then the pointer is modified by this routine.
75 *
76 *  NOTE: See the README in this directory for information on the
77 *        management of the "EF" bit in the PSR.
78 */
79
80        .align 4
81        PUBLIC(_CPU_Context_restore_fp)
82SYM(_CPU_Context_restore_fp):
83        ld      [%o0], %o1
84        ldd     [%o1 + FO_F1_OFFSET], %f0
85        ldd     [%o1 + F2_F3_OFFSET], %f2
86        ldd     [%o1 + F4_F5_OFFSET], %f4
87        ldd     [%o1 + F6_F7_OFFSET], %f6
88        ldd     [%o1 + F8_F9_OFFSET], %f8
89        ldd     [%o1 + F1O_F11_OFFSET], %f10
90        ldd     [%o1 + F12_F13_OFFSET], %f12
91        ldd     [%o1 + F14_F15_OFFSET], %f14
92        ldd     [%o1 + F16_F17_OFFSET], %f16
93        ldd     [%o1 + F18_F19_OFFSET], %f18
94        ldd     [%o1 + F2O_F21_OFFSET], %f20
95        ldd     [%o1 + F22_F23_OFFSET], %f22
96        ldd     [%o1 + F24_F25_OFFSET], %f24
97        ldd     [%o1 + F26_F27_OFFSET], %f26
98        ldd     [%o1 + F28_F29_OFFSET], %f28
99        ldd     [%o1 + F3O_F31_OFFSET], %f30
100        jmp     %o7 + 8
101         ld     [%o1 + FSR_OFFSET], %fsr
102
103#endif /* SPARC_HAS_FPU */
104
105/* end of file */
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