source: rtems/cpukit/score/cpu/sparc/cpu_asm.S @ 2f8704b6

5
Last change on this file since 2f8704b6 was 2f8704b6, checked in by Daniel Cederman <cederman@…>, on 07/13/17 at 07:26:50

sparc: Add assembly workaround for LEON3FT B2BST errata

This patch adds NOP instructions to prevent instruction sequences
that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009:
"LEON3FT Stale Cache Entry After Store with Data Tag Parity Error"
for more information.

The sequences are only modified if FIX_LEON3FT_B2BST is defined.

The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc,
and -mfix-ut699 GCC flags that prevents the sensitive sequences from
being generated.

Update #3057.

  • Property mode set to 100644
File size: 4.0 KB
RevLine 
[c62d36f]1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
[80f7732]5 *  in assembly language.
[c62d36f]6 *
[06dcaf0]7 *  COPYRIGHT (c) 1989-2011.
[c4808ca]8 *  On-Line Applications Research Corporation (OAR).
9 *
[98e4ebf5]10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
[c499856]12 *  http://www.rtems.org/license/LICENSE.
[c4808ca]13 *
[669a6dc3]14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
[80f7732]15 *  Research Corporation (OAR) under contract to the European Space
[669a6dc3]16 *  Agency (ESA).
17 *
[80f7732]18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
[669a6dc3]19 *  European Space Agency.
[c62d36f]20 */
21
[febaa8a]22#ifdef HAVE_CONFIG_H
23#include "config.h"
24#endif
25
[b49bcfc]26#include <rtems/asm.h>
[6d42b4c6]27#include <rtems/system.h>
[c62d36f]28
[a51b352]29#if (SPARC_HAS_FPU == 1) && !defined(SPARC_USE_SAFE_FP_SUPPORT)
[9700578]30
[c62d36f]31/*
[9700578]32 *  void _CPU_Context_save_fp(
33 *    void **fp_context_ptr
34 *  )
[c62d36f]35 *
36 *  This routine is responsible for saving the FP context
37 *  at *fp_context_ptr.  If the point to load the FP context
38 *  from is changed then the pointer is modified by this routine.
39 *
[80f7732]40 *  NOTE: See the README in this directory for information on the
[9700578]41 *        management of the "EF" bit in the PSR.
[c62d36f]42 */
43
44        .align 4
45        PUBLIC(_CPU_Context_save_fp)
46SYM(_CPU_Context_save_fp):
[1f6cdba6]47        ld      [%o0], %o1
[8a1dc71b]48        std     %f0, [%o1 + FO_F1_OFFSET]
[2f8704b6]49        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]50        std     %f2, [%o1 + F2_F3_OFFSET]
[2f8704b6]51        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]52        std     %f4, [%o1 + F4_F5_OFFSET]
[2f8704b6]53        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]54        std     %f6, [%o1 + F6_F7_OFFSET]
[2f8704b6]55        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]56        std     %f8, [%o1 + F8_F9_OFFSET]
[2f8704b6]57        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]58        std     %f10, [%o1 + F1O_F11_OFFSET]
[2f8704b6]59        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]60        std     %f12, [%o1 + F12_F13_OFFSET]
[2f8704b6]61        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]62        std     %f14, [%o1 + F14_F15_OFFSET]
[2f8704b6]63        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]64        std     %f16, [%o1 + F16_F17_OFFSET]
[2f8704b6]65        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]66        std     %f18, [%o1 + F18_F19_OFFSET]
[2f8704b6]67        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]68        std     %f20, [%o1 + F2O_F21_OFFSET]
[2f8704b6]69        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]70        std     %f22, [%o1 + F22_F23_OFFSET]
[2f8704b6]71        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]72        std     %f24, [%o1 + F24_F25_OFFSET]
[2f8704b6]73        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]74        std     %f26, [%o1 + F26_F27_OFFSET]
[2f8704b6]75        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]76        std     %f28, [%o1 + F28_F29_OFFSET]
[2f8704b6]77        SPARC_LEON3FT_B2BST_NOP
[8a1dc71b]78        std     %f30, [%o1 + F3O_F31_OFFSET]
[2f8704b6]79        SPARC_LEON3FT_B2BST_NOP
80#if defined(__FIX_LEON3FT_B2BST)
81        st     %fsr, [%o1 + FSR_OFFSET]
82        jmp     %o7 + 8
83         nop
84#else
[8a1dc71b]85        jmp     %o7 + 8
86         st     %fsr, [%o1 + FSR_OFFSET]
[2f8704b6]87#endif
[c62d36f]88
89/*
[9700578]90 *  void _CPU_Context_restore_fp(
91 *    void **fp_context_ptr
92 *  )
[c62d36f]93 *
94 *  This routine is responsible for restoring the FP context
95 *  at *fp_context_ptr.  If the point to load the FP context
96 *  from is changed then the pointer is modified by this routine.
97 *
[80f7732]98 *  NOTE: See the README in this directory for information on the
[9700578]99 *        management of the "EF" bit in the PSR.
[c62d36f]100 */
101
102        .align 4
103        PUBLIC(_CPU_Context_restore_fp)
104SYM(_CPU_Context_restore_fp):
[1f6cdba6]105        ld      [%o0], %o1
[8a1dc71b]106        ldd     [%o1 + FO_F1_OFFSET], %f0
107        ldd     [%o1 + F2_F3_OFFSET], %f2
108        ldd     [%o1 + F4_F5_OFFSET], %f4
109        ldd     [%o1 + F6_F7_OFFSET], %f6
110        ldd     [%o1 + F8_F9_OFFSET], %f8
111        ldd     [%o1 + F1O_F11_OFFSET], %f10
112        ldd     [%o1 + F12_F13_OFFSET], %f12
113        ldd     [%o1 + F14_F15_OFFSET], %f14
114        ldd     [%o1 + F16_F17_OFFSET], %f16
115        ldd     [%o1 + F18_F19_OFFSET], %f18
116        ldd     [%o1 + F2O_F21_OFFSET], %f20
117        ldd     [%o1 + F22_F23_OFFSET], %f22
118        ldd     [%o1 + F24_F25_OFFSET], %f24
119        ldd     [%o1 + F26_F27_OFFSET], %f26
120        ldd     [%o1 + F28_F29_OFFSET], %f28
121        ldd     [%o1 + F3O_F31_OFFSET], %f30
122        jmp     %o7 + 8
123         ld     [%o1 + FSR_OFFSET], %fsr
[c62d36f]124
[9700578]125#endif /* SPARC_HAS_FPU */
126
127/* end of file */
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