[c62d36f] | 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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[80f7732] | 5 | * in assembly language. |
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[c62d36f] | 6 | * |
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[06dcaf0] | 7 | * COPYRIGHT (c) 1989-2011. |
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[c4808ca] | 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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[98e4ebf5] | 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[c4808ca] | 13 | * |
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[669a6dc3] | 14 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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[80f7732] | 15 | * Research Corporation (OAR) under contract to the European Space |
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[669a6dc3] | 16 | * Agency (ESA). |
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| 17 | * |
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[80f7732] | 18 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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[669a6dc3] | 19 | * European Space Agency. |
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[c62d36f] | 20 | */ |
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| 21 | |
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[febaa8a] | 22 | #ifdef HAVE_CONFIG_H |
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| 23 | #include "config.h" |
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| 24 | #endif |
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| 25 | |
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[b49bcfc] | 26 | #include <rtems/asm.h> |
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[6d42b4c6] | 27 | #include <rtems/system.h> |
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[c62d36f] | 28 | |
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[a51b352] | 29 | #if (SPARC_HAS_FPU == 1) && !defined(SPARC_USE_SAFE_FP_SUPPORT) |
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[9700578] | 30 | |
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[c62d36f] | 31 | /* |
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[9700578] | 32 | * void _CPU_Context_save_fp( |
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| 33 | * void **fp_context_ptr |
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| 34 | * ) |
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[c62d36f] | 35 | * |
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| 36 | * This routine is responsible for saving the FP context |
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| 37 | * at *fp_context_ptr. If the point to load the FP context |
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| 38 | * from is changed then the pointer is modified by this routine. |
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| 39 | * |
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[80f7732] | 40 | * NOTE: See the README in this directory for information on the |
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[9700578] | 41 | * management of the "EF" bit in the PSR. |
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[c62d36f] | 42 | */ |
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| 43 | |
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| 44 | .align 4 |
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| 45 | PUBLIC(_CPU_Context_save_fp) |
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| 46 | SYM(_CPU_Context_save_fp): |
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[1f6cdba6] | 47 | ld [%o0], %o1 |
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[8a1dc71b] | 48 | std %f0, [%o1 + FO_F1_OFFSET] |
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[2f8704b6] | 49 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 50 | std %f2, [%o1 + F2_F3_OFFSET] |
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[2f8704b6] | 51 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 52 | std %f4, [%o1 + F4_F5_OFFSET] |
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[2f8704b6] | 53 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 54 | std %f6, [%o1 + F6_F7_OFFSET] |
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[2f8704b6] | 55 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 56 | std %f8, [%o1 + F8_F9_OFFSET] |
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[2f8704b6] | 57 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 58 | std %f10, [%o1 + F1O_F11_OFFSET] |
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[2f8704b6] | 59 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 60 | std %f12, [%o1 + F12_F13_OFFSET] |
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[2f8704b6] | 61 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 62 | std %f14, [%o1 + F14_F15_OFFSET] |
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[2f8704b6] | 63 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 64 | std %f16, [%o1 + F16_F17_OFFSET] |
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[2f8704b6] | 65 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 66 | std %f18, [%o1 + F18_F19_OFFSET] |
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[2f8704b6] | 67 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 68 | std %f20, [%o1 + F2O_F21_OFFSET] |
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[2f8704b6] | 69 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 70 | std %f22, [%o1 + F22_F23_OFFSET] |
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[2f8704b6] | 71 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 72 | std %f24, [%o1 + F24_F25_OFFSET] |
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[2f8704b6] | 73 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 74 | std %f26, [%o1 + F26_F27_OFFSET] |
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[2f8704b6] | 75 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 76 | std %f28, [%o1 + F28_F29_OFFSET] |
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[2f8704b6] | 77 | SPARC_LEON3FT_B2BST_NOP |
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[8a1dc71b] | 78 | std %f30, [%o1 + F3O_F31_OFFSET] |
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[2f8704b6] | 79 | SPARC_LEON3FT_B2BST_NOP |
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| 80 | #if defined(__FIX_LEON3FT_B2BST) |
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| 81 | st %fsr, [%o1 + FSR_OFFSET] |
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| 82 | jmp %o7 + 8 |
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| 83 | nop |
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| 84 | #else |
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[8a1dc71b] | 85 | jmp %o7 + 8 |
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| 86 | st %fsr, [%o1 + FSR_OFFSET] |
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[2f8704b6] | 87 | #endif |
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[c62d36f] | 88 | |
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| 89 | /* |
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[9700578] | 90 | * void _CPU_Context_restore_fp( |
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| 91 | * void **fp_context_ptr |
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| 92 | * ) |
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[c62d36f] | 93 | * |
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| 94 | * This routine is responsible for restoring the FP context |
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| 95 | * at *fp_context_ptr. If the point to load the FP context |
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| 96 | * from is changed then the pointer is modified by this routine. |
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| 97 | * |
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[80f7732] | 98 | * NOTE: See the README in this directory for information on the |
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[9700578] | 99 | * management of the "EF" bit in the PSR. |
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[c62d36f] | 100 | */ |
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| 101 | |
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| 102 | .align 4 |
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| 103 | PUBLIC(_CPU_Context_restore_fp) |
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| 104 | SYM(_CPU_Context_restore_fp): |
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[1f6cdba6] | 105 | ld [%o0], %o1 |
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[8a1dc71b] | 106 | ldd [%o1 + FO_F1_OFFSET], %f0 |
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| 107 | ldd [%o1 + F2_F3_OFFSET], %f2 |
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| 108 | ldd [%o1 + F4_F5_OFFSET], %f4 |
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| 109 | ldd [%o1 + F6_F7_OFFSET], %f6 |
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| 110 | ldd [%o1 + F8_F9_OFFSET], %f8 |
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| 111 | ldd [%o1 + F1O_F11_OFFSET], %f10 |
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| 112 | ldd [%o1 + F12_F13_OFFSET], %f12 |
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| 113 | ldd [%o1 + F14_F15_OFFSET], %f14 |
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| 114 | ldd [%o1 + F16_F17_OFFSET], %f16 |
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| 115 | ldd [%o1 + F18_F19_OFFSET], %f18 |
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| 116 | ldd [%o1 + F2O_F21_OFFSET], %f20 |
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| 117 | ldd [%o1 + F22_F23_OFFSET], %f22 |
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| 118 | ldd [%o1 + F24_F25_OFFSET], %f24 |
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| 119 | ldd [%o1 + F26_F27_OFFSET], %f26 |
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| 120 | ldd [%o1 + F28_F29_OFFSET], %f28 |
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| 121 | ldd [%o1 + F3O_F31_OFFSET], %f30 |
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| 122 | jmp %o7 + 8 |
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| 123 | ld [%o1 + FSR_OFFSET], %fsr |
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[c62d36f] | 124 | |
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[9700578] | 125 | #endif /* SPARC_HAS_FPU */ |
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| 126 | |
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| 127 | /* end of file */ |
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