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cpu_asm.S @ 0cae482a

Last change on this file since 0cae482a was 0cae482a, checked in by Daniel Cederman <cederman@…>, on 12/19/17 at 12:37:08

sparc: Remove sequences that the B2BST scan script warns about

Update #4336.

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[5d69cd3]	1	/* cpu_asm.s
	2	*
	3	* This file contains the basic algorithms for all assembly code used
	4	* in an specific CPU port of RTEMS. These algorithms must be implemented
	5	* in assembly language.
	6	*
	7	* COPYRIGHT (c) 1989-2011.
	8	* On-Line Applications Research Corporation (OAR).
	9	*
[146adb1]	10	* Copyright (c) 2014, 2017 embedded brains GmbH
[fbda4a8]	11	*
[5d69cd3]	12	* The license and distribution terms for this file may be
	13	* found in the file LICENSE in this distribution or at
[c499856]	14	* http://www.rtems.org/license/LICENSE.
[5d69cd3]	15	*
	16	* Ported to ERC32 implementation of the SPARC by On-Line Applications
	17	* Research Corporation (OAR) under contract to the European Space
	18	* Agency (ESA).
	19	*
	20	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
	21	* European Space Agency.
	22	*/
	23
	24	#include <rtems/asm.h>
[f8ad6c6f]	25	#include <rtems/score/percpu.h>
[8b077ca0]	26
[a400d06f]	27	#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
[427dcee]	28	#define FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
[a51b352]	29	#define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
	30	#define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
	31	#define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
	32	#define FP_FRAME_OFFSET_F8_F9 (FP_FRAME_OFFSET_F6_F7 + 8)
	33	#define FP_FRAME_OFFSET_F1O_F11 (FP_FRAME_OFFSET_F8_F9 + 8)
	34	#define FP_FRAME_OFFSET_F12_F13 (FP_FRAME_OFFSET_F1O_F11 + 8)
	35	#define FP_FRAME_OFFSET_F14_F15 (FP_FRAME_OFFSET_F12_F13 + 8)
	36	#define FP_FRAME_OFFSET_F16_F17 (FP_FRAME_OFFSET_F14_F15 + 8)
	37	#define FP_FRAME_OFFSET_F18_F19 (FP_FRAME_OFFSET_F16_F17 + 8)
	38	#define FP_FRAME_OFFSET_F2O_F21 (FP_FRAME_OFFSET_F18_F19 + 8)
	39	#define FP_FRAME_OFFSET_F22_F23 (FP_FRAME_OFFSET_F2O_F21 + 8)
	40	#define FP_FRAME_OFFSET_F24_F25 (FP_FRAME_OFFSET_F22_F23 + 8)
	41	#define FP_FRAME_OFFSET_F26_F27 (FP_FRAME_OFFSET_F24_F25 + 8)
	42	#define FP_FRAME_OFFSET_F28_F29 (FP_FRAME_OFFSET_F26_F27 + 8)
	43	#define FP_FRAME_OFFSET_F3O_F31 (FP_FRAME_OFFSET_F28_F29 + 8)
	44	#define FP_FRAME_OFFSET_FSR (FP_FRAME_OFFSET_F3O_F31 + 8)
	45	#define FP_FRAME_SIZE (FP_FRAME_OFFSET_FSR + 8)
	46	#endif
	47
[88f6c4fc]	48	/*
	49	* void _CPU_Context_switch(
	50	* Context_Control *run,
	51	* Context_Control *heir
	52	* )
	53	*
	54	* This routine performs a normal non-FP context switch.
	55	*/
	56
	57	.align 4
	58	PUBLIC(_CPU_Context_switch)
	59	SYM(_CPU_Context_switch):
[b2ec2d15]	60	st %g5, [%o0 + G5_OFFSET] ! save the global registers
[32b4a0c]	61
	62	/*
	63	* No need to save the thread pointer %g7 since it is a thread
	64	* invariant. It is initialized once in _CPU_Context_Initialize().
	65	*/
[88f6c4fc]	66
	67	std %l0, [%o0 + L0_OFFSET] ! save the local registers
[2f8704b6]	68	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	69	std %l2, [%o0 + L2_OFFSET]
[2f8704b6]	70	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	71	std %l4, [%o0 + L4_OFFSET]
[2f8704b6]	72	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	73	std %l6, [%o0 + L6_OFFSET]
[2f8704b6]	74	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	75
	76	std %i0, [%o0 + I0_OFFSET] ! save the input registers
[2f8704b6]	77	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	78	std %i2, [%o0 + I2_OFFSET]
[2f8704b6]	79	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	80	std %i4, [%o0 + I4_OFFSET]
[2f8704b6]	81	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	82	std %i6, [%o0 + I6_FP_OFFSET]
[2f8704b6]	83	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	84
[97cf623d]	85	std %o6, [%o0 + O6_SP_OFFSET] ! save the output registers
[88f6c4fc]	86
[f8ad6c6f]	87	! load the ISR stack nesting prevention flag
[c11ac2d5]	88	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
[f8ad6c6f]	89	! save it a bit later so we do not waste a couple of cycles
	90
[88f6c4fc]	91	rd %psr, %o2
	92	st %o2, [%o0 + PSR_OFFSET] ! save status register
	93
[f8ad6c6f]	94	! Now actually save ISR stack nesting prevention flag
	95	st %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
	96
[88f6c4fc]	97	/*
	98	* This is entered from _CPU_Context_restore with:
	99	* o1 = context to restore
	100	* o2 = psr
	101	*/
	102
	103	PUBLIC(_CPU_Context_restore_heir)
	104	SYM(_CPU_Context_restore_heir):
	105	/*
	106	* Flush all windows with valid contents except the current one.
	107	* In examining the set register windows, one may logically divide
	108	* the windows into sets (some of which may be empty) based on their
	109	* current status:
	110	*
	111	* + current (i.e. in use),
	112	* + used (i.e. a restore would not trap)
	113	* + invalid (i.e. 1 in corresponding bit in WIM)
	114	* + unused
	115	*
	116	* Either the used or unused set of windows may be empty.
	117	*
	118	* NOTE: We assume only one bit is set in the WIM at a time.
	119	*
	120	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
	121	* into sets as follows:
	122	*
	123	* + 0 - invalid
	124	* + 1-4 - unused
	125	* + 5 - current
	126	* + 6-7 - used
	127	*
	128	* In this case, we only would save the used windows -- 6 and 7.
	129	*
	130	* Traps are disabled for the same logical period as in a
	131	* flush all windows trap handler.
	132	*
	133	* Register Usage while saving the windows:
	134	* g1 = current PSR
	135	* g2 = current wim
	136	* g3 = CWP
	137	* g4 = wim scratch
	138	* g5 = scratch
	139	*/
	140
	141	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
[78cac9b]	142	andn %o2, SPARC_PSR_ET_MASK, %g1 ! g1 = psr with traps disabled
	143	mov %g1, %psr ! ** DISABLE TRAPS **
[88f6c4fc]	144	mov %wim, %g2 ! g2 = wim
	145	mov 1, %g4
	146	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
	147
	148	save_frame_loop:
	149	sll %g4, 1, %g5 ! rotate the "wim" left 1
	150	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
	151	or %g4, %g5, %g4 ! g4 = wim if we do one restore
	152
	153	/*
	154	* If a restore would not underflow, then continue.
	155	*/
	156
	157	andcc %g4, %g2, %g0 ! Any windows to flush?
	158	bnz done_flushing ! No, then continue
	159	nop
	160
	161	restore ! back one window
	162
	163	/*
	164	* Now save the window just as if we overflowed to it.
	165	*/
	166
	167	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
[2f8704b6]	168	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	169	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
[2f8704b6]	170	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	171	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
[2f8704b6]	172	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	173	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
[2f8704b6]	174	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	175
	176	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
[2f8704b6]	177	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	178	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
[2f8704b6]	179	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	180	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
[2f8704b6]	181	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	182	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
[2f8704b6]	183	SPARC_LEON3FT_B2BST_NOP
[88f6c4fc]	184
	185	ba save_frame_loop
	186	nop
	187
	188	done_flushing:
	189
[78cac9b]	190	! Wait three instructions after the write to PSR before using
	191	! non-global registers or instructions affecting the CWP
	192	mov %g1, %psr ! restore cwp
	193	add %g3, 1, %g2 ! calculate desired WIM
	194	and %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
[88f6c4fc]	195	mov 1, %g4
[78cac9b]	196	sll %g4, %g2, %g4 ! g4 = new WIM
[88f6c4fc]	197	mov %g4, %wim
	198
[38b59a6]	199	#if defined(RTEMS_SMP)
[d5e073c]	200	/*
	201	* The executing thread no longer executes on this processor. Switch
	202	* the stack to the temporary interrupt stack of this processor. Mark
	203	* the context of the executing thread as not executing.
	204	*/
	205	add %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp
[fbda4a8]	206	st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
	207
	208	! Try to update the is executing indicator of the heir context
	209	mov 1, %g1
	210
[d5e073c]	211	.Ltry_update_is_executing:
[38b59a6]	212
[fbda4a8]	213	swap [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
[38b59a6]	214	cmp %g1, 0
[d5e073c]	215	bne .Lcheck_is_executing
[38b59a6]	216
[fbda4a8]	217	! The next load is in a delay slot, which is all right
[38b59a6]	218	#endif
	219
[146adb1]	220	#if defined(SPARC_USE_LAZY_FP_SWITCH)
	221	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %g2
	222	#endif
[78cac9b]	223	ld [%o1 + PSR_OFFSET], %g1 ! g1 = heir psr with traps enabled
[146adb1]	224	#if defined(SPARC_USE_LAZY_FP_SWITCH)
	225	sethi %hi(SPARC_PSR_EF_MASK), %g5
	226	cmp %g2, %g0
	227	bne,a .Lclear_psr_ef_done
	228	andn %g1, %g5, %g1 ! g1 = heir psr w/o PSR[EF]
	229	.Lclear_psr_ef_done:
	230	#endif
[78cac9b]	231	andn %g1, SPARC_PSR_CWP_MASK, %g1 ! g1 = heir psr w/o cwp
	232	or %g1, %g3, %g1 ! g1 = heir psr with cwp
	233	mov %g1, %psr ! restore status register and
	234	! ** ENABLE TRAPS **
	235
[b2ec2d15]	236	ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
[7c0bd74]	237	ld [%o1 + G7_OFFSET], %g7
[88f6c4fc]	238
	239	! Load thread specific ISR dispatch prevention flag
	240	ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
	241	! Store it to memory later to use the cycles
	242
	243	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
	244	ldd [%o1 + L2_OFFSET], %l2
	245	ldd [%o1 + L4_OFFSET], %l4
	246	ldd [%o1 + L6_OFFSET], %l6
	247
	248	! Now restore thread specific ISR dispatch prevention flag
[c11ac2d5]	249	st %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
[88f6c4fc]	250
[20828099]	251	ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers
[88f6c4fc]	252	ldd [%o1 + I2_OFFSET], %i2
	253	ldd [%o1 + I4_OFFSET], %i4
	254	ldd [%o1 + I6_FP_OFFSET], %i6
	255
[97cf623d]	256	ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers
[88f6c4fc]	257
	258	jmp %o7 + 8 ! return
	259	nop ! delay slot
	260
[fbda4a8]	261	#if defined(RTEMS_SMP)
[d5e073c]	262	.Lcheck_is_executing:
[fbda4a8]	263
	264	! Check the is executing indicator of the heir context
	265	ld [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
	266	cmp %g1, 0
[d5e073c]	267	beq .Ltry_update_is_executing
[fbda4a8]	268	mov 1, %g1
	269
[258ad71]	270	! We may have a new heir
[fbda4a8]	271
	272	! Read the executing and heir
[d64f2e7]	273	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %g2
	274	ld [%g6 + PER_CPU_OFFSET_HEIR], %g4
[fbda4a8]	275
[258ad71]	276	! Update the executing only if necessary to avoid cache line
	277	! monopolization.
[d64f2e7]	278	cmp %g2, %g4
[d5e073c]	279	beq .Ltry_update_is_executing
[258ad71]	280	mov 1, %g1
	281
[fbda4a8]	282	! Calculate the heir context pointer
[d64f2e7]	283	sub %o1, %g2, %g2
	284	add %g2, %g4, %o1
[fbda4a8]	285
	286	! Update the executing
[d64f2e7]	287	st %g4, [%g6 + PER_CPU_OFFSET_EXECUTING]
[fbda4a8]	288
[d5e073c]	289	ba .Ltry_update_is_executing
[fbda4a8]	290	mov 1, %g1
	291	#endif
	292
[88f6c4fc]	293	/*
	294	* void _CPU_Context_restore(
	295	* Context_Control *new_context
	296	* )
	297	*
	298	* This routine is generally used only to perform restart self.
	299	*
	300	* NOTE: It is unnecessary to reload some registers.
	301	*/
	302	.align 4
	303	PUBLIC(_CPU_Context_restore)
	304	SYM(_CPU_Context_restore):
[427dcee]	305	save %sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
[88f6c4fc]	306	rd %psr, %o2
[38b59a6]	307	#if defined(RTEMS_SMP)
[26ffb8c2]	308	! On SPARC the restore path needs also a valid executing context on SMP
	309	! to update the is executing indicator.
[38b59a6]	310	mov %i0, %o0
	311	#endif
[88f6c4fc]	312	ba SYM(_CPU_Context_restore_heir)
	313	mov %i0, %o1 ! in the delay slot
	314
[5d69cd3]	315	/*
	316	* void _ISR_Handler()
	317	*
	318	* This routine provides the RTEMS interrupt management.
	319	*
	320	* We enter this handler from the 4 instructions in the trap table with
	321	* the following registers assumed to be set as shown:
	322	*
	323	* l0 = PSR
	324	* l1 = PC
	325	* l2 = nPC
	326	* l3 = trap type
	327	*
	328	* NOTE: By an executive defined convention, trap type is between 0 and 255 if
	329	* it is an asynchonous trap and 256 and 511 if it is synchronous.
	330	*/
	331
	332	.align 4
	333	PUBLIC(_ISR_Handler)
	334	SYM(_ISR_Handler):
	335	/*
	336	* Fix the return address for synchronous traps.
	337	*/
	338
	339	andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
	340	! Is this a synchronous trap?
	341	be,a win_ovflow ! No, then skip the adjustment
	342	nop ! DELAY
	343	mov %l1, %l6 ! save trapped pc for debug info
	344	mov %l2, %l1 ! do not return to the instruction
	345	add %l2, 4, %l2 ! indicated
	346
	347	win_ovflow:
	348	/*
	349	* Save the globals this block uses.
	350	*
	351	* These registers are not restored from the locals. Their contents
	352	* are saved directly from the locals into the ISF below.
	353	*/
	354
	355	mov %g4, %l4 ! save the globals this block uses
	356	mov %g5, %l5
	357
	358	/*
	359	* When at a "window overflow" trap, (wim == (1 << cwp)).
	360	* If we get here like that, then process a window overflow.
	361	*/
	362
	363	rd %wim, %g4
	364	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
	365	! are LS 5 bits ; how convenient :)
	366	cmp %g5, 1 ! Is this an invalid window?
	367	bne dont_do_the_window ! No, then skip all this stuff
	368	! we are using the delay slot
	369
	370	/*
	371	* The following is same as a 1 position right rotate of WIM
	372	*/
	373
	374	srl %g4, 1, %g5 ! g5 = WIM >> 1
	375	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
	376	! g4 = WIM << (Number Windows - 1)
	377	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
	378	! (WIM << (Number Windows - 1))
	379
	380	/*
	381	* At this point:
	382	*
	383	* g4 = the new WIM
	384	* g5 is free
	385	*/
	386
	387	/*
	388	* Since we are tinkering with the register windows, we need to
	389	* make sure that all the required information is in global registers.
	390	*/
	391
	392	save ! Save into the window
	393	wr %g4, 0, %wim ! WIM = new WIM
	394	nop ! delay slots
	395	nop
	396	nop
	397
	398	/*
	399	* Now save the window just as if we overflowed to it.
	400	*/
	401
	402	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
[2f8704b6]	403	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	404	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
[2f8704b6]	405	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	406	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
[2f8704b6]	407	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	408	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
[2f8704b6]	409	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	410
	411	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
[2f8704b6]	412	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	413	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
[2f8704b6]	414	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	415	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
[2f8704b6]	416	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	417	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
	418
	419	restore
	420	nop
	421
	422	dont_do_the_window:
	423	/*
	424	* Global registers %g4 and %g5 are saved directly from %l4 and
	425	* %l5 directly into the ISF below.
	426	*/
	427
	428	/*
	429	* Save the state of the interrupted task -- especially the global
	430	* registers -- in the Interrupt Stack Frame. Note that the ISF
	431	* includes a regular minimum stack frame which will be used if
	432	* needed by register window overflow and underflow handlers.
	433	*
	434	* REGISTERS SAME AS AT _ISR_Handler
	435	*/
	436
[c539a865]	437	sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
[5d69cd3]	438	! make space for ISF
	439
	440	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
[2f8704b6]	441	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	442	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
	443	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
	444	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
[2f8704b6]	445	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	446	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
[2f8704b6]	447	SPARC_LEON3FT_B2BST_NOP
[7c0bd74]	448	st %g7, [%sp + ISF_G7_OFFSET] ! save g7
[5d69cd3]	449
	450	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
[2f8704b6]	451	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	452	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
[2f8704b6]	453	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	454	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
[2f8704b6]	455	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	456	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
	457
	458	rd %y, %g1
	459	st %g1, [%sp + ISF_Y_OFFSET] ! save y
	460	st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
	461
	462	mov %sp, %o1 ! 2nd arg to ISR Handler
	463
[849bb7a3]	464	/*
	465	* Increment ISR nest level and Thread dispatch disable level.
	466	*
	467	* Register usage for this section:
	468	*
	469	* l6 = _Thread_Dispatch_disable_level value
	470	* l7 = _ISR_Nest_level value
	471	*
[7c0bd74]	472	* NOTE: It is assumed that l6 - l7 will be preserved until the ISR
[849bb7a3]	473	* nest and thread dispatch disable levels are unnested.
	474	*/
	475
[7c0bd74]	476	ld [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
	477	ld [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
[849bb7a3]	478
	479	add %l7, 1, %l7
[7c0bd74]	480	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
[2f8704b6]	481	SPARC_LEON3FT_B2BST_NOP
[849bb7a3]	482
[f715433]	483	add %l6, 1, %l6
[7c0bd74]	484	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
[f715433]	485
[2764bd43]	486	#if SPARC_HAS_FPU == 1
	487	/*
	488	* We cannot use an intermediate value for operations with the PSR[EF]
	489	* bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
	490	*/
	491	sethi %hi(SPARC_PSR_EF_MASK), %l5
	492	#endif
	493
[849bb7a3]	494	/*
	495	* If ISR nest level was zero (now 1), then switch stack.
	496	*/
	497
	498	mov %sp, %fp
	499	subcc %l7, 1, %l7 ! outermost interrupt handler?
	500	bnz dont_switch_stacks ! No, then do not switch stacks
	501
[9460333e]	502	#if defined(RTEMS_PROFILING)
	503	sethi %hi(_SPARC_Counter), %o5
	504	ld [%o5 + %lo(_SPARC_Counter)], %l4
[8639685]	505	call %l4
[9460333e]	506	nop
	507	mov %o0, %o5
[de5d6d0]	508	#else
	509	nop
	510	#endif
	511
[26ffb8c2]	512	ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
[849bb7a3]	513
[2764bd43]	514	#if SPARC_HAS_FPU == 1
	515	/*
	516	* Test if the interrupted thread uses the floating point unit
	517	* (PSR[EF] == 1). In case it uses the floating point unit, then store
	518	* the floating point status register. This has the side-effect that
	519	* all pending floating point operations complete before the store
	520	* completes. The PSR[EF] bit is restored after the call to the
	521	* interrupt handler. Thus post-switch actions (e.g. signal handlers)
	522	* and context switch extensions may still corrupt the floating point
	523	* context.
	524	*/
	525	andcc %l0, %l5, %g0
	526	bne,a dont_switch_stacks
	527	st %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
	528	#endif
	529
[849bb7a3]	530	dont_switch_stacks:
	531	/*
	532	* Make sure we have a place on the stack for the window overflow
	533	* trap handler to write into. At this point it is safe to
	534	* enable traps again.
	535	*/
	536
[427dcee]	537	sub %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
[849bb7a3]	538
[5d69cd3]	539	/*
	540	* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
	541	* set the PIL in the %psr to mask off interrupts with lower priority.
	542	* The original %psr in %l0 is not modified since it will be restored
	543	* when the interrupt handler returns.
	544	*/
	545
	546	mov %l0, %g5
[26ffb8c2]	547	and %l3, 0x0ff, %g4
[5d69cd3]	548	subcc %g4, 0x11, %g0
	549	bl dont_fix_pil
	550	subcc %g4, 0x1f, %g0
	551	bg dont_fix_pil
	552	sll %g4, 8, %g4
	553	and %g4, SPARC_PSR_PIL_MASK, %g4
	554	andn %l0, SPARC_PSR_PIL_MASK, %g5
	555	ba pil_fixed
	556	or %g4, %g5, %g5
	557	dont_fix_pil:
	558	or %g5, SPARC_PSR_PIL_MASK, %g5
	559	pil_fixed:
[2764bd43]	560
	561	#if SPARC_HAS_FPU == 1
	562	/*
	563	* Clear the PSR[EF] bit of the interrupted context to ensure that
	564	* interrupt service routines cannot corrupt the floating point context.
	565	*/
	566	andn %g5, %l5, %g5
	567	#endif
	568
[5d69cd3]	569	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
	570
	571	/*
	572	* Vector to user's handler.
	573	*
	574	* NOTE: TBR may no longer have vector number in it since
	575	* we just enabled traps. It is definitely in l3.
	576	*/
	577
	578	sethi %hi(SYM(_ISR_Vector_table)), %g4
[03b7789]	579	or %g4, %lo(SYM(_ISR_Vector_table)), %g4
[5d69cd3]	580	and %l3, 0xFF, %g5 ! remove synchronous trap indicator
	581	sll %g5, 2, %g5 ! g5 = offset into table
	582	ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
	583
	584
	585	! o1 = 2nd arg = address of the ISF
	586	! WAS LOADED WHEN ISF WAS SAVED!!!
	587	mov %l3, %o0 ! o0 = 1st arg = vector number
[8639685]	588	call %g4
[9460333e]	589	#if defined(RTEMS_PROFILING)
[de5d6d0]	590	mov %o5, %l3 ! save interrupt entry instant
[6a1b9e4]	591	#else
	592	nop ! delay slot
	593	#endif
	594
[146adb1]	595	#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
[6a1b9e4]	596	mov %l0, %g1 ! PSR[EF] value of interrupted context
	597	ta SPARC_SWTRAP_IRQDIS_FP ! ** DISABLE INTERRUPTS **
	598	#else
	599	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
	600	#endif
	601
	602	#if defined(RTEMS_PROFILING)
[de5d6d0]	603	cmp %l7, 0
	604	bne profiling_not_outer_most_exit
	605	nop
[8639685]	606	call %l4 ! Call _SPARC_Counter.counter_read
[6a1b9e4]	607	mov %g1, %l4 ! Save previous interrupt status
[9460333e]	608	mov %o0, %o2 ! o2 = 3rd arg = interrupt exit instant
[de5d6d0]	609	mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
[8639685]	610	call SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
[7c0bd74]	611	mov %g6, %o0 ! o0 = 1st arg = per-CPU control
[de5d6d0]	612	profiling_not_outer_most_exit:
	613	#endif
[5d69cd3]	614
	615	/*
	616	* Decrement ISR nest level and Thread dispatch disable level.
	617	*
	618	* Register usage for this section:
	619	*
[6a1b9e4]	620	* o2 = g6->dispatch_necessary value
	621	* o3 = g6->isr_dispatch_disable value
	622	* l6 = g6->thread_dispatch_disable_level value
	623	* l7 = g6->isr_nest_level value
[5d69cd3]	624	*/
	625
[6a1b9e4]	626	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
	627	ld [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
[7c0bd74]	628	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
[2f8704b6]	629	SPARC_LEON3FT_B2BST_NOP
[5d69cd3]	630	sub %l6, 1, %l6
[7c0bd74]	631	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
[5d69cd3]	632
	633	/*
[6a1b9e4]	634	* Thread dispatching is necessary and allowed if and only if
	635	* g6->dispatch_necessary == 1 and
	636	* g6->isr_dispatch_disable == 0 and
	637	* g6->thread_dispatch_disable_level == 0.
	638	*
	639	* Otherwise, continue with the simple return.
[5d69cd3]	640	*/
[6a1b9e4]	641	xor %o2, 1, %o2
	642	or %o2, %l6, %o2
	643	orcc %o2, %o3, %o2
	644	bnz simple_return
[5d69cd3]	645
	646	/*
[6a1b9e4]	647	* Switch back on the interrupted tasks stack and add enough room to
	648	* invoke the dispatcher. Doing this in the delay slot causes no harm,
	649	* since the stack pointer (%sp) is not used in the simple return path.
[5d69cd3]	650	*/
[6a1b9e4]	651	sub %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
[5d69cd3]	652
[6a1b9e4]	653	isr_dispatch:
[5d69cd3]	654
[6a1b9e4]	655	/* Set ISR dispatch disable and thread dispatch disable level to one */
	656	mov 1, %l6
	657	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
[c11ac2d5]	658	st %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
[5d69cd3]	659
[6a1b9e4]	660	/* Call _Thread_Do_dispatch(), this function will enable interrupts */
[5d69cd3]	661
[6a1b9e4]	662	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
[a51b352]	663
[146adb1]	664	#if defined(SPARC_USE_LAZY_FP_SWITCH)
	665	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
	666	andcc %l0, %l5, %g0
	667	be .Lnon_fp_thread_dispatch
	668	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %l6
	669
	670	/* Set new floating point unit owner to executing thread */
	671	st %l6, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
	672
	673	call SYM(_Thread_Do_dispatch)
	674	mov %g6, %o0
	675
	676	/*
	677	* If we are still the floating point unit owner, then reset the
	678	* floating point unit owner to NULL, otherwise clear PSR[EF] in the
	679	* interrupt frame and let the FP disabled system call do the floating
	680	* point context save/restore.
	681	*/
	682	ld [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET], %l7
	683	cmp %l6, %l7
[2a720f4]	684	bne,a .Ldisable_fp
[146adb1]	685	andn %l0, %l5, %l0
[0cae482a]	686	st %g0, [%g6 + SPARC_PER_CPU_FP_OWNER_OFFSET]
[146adb1]	687	ba .Lthread_dispatch_done
[0cae482a]	688	nop
[146adb1]	689	.Ldisable_fp:
[0cae482a]	690	st %l0, [%fp + ISF_PSR_OFFSET]
[146adb1]	691	ba .Lthread_dispatch_done
[0cae482a]	692	nop
[146adb1]	693	.Lnon_fp_thread_dispatch:
	694	#elif defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
[a51b352]	695	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
	696	andcc %l0, %l5, %g0
[146adb1]	697	be .Lnon_fp_thread_dispatch
[a51b352]	698	nop
	699
	700	/*
	701	* Yes, this is a floating point thread, then save the floating point
	702	* context to a new stack frame. Then do the thread dispatch.
	703	* Post-switch actions (e.g. signal handlers) and context switch
	704	* extensions may safely use the floating point unit.
	705	*/
	706	sub %sp, FP_FRAME_SIZE, %sp
	707	std %f0, [%sp + FP_FRAME_OFFSET_FO_F1]
[2f8704b6]	708	SPARC_LEON3FT_B2BST_NOP
[a51b352]	709	std %f2, [%sp + FP_FRAME_OFFSET_F2_F3]
[2f8704b6]	710	SPARC_LEON3FT_B2BST_NOP
[a51b352]	711	std %f4, [%sp + FP_FRAME_OFFSET_F4_F5]
[2f8704b6]	712	SPARC_LEON3FT_B2BST_NOP
[a51b352]	713	std %f6, [%sp + FP_FRAME_OFFSET_F6_F7]
[2f8704b6]	714	SPARC_LEON3FT_B2BST_NOP
[a51b352]	715	std %f8, [%sp + FP_FRAME_OFFSET_F8_F9]
[2f8704b6]	716	SPARC_LEON3FT_B2BST_NOP
[a51b352]	717	std %f10, [%sp + FP_FRAME_OFFSET_F1O_F11]
[2f8704b6]	718	SPARC_LEON3FT_B2BST_NOP
[a51b352]	719	std %f12, [%sp + FP_FRAME_OFFSET_F12_F13]
[2f8704b6]	720	SPARC_LEON3FT_B2BST_NOP
[a51b352]	721	std %f14, [%sp + FP_FRAME_OFFSET_F14_F15]
[2f8704b6]	722	SPARC_LEON3FT_B2BST_NOP
[a51b352]	723	std %f16, [%sp + FP_FRAME_OFFSET_F16_F17]
[2f8704b6]	724	SPARC_LEON3FT_B2BST_NOP
[a51b352]	725	std %f18, [%sp + FP_FRAME_OFFSET_F18_F19]
[2f8704b6]	726	SPARC_LEON3FT_B2BST_NOP
[a51b352]	727	std %f20, [%sp + FP_FRAME_OFFSET_F2O_F21]
[2f8704b6]	728	SPARC_LEON3FT_B2BST_NOP
[a51b352]	729	std %f22, [%sp + FP_FRAME_OFFSET_F22_F23]
[2f8704b6]	730	SPARC_LEON3FT_B2BST_NOP
[a51b352]	731	std %f24, [%sp + FP_FRAME_OFFSET_F24_F25]
[2f8704b6]	732	SPARC_LEON3FT_B2BST_NOP
[a51b352]	733	std %f26, [%sp + FP_FRAME_OFFSET_F26_F27]
[2f8704b6]	734	SPARC_LEON3FT_B2BST_NOP
[a51b352]	735	std %f28, [%sp + FP_FRAME_OFFSET_F28_F29]
[2f8704b6]	736	SPARC_LEON3FT_B2BST_NOP
[a51b352]	737	std %f30, [%sp + FP_FRAME_OFFSET_F3O_F31]
[2f8704b6]	738	SPARC_LEON3FT_B2BST_NOP
[6a1b9e4]	739	st %fsr, [%sp + FP_FRAME_OFFSET_FSR]
[8639685]	740	call SYM(_Thread_Do_dispatch)
[6a1b9e4]	741	mov %g6, %o0
[a51b352]	742
	743	/*
	744	* Restore the floating point context from stack frame and release the
	745	* stack frame.
	746	*/
	747	ldd [%sp + FP_FRAME_OFFSET_FO_F1], %f0
	748	ldd [%sp + FP_FRAME_OFFSET_F2_F3], %f2
	749	ldd [%sp + FP_FRAME_OFFSET_F4_F5], %f4
	750	ldd [%sp + FP_FRAME_OFFSET_F6_F7], %f6
	751	ldd [%sp + FP_FRAME_OFFSET_F8_F9], %f8
	752	ldd [%sp + FP_FRAME_OFFSET_F1O_F11], %f10
	753	ldd [%sp + FP_FRAME_OFFSET_F12_F13], %f12
	754	ldd [%sp + FP_FRAME_OFFSET_F14_F15], %f14
	755	ldd [%sp + FP_FRAME_OFFSET_F16_F17], %f16
	756	ldd [%sp + FP_FRAME_OFFSET_F18_F19], %f18
	757	ldd [%sp + FP_FRAME_OFFSET_F2O_F21], %f20
	758	ldd [%sp + FP_FRAME_OFFSET_F22_F23], %f22
	759	ldd [%sp + FP_FRAME_OFFSET_F24_F25], %f24
	760	ldd [%sp + FP_FRAME_OFFSET_F26_F27], %f26
	761	ldd [%sp + FP_FRAME_OFFSET_F28_F29], %f28
	762	ldd [%sp + FP_FRAME_OFFSET_F3O_F31], %f30
	763	ld [%sp + FP_FRAME_OFFSET_FSR], %fsr
[146adb1]	764	ba .Lthread_dispatch_done
[a51b352]	765	add %sp, FP_FRAME_SIZE, %sp
	766
[146adb1]	767	.Lnon_fp_thread_dispatch:
[a51b352]	768	#endif
	769
[8639685]	770	call SYM(_Thread_Do_dispatch)
[6a1b9e4]	771	mov %g6, %o0
[5d69cd3]	772
[146adb1]	773	#if SPARC_HAS_FPU == 1
	774	.Lthread_dispatch_done:
[a51b352]	775	#endif
	776
[6a1b9e4]	777	ta SPARC_SWTRAP_IRQDIS ! ** DISABLE INTERRUPTS **
[5d69cd3]	778
	779	/*
	780	* While we had ISR dispatching disabled in this thread,
[6a1b9e4]	781	* did we miss anything? If so, then we need to do another
	782	* _Thread_Do_dispatch() before leaving this ISR dispatch context.
[5d69cd3]	783	*/
[dff1803]	784	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
[5d69cd3]	785
[6a1b9e4]	786	orcc %l7, %g0, %g0 ! Is a thread dispatch necessary?
	787	bne isr_dispatch ! Yes, then invoke the dispatcher again.
	788	mov 0, %o1 ! ISR level for _Thread_Do_dispatch()
[5d69cd3]	789
[6a1b9e4]	790	/*
	791	* No, then set the ISR dispatch disable flag to zero and continue with
	792	* the simple return.
	793	*/
[c11ac2d5]	794	st %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
[5d69cd3]	795
	796	/*
	797	* The CWP in place at this point may be different from
	798	* that which was in effect at the beginning of the ISR if we
	799	* have been context switched between the beginning of this invocation
	800	* of _ISR_Handler and this point. Thus the CWP and WIM should
	801	* not be changed back to their values at ISR entry time. Any
	802	* changes to the PSR must preserve the CWP.
	803	*/
	804
	805	simple_return:
	806	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
	807	wr %l5, 0, %y
	808
	809	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
	810	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
	811	rd %psr, %l3
	812	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
	813	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
	814	or %l3, %l0, %l0 ! install it later...
	815	andn %l0, SPARC_PSR_ET_MASK, %l0
	816
	817	/*
	818	* Restore tasks global and out registers
	819	*/
	820
	821	mov %fp, %g1
	822
	823	! g1 is restored later
	824	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
	825	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
[7c0bd74]	826	ld [%fp + ISF_G7_OFFSET], %g7 ! restore g7
[5d69cd3]	827
	828	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
	829	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
	830	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
	831	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
	832
	833	/*
	834	* Registers:
	835	*
	836	* ALL global registers EXCEPT G1 and the input registers have
	837	* already been restored and thuse off limits.
	838	*
	839	* The following is the contents of the local registers:
	840	*
	841	* l0 = original psr
	842	* l1 = return address (i.e. PC)
	843	* l2 = nPC
	844	* l3 = CWP
	845	*/
	846
	847	/*
	848	* if (CWP + 1) is an invalid window then we need to reload it.
	849	*
	850	* WARNING: Traps should now be disabled
	851	*/
	852
	853	mov %l0, %psr ! ** DISABLE TRAPS **
	854	nop
	855	nop
	856	nop
	857	rd %wim, %l4
	858	add %l0, 1, %l6 ! l6 = cwp + 1
	859	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
	860	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
	861	! and CWP are conveniently LS 5 bits
	862	cmp %l5, 1 ! Is tasks window invalid?
	863	bne good_task_window
	864
	865	/*
	866	* The following code is the same as a 1 position left rotate of WIM.
	867	*/
	868
	869	sll %l4, 1, %l5 ! l5 = WIM << 1
	870	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
	871	! l4 = WIM >> (Number Windows - 1)
	872	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
	873	! (WIM >> (Number Windows - 1))
	874
	875	/*
	876	* Now restore the window just as if we underflowed to it.
	877	*/
	878
	879	wr %l4, 0, %wim ! WIM = new WIM
	880	nop ! must delay after writing WIM
	881	nop
	882	nop
	883	restore ! now into the tasks window
	884
	885	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
	886	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
	887	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
	888	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
	889	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
	890	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
	891	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
	892	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
	893	! reload of sp clobbers ISF
	894	save ! Back to ISR dispatch window
	895
	896	good_task_window:
	897
	898	mov %l0, %psr ! ** DISABLE TRAPS **
[26ffb8c2]	899	nop; nop; nop
[5d69cd3]	900	! and restore condition codes.
	901	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
	902	jmp %l1 ! transfer control and
	903	rett %l2 ! go back to tasks window
	904
	905	/* end of file */

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