1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSScoreCPUSPARC |
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7 | * |
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8 | * @brief This source file contains static assertions to ensure the consistency |
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9 | * of interfaces used in C and assembler and it contains the SPARC-specific |
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10 | * implementation of _CPU_Initialize(), _CPU_ISR_Get_level(), and |
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11 | * _CPU_Context_Initialize(). |
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12 | */ |
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13 | |
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14 | /* |
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15 | * COPYRIGHT (c) 1989-2007. |
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16 | * On-Line Applications Research Corporation (OAR). |
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17 | * |
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18 | * Copyright (c) 2017 embedded brains GmbH |
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19 | * |
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20 | * Redistribution and use in source and binary forms, with or without |
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21 | * modification, are permitted provided that the following conditions |
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22 | * are met: |
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23 | * 1. Redistributions of source code must retain the above copyright |
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24 | * notice, this list of conditions and the following disclaimer. |
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25 | * 2. Redistributions in binary form must reproduce the above copyright |
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26 | * notice, this list of conditions and the following disclaimer in the |
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27 | * documentation and/or other materials provided with the distribution. |
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28 | * |
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29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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30 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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31 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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32 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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33 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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34 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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37 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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39 | * POSSIBILITY OF SUCH DAMAGE. |
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40 | */ |
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41 | |
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42 | #ifdef HAVE_CONFIG_H |
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43 | #include "config.h" |
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44 | #endif |
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45 | |
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46 | #include <rtems/score/percpu.h> |
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47 | #include <rtems/score/tls.h> |
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48 | #include <rtems/score/thread.h> |
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49 | |
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50 | #if SPARC_HAS_FPU == 1 |
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51 | RTEMS_STATIC_ASSERT( |
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52 | offsetof( Per_CPU_Control, cpu_per_cpu.fsr) |
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53 | == SPARC_PER_CPU_FSR_OFFSET, |
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54 | SPARC_PER_CPU_FSR_OFFSET |
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55 | ); |
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56 | |
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57 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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58 | RTEMS_STATIC_ASSERT( |
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59 | offsetof( Per_CPU_Control, cpu_per_cpu.fp_owner) |
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60 | == SPARC_PER_CPU_FP_OWNER_OFFSET, |
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61 | SPARC_PER_CPU_FP_OWNER_OFFSET |
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62 | ); |
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63 | #endif |
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64 | #endif |
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65 | |
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66 | #define SPARC_ASSERT_OFFSET(field, off) \ |
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67 | RTEMS_STATIC_ASSERT( \ |
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68 | offsetof(Context_Control, field) == off ## _OFFSET, \ |
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69 | Context_Control_offset_ ## field \ |
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70 | ) |
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71 | |
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72 | SPARC_ASSERT_OFFSET(g5, G5); |
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73 | SPARC_ASSERT_OFFSET(g7, G7); |
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74 | |
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75 | RTEMS_STATIC_ASSERT( |
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76 | offsetof(Context_Control, l0_and_l1) == L0_OFFSET, |
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77 | Context_Control_offset_L0 |
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78 | ); |
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79 | |
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80 | RTEMS_STATIC_ASSERT( |
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81 | offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET, |
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82 | Context_Control_offset_L1 |
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83 | ); |
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84 | |
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85 | SPARC_ASSERT_OFFSET(l2, L2); |
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86 | SPARC_ASSERT_OFFSET(l3, L3); |
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87 | SPARC_ASSERT_OFFSET(l4, L4); |
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88 | SPARC_ASSERT_OFFSET(l5, L5); |
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89 | SPARC_ASSERT_OFFSET(l6, L6); |
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90 | SPARC_ASSERT_OFFSET(l7, L7); |
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91 | SPARC_ASSERT_OFFSET(i0, I0); |
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92 | SPARC_ASSERT_OFFSET(i1, I1); |
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93 | SPARC_ASSERT_OFFSET(i2, I2); |
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94 | SPARC_ASSERT_OFFSET(i3, I3); |
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95 | SPARC_ASSERT_OFFSET(i4, I4); |
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96 | SPARC_ASSERT_OFFSET(i5, I5); |
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97 | SPARC_ASSERT_OFFSET(i6_fp, I6_FP); |
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98 | SPARC_ASSERT_OFFSET(i7, I7); |
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99 | SPARC_ASSERT_OFFSET(o6_sp, O6_SP); |
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100 | SPARC_ASSERT_OFFSET(o7, O7); |
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101 | SPARC_ASSERT_OFFSET(psr, PSR); |
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102 | SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); |
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103 | |
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104 | #if defined(RTEMS_SMP) |
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105 | SPARC_ASSERT_OFFSET(is_executing, SPARC_CONTEXT_CONTROL_IS_EXECUTING); |
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106 | #endif |
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107 | |
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108 | #define SPARC_ASSERT_ISF_OFFSET(field, off) \ |
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109 | RTEMS_STATIC_ASSERT( \ |
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110 | offsetof(CPU_Interrupt_frame, field) == ISF_ ## off ## _OFFSET, \ |
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111 | CPU_Interrupt_frame_offset_ ## field \ |
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112 | ) |
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113 | |
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114 | SPARC_ASSERT_ISF_OFFSET(psr, PSR); |
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115 | SPARC_ASSERT_ISF_OFFSET(pc, PC); |
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116 | SPARC_ASSERT_ISF_OFFSET(npc, NPC); |
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117 | SPARC_ASSERT_ISF_OFFSET(g1, G1); |
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118 | SPARC_ASSERT_ISF_OFFSET(g2, G2); |
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119 | SPARC_ASSERT_ISF_OFFSET(g3, G3); |
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120 | SPARC_ASSERT_ISF_OFFSET(g4, G4); |
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121 | SPARC_ASSERT_ISF_OFFSET(g5, G5); |
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122 | SPARC_ASSERT_ISF_OFFSET(g7, G7); |
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123 | SPARC_ASSERT_ISF_OFFSET(i0, I0); |
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124 | SPARC_ASSERT_ISF_OFFSET(i1, I1); |
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125 | SPARC_ASSERT_ISF_OFFSET(i2, I2); |
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126 | SPARC_ASSERT_ISF_OFFSET(i3, I3); |
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127 | SPARC_ASSERT_ISF_OFFSET(i4, I4); |
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128 | SPARC_ASSERT_ISF_OFFSET(i5, I5); |
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129 | SPARC_ASSERT_ISF_OFFSET(i6_fp, I6_FP); |
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130 | SPARC_ASSERT_ISF_OFFSET(i7, I7); |
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131 | SPARC_ASSERT_ISF_OFFSET(y, Y); |
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132 | SPARC_ASSERT_ISF_OFFSET(tpc, TPC); |
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133 | |
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134 | #define SPARC_ASSERT_FP_OFFSET(field, off) \ |
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135 | RTEMS_STATIC_ASSERT( \ |
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136 | offsetof(Context_Control_fp, field) == SPARC_FP_CONTEXT_OFFSET_ ## off, \ |
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137 | Context_Control_fp_offset_ ## field \ |
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138 | ) |
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139 | |
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140 | SPARC_ASSERT_FP_OFFSET(f0_f1, F0_F1); |
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141 | SPARC_ASSERT_FP_OFFSET(f2_f3, F2_F3); |
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142 | SPARC_ASSERT_FP_OFFSET(f4_f5, F4_F5); |
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143 | SPARC_ASSERT_FP_OFFSET(f6_f7, F6_F7); |
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144 | SPARC_ASSERT_FP_OFFSET(f8_f9, F8_F9); |
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145 | SPARC_ASSERT_FP_OFFSET(f10_f11, F10_F11); |
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146 | SPARC_ASSERT_FP_OFFSET(f12_f13, F12_F13); |
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147 | SPARC_ASSERT_FP_OFFSET(f14_f15, F14_F15); |
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148 | SPARC_ASSERT_FP_OFFSET(f16_f17, F16_F17); |
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149 | SPARC_ASSERT_FP_OFFSET(f18_f19, F18_F19); |
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150 | SPARC_ASSERT_FP_OFFSET(f20_f21, F20_F21); |
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151 | SPARC_ASSERT_FP_OFFSET(f22_f23, F22_F23); |
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152 | SPARC_ASSERT_FP_OFFSET(f24_f25, F24_F25); |
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153 | SPARC_ASSERT_FP_OFFSET(f26_f27, F26_F27); |
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154 | SPARC_ASSERT_FP_OFFSET(f28_f29, F28_F29); |
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155 | SPARC_ASSERT_FP_OFFSET(f30_f31, F30_F31); |
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156 | SPARC_ASSERT_FP_OFFSET(fsr, FSR); |
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157 | |
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158 | RTEMS_STATIC_ASSERT( |
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159 | sizeof(SPARC_Minimum_stack_frame) == SPARC_MINIMUM_STACK_FRAME_SIZE, |
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160 | SPARC_MINIMUM_STACK_FRAME_SIZE |
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161 | ); |
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162 | |
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163 | /* https://devel.rtems.org/ticket/2352 */ |
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164 | RTEMS_STATIC_ASSERT( |
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165 | sizeof(CPU_Interrupt_frame) % CPU_ALIGNMENT == 0, |
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166 | CPU_Interrupt_frame_alignment |
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167 | ); |
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168 | |
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169 | #define SPARC_ASSERT_REGISTER_WINDOW_OFFSET( member, off ) \ |
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170 | RTEMS_STATIC_ASSERT( \ |
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171 | offsetof( SPARC_Register_window, member ) == \ |
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172 | RTEMS_XCONCAT( SPARC_REGISTER_WINDOW_OFFSET_, off ), \ |
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173 | SPARC_Register_window ## member \ |
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174 | ) |
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175 | |
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176 | SPARC_ASSERT_REGISTER_WINDOW_OFFSET( local[ 0 ], LOCAL( 0 ) ); |
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177 | SPARC_ASSERT_REGISTER_WINDOW_OFFSET( local[ 1 ], LOCAL( 1 ) ); |
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178 | SPARC_ASSERT_REGISTER_WINDOW_OFFSET( input[ 0 ], INPUT( 0 ) ); |
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179 | SPARC_ASSERT_REGISTER_WINDOW_OFFSET( input[ 1 ], INPUT( 1 ) ); |
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180 | |
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181 | RTEMS_STATIC_ASSERT( |
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182 | sizeof( SPARC_Register_window ) == SPARC_REGISTER_WINDOW_SIZE, |
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183 | SPARC_REGISTER_WINDOW_SIZE |
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184 | ); |
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185 | |
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186 | #define SPARC_ASSERT_EXCEPTION_OFFSET( member, off ) \ |
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187 | RTEMS_STATIC_ASSERT( \ |
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188 | offsetof( CPU_Exception_frame, member ) == \ |
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189 | RTEMS_XCONCAT( SPARC_EXCEPTION_OFFSET_, off ), \ |
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190 | CPU_Exception_frame_offset_ ## member \ |
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191 | ) |
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192 | |
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193 | SPARC_ASSERT_EXCEPTION_OFFSET( psr, PSR ); |
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194 | SPARC_ASSERT_EXCEPTION_OFFSET( pc, PC ); |
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195 | SPARC_ASSERT_EXCEPTION_OFFSET( npc, NPC ); |
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196 | SPARC_ASSERT_EXCEPTION_OFFSET( trap, TRAP ); |
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197 | SPARC_ASSERT_EXCEPTION_OFFSET( wim, WIM ); |
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198 | SPARC_ASSERT_EXCEPTION_OFFSET( y, Y ); |
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199 | SPARC_ASSERT_EXCEPTION_OFFSET( global[ 0 ], GLOBAL( 0 ) ); |
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200 | SPARC_ASSERT_EXCEPTION_OFFSET( global[ 1 ], GLOBAL( 1 ) ); |
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201 | SPARC_ASSERT_EXCEPTION_OFFSET( output[ 0 ], OUTPUT( 0 ) ); |
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202 | SPARC_ASSERT_EXCEPTION_OFFSET( output[ 1 ], OUTPUT( 1 ) ); |
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203 | |
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204 | #if SPARC_HAS_FPU == 1 |
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205 | SPARC_ASSERT_EXCEPTION_OFFSET( fsr, FSR ); |
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206 | SPARC_ASSERT_EXCEPTION_OFFSET( fp[ 0 ], FP( 0 ) ); |
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207 | SPARC_ASSERT_EXCEPTION_OFFSET( fp[ 1 ], FP( 1 ) ); |
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208 | #endif |
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209 | |
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210 | RTEMS_STATIC_ASSERT( |
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211 | sizeof( CPU_Exception_frame ) == SPARC_EXCEPTION_FRAME_SIZE, |
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212 | SPARC_EXCEPTION_FRAME_SIZE |
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213 | ); |
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214 | |
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215 | RTEMS_STATIC_ASSERT( |
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216 | sizeof( CPU_Exception_frame ) % CPU_ALIGNMENT == 0, |
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217 | CPU_Exception_frame_alignment |
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218 | ); |
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219 | |
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220 | /* |
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221 | * _CPU_Initialize |
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222 | * |
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223 | * This routine performs processor dependent initialization. |
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224 | * |
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225 | * INPUT PARAMETERS: NONE |
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226 | * |
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227 | * Output Parameters: NONE |
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228 | * |
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229 | * NOTE: There is no need to save the pointer to the thread dispatch routine. |
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230 | * The SPARC's assembly code can reference it directly with no problems. |
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231 | */ |
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232 | |
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233 | void _CPU_Initialize(void) |
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234 | { |
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235 | #if defined(SPARC_USE_LAZY_FP_SWITCH) |
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236 | __asm__ volatile ( |
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237 | ".global SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET\n" |
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238 | ".set SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET, %0\n" |
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239 | ".global SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET\n" |
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240 | ".set SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET, %1\n" |
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241 | : |
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242 | : "i" (offsetof(Thread_Control, Registers.fp_context)), |
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243 | "i" (offsetof(Thread_Control, fp_context)) |
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244 | ); |
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245 | #endif |
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246 | } |
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247 | |
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248 | uint32_t _CPU_ISR_Get_level( void ) |
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249 | { |
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250 | uint32_t level; |
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251 | |
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252 | sparc_get_interrupt_level( level ); |
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253 | |
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254 | return level; |
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255 | } |
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256 | |
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257 | void _CPU_Context_Initialize( |
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258 | Context_Control *the_context, |
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259 | uint32_t *stack_base, |
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260 | uint32_t size, |
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261 | uint32_t new_level, |
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262 | void *entry_point, |
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263 | bool is_fp, |
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264 | void *tls_area |
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265 | ) |
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266 | { |
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267 | uint32_t stack_high; /* highest "stack aligned" address */ |
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268 | uint32_t tmp_psr; |
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269 | |
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270 | /* |
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271 | * On CPUs with stacks which grow down (i.e. SPARC), we build the stack |
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272 | * based on the stack_high address. |
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273 | */ |
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274 | |
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275 | stack_high = ((uint32_t)(stack_base) + size); |
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276 | stack_high &= ~(CPU_STACK_ALIGNMENT - 1); |
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277 | |
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278 | /* |
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279 | * See the README in this directory for a diagram of the stack. |
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280 | */ |
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281 | |
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282 | the_context->o7 = ((uint32_t) entry_point) - 8; |
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283 | the_context->o6_sp = stack_high - SPARC_MINIMUM_STACK_FRAME_SIZE; |
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284 | the_context->i6_fp = 0; |
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285 | |
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286 | /* |
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287 | * Build the PSR for the task. Most everything can be 0 and the |
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288 | * CWP is corrected during the context switch. |
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289 | * |
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290 | * The EF bit determines if the floating point unit is available. |
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291 | * The FPU is ONLY enabled if the context is associated with an FP task |
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292 | * and this SPARC model has an FPU. |
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293 | */ |
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294 | |
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295 | sparc_get_psr( tmp_psr ); |
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296 | tmp_psr &= ~SPARC_PSR_PIL_MASK; |
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297 | tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; |
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298 | tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ |
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299 | |
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300 | /* _CPU_Context_restore_heir() relies on this */ |
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301 | _Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 ); |
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302 | |
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303 | #if (SPARC_HAS_FPU == 1) |
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304 | /* |
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305 | * If this bit is not set, then a task gets a fault when it accesses |
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306 | * a floating point register. This is a nice way to detect floating |
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307 | * point tasks which are not currently declared as such. |
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308 | */ |
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309 | |
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310 | if ( is_fp ) |
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311 | tmp_psr |= SPARC_PSR_EF_MASK; |
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312 | #endif |
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313 | the_context->psr = tmp_psr; |
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314 | |
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315 | /* |
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316 | * Since THIS thread is being created, there is no way that THIS |
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317 | * thread can have an interrupt stack frame on its stack. |
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318 | */ |
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319 | the_context->isr_dispatch_disable = 0; |
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320 | |
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321 | if ( tls_area != NULL ) { |
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322 | void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area ); |
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323 | |
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324 | the_context->g7 = (uintptr_t) tcb; |
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325 | } |
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326 | } |
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