source: rtems/cpukit/score/cpu/sparc/cpu.c @ c62d36f

4.104.114.84.95
Last change on this file since c62d36f was c62d36f, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 6, 1995 at 8:01:20 PM

SPARC merged and successfully tested w/o interrupt support

  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  $Id$
5 */
6
7#include <rtems/system.h>
8#include <rtems/score/isr.h>
9
10/*  _CPU_Initialize
11 *
12 *  This routine performs processor dependent initialization.
13 *
14 *  INPUT PARAMETERS:
15 *    cpu_table       - CPU table to initialize
16 *    thread_dispatch - address of disptaching routine
17 */
18
19
20void _CPU_Initialize(
21  rtems_cpu_table  *cpu_table,
22  void      (*thread_dispatch)      /* ignored on this CPU */
23)
24{
25  void *pointer;
26
27  /*
28   *  The thread_dispatch argument is the address of the entry point
29   *  for the routine called at the end of an ISR once it has been
30   *  decided a context switch is necessary.  On some compilation
31   *  systems it is difficult to call a high-level language routine
32   *  from assembly.  This allows us to trick these systems.
33   *
34   *  If you encounter this problem save the entry point in a CPU
35   *  dependent variable.
36   */
37
38  _CPU_Thread_dispatch_pointer = thread_dispatch;
39
40  /*
41   *  If there is not an easy way to initialize the FP context
42   *  during Context_Initialize, then it is usually easier to
43   *  save an "uninitialized" FP context here and copy it to
44   *  the task's during Context_Initialize.
45   */
46
47  pointer = &_CPU_Null_fp_context;
48  _CPU_Context_save_fp( &pointer );
49
50  _CPU_Table = *cpu_table;
51}
52
53/*PAGE
54 *
55 *  _CPU_ISR_Get_level
56 */
57 
58unsigned32 _CPU_ISR_Get_level( void )
59{
60  unsigned32 level;
61 
62  sparc_get_interrupt_level( level );
63 
64  return level;
65}
66
67/*  _CPU_ISR_install_vector
68 *
69 *  This kernel routine installs the RTEMS handler for the
70 *  specified vector.
71 *
72 *  Input parameters:
73 *    vector      - interrupt vector number
74 *    old_handler - former ISR for this vector number
75 *    new_handler - replacement ISR for this vector number
76 *
77 *  Output parameters:  NONE
78 *
79 */
80
81
82void _CPU_ISR_install_vector(
83  unsigned32  vector,
84  proc_ptr    new_handler,
85  proc_ptr   *old_handler
86)
87{
88   *old_handler = _ISR_Vector_table[ vector ];
89
90   /*
91    *  If the interrupt vector table is a table of pointer to isr entry
92    *  points, then we need to install the appropriate RTEMS interrupt
93    *  handler for this vector number.
94    */
95
96   /*
97    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
98    *  be used by the _ISR_Handler so the user gets control.
99    */
100
101    _ISR_Vector_table[ vector ] = new_handler;
102}
103
104/*PAGE
105 *
106 *  _CPU_Install_interrupt_stack
107 */
108
109void _CPU_Install_interrupt_stack( void )
110{
111}
112
113/*PAGE
114 *
115 *  _CPU_Context_Initialize
116 */
117
118/*
119 *  The following constants assist in building a thread's initial context.
120 */
121
122#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
123#define ADDR_ADJ_OFFSET  -8
124
125void _CPU_Context_Initialize(
126  Context_Control  *_the_context,
127  unsigned32       *_stack_base,
128  unsigned32        _size,
129  unsigned32        _new_level,
130  void             *_entry_point
131)
132{
133    unsigned32   jmp_addr;
134    unsigned32   _stack_high;  /* highest "stack aligned" address */
135    unsigned32   _the_size;
136    unsigned32   tmp_psr;
137 
138    jmp_addr = (unsigned32) _entry_point;
139 
140    /*
141     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
142     *  based on the _stack_high address. 
143     */
144 
145    _stack_high = ((unsigned32)(_stack_base) + _size);
146    _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
147 
148    _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
149 
150/* XXX following code is based on unix port */
151    /*
152     *  XXX SPARC port needs a diagram like this one...
153     *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
154     *  diagram of the stack.
155     */
156 
157    _the_context->o7 = jmp_addr + ADDR_ADJ_OFFSET;
158    _the_context->o6 = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
159    _the_context->i6 = (unsigned32)(_stack_high);
160#if 0
161    _the_context->rp = jmp_addr + ADDR_ADJ_OFFSET;
162    _the_context->sp = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
163    _the_context->fp = (unsigned32)(_stack_high);
164#endif
165
166    _the_context->wim = 0x01;
167
168    sparc_get_psr( tmp_psr );
169    tmp_psr &= ~SPARC_PIL_MASK;
170    tmp_psr |= (((_new_level) << 8) & SPARC_PIL_MASK);
171    tmp_psr  = (tmp_psr & ~0x07) | 0x07;  /* XXX should use num windows */
172    _the_context->psr = tmp_psr;
173}
174
175/*PAGE
176 *
177 *  _CPU_Internal_threads_Idle_thread_body
178 *
179 *  NOTES:
180 *
181 *  1. This is the same as the regular CPU independent algorithm.
182 *
183 *  2. If you implement this using a "halt", "idle", or "shutdown"
184 *     instruction, then don't forget to put it in an infinite loop.
185 *
186 *  3. Be warned. Some processors with onboard DMA have been known
187 *     to stop the DMA if the CPU were put in IDLE mode.  This might
188 *     also be a problem with other on-chip peripherals.  So use this
189 *     hook with caution.
190 */
191
192void _CPU_Internal_threads_Idle_thread_body( void )
193{
194
195  for( ; ; )
196    /* insert your "halt" instruction here */ ;
197}
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