source: rtems/cpukit/score/cpu/sparc/cpu.c @ a32835a3

4.104.114.84.9
Last change on this file since a32835a3 was a32835a3, checked in by Joel Sherrill <joel.sherrill@…>, on May 10, 2007 at 6:40:49 PM

2007-05-10 Joel Sherrill <joel.sherrill@…>

PR 1237/rtems

  • cpu.c, cpu_asm.S, rtems/score/cpu.h: Add logic to prevent stack creep when interrupts occur at a sufficient rate that the interrupted thread never gets to clean its stack. This patch ensures that an interrupted thread will not nest ISR dispatches on its stack.
  • Property mode set to 100644
File size: 9.4 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/rtems/cache.h>
17
18/*
19 *  This initializes the set of opcodes placed in each trap
20 *  table entry.  The routine which installs a handler is responsible
21 *  for filling in the fields for the _handler address and the _vector
22 *  trap type.
23 *
24 *  The constants following this structure are masks for the fields which
25 *  must be filled in when the handler is installed.
26 */
27
28const CPU_Trap_table_entry _CPU_Trap_slot_template = {
29  0xa1480000,      /* mov   %psr, %l0           */
30  0x29000000,      /* sethi %hi(_handler), %l4  */
31  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
32  0xa6102000       /* mov   _vector, %l3        */
33};
34
35/*PAGE
36 *
37 *  _CPU_Initialize
38 *
39 *  This routine performs processor dependent initialization.
40 *
41 *  Input Parameters:
42 *    cpu_table       - CPU table to initialize
43 *    thread_dispatch - address of disptaching routine
44 *
45 *  Output Parameters: NONE
46 *
47 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
48 *        The SPARC's assembly code can reference it directly with no problems.
49 */
50
51void _CPU_Initialize(
52  rtems_cpu_table  *cpu_table,
53  void            (*thread_dispatch)      /* ignored on this CPU */
54)
55{
56#if (SPARC_HAS_FPU == 1)
57  Context_Control_fp *pointer;
58
59  /*
60   *  This seems to be the most appropriate way to obtain an initial
61   *  FP context on the SPARC.  The NULL fp context is copied it to
62   *  the task's FP context during Context_Initialize.
63   */
64
65  pointer = &_CPU_Null_fp_context;
66  _CPU_Context_save_fp( &pointer );
67#endif
68
69  /*
70   *  Grab our own copy of the user's CPU table.
71   */
72
73  _CPU_Table = *cpu_table;
74
75  /*
76   *  Since no tasks have been created yet and no interrupts have occurred,
77   *  there is no way that the currently executing thread can have an
78   *  _ISR_Dispatch stack frame on its stack.
79   */
80  _CPU_ISR_Dispatch_disable = 0;
81}
82
83/*PAGE
84 *
85 *  _CPU_ISR_Get_level
86 *
87 *  Input Parameters: NONE
88 *
89 *  Output Parameters:
90 *    returns the current interrupt level (PIL field of the PSR)
91 */
92 
93uint32_t   _CPU_ISR_Get_level( void )
94{
95  uint32_t   level;
96 
97  sparc_get_interrupt_level( level );
98 
99  return level;
100}
101
102/*PAGE
103 *
104 *  _CPU_ISR_install_raw_handler
105 *
106 *  This routine installs the specified handler as a "raw" non-executive
107 *  supported trap handler (a.k.a. interrupt service routine).
108 *
109 *  Input Parameters:
110 *    vector      - trap table entry number plus synchronous
111 *                    vs. asynchronous information
112 *    new_handler - address of the handler to be installed
113 *    old_handler - pointer to an address of the handler previously installed
114 *
115 *  Output Parameters: NONE
116 *    *new_handler - address of the handler previously installed
117 *
118 *  NOTE:
119 *
120 *  On the SPARC, there are really only 256 vectors.  However, the executive
121 *  has no easy, fast, reliable way to determine which traps are synchronous
122 *  and which are asynchronous.  By default, synchronous traps return to the
123 *  instruction which caused the interrupt.  So if you install a software
124 *  trap handler as an executive interrupt handler (which is desirable since
125 *  RTEMS takes care of window and register issues), then the executive needs
126 *  to know that the return address is to the trap rather than the instruction
127 *  following the trap.
128 *
129 *  So vectors 0 through 255 are treated as regular asynchronous traps which
130 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
131 *  by the executive to be synchronous and to require that the return address
132 *  be fudged.
133 *
134 *  If you use this mechanism to install a trap handler which must reexecute
135 *  the instruction which caused the trap, then it should be installed as
136 *  an asynchronous trap.  This will avoid the executive changing the return
137 *  address.
138 */
139 
140void _CPU_ISR_install_raw_handler(
141  uint32_t    vector,
142  proc_ptr    new_handler,
143  proc_ptr   *old_handler
144)
145{
146  uint32_t               real_vector;
147  CPU_Trap_table_entry  *tbr;
148  CPU_Trap_table_entry  *slot;
149  uint32_t               u32_tbr;
150  uint32_t               u32_handler;
151
152  /*
153   *  Get the "real" trap number for this vector ignoring the synchronous
154   *  versus asynchronous indicator included with our vector numbers.
155   */
156
157  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
158
159  /*
160   *  Get the current base address of the trap table and calculate a pointer
161   *  to the slot we are interested in.
162   */
163
164  sparc_get_tbr( u32_tbr );
165
166  u32_tbr &= 0xfffff000;
167
168  tbr = (CPU_Trap_table_entry *) u32_tbr;
169
170  slot = &tbr[ real_vector ];
171
172  /*
173   *  Get the address of the old_handler from the trap table.
174   *
175   *  NOTE: The old_handler returned will be bogus if it does not follow
176   *        the RTEMS model.
177   */
178
179#define HIGH_BITS_MASK   0xFFFFFC00
180#define HIGH_BITS_SHIFT  10
181#define LOW_BITS_MASK    0x000003FF
182
183  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
184    u32_handler = 
185      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
186      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
187    *old_handler = (proc_ptr) u32_handler;
188  } else
189    *old_handler = 0;
190
191  /*
192   *  Copy the template to the slot and then fix it.
193   */
194
195  *slot = _CPU_Trap_slot_template;
196
197  u32_handler = (uint32_t  ) new_handler;
198
199  slot->mov_vector_l3 |= vector;
200  slot->sethi_of_handler_to_l4 |= 
201    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
202  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
203
204  /* need to flush icache after this !!! */
205
206  rtems_cache_invalidate_entire_instruction();
207
208}
209
210/*PAGE
211 *
212 *  _CPU_ISR_install_vector
213 *
214 *  This kernel routine installs the RTEMS handler for the
215 *  specified vector.
216 *
217 *  Input parameters:
218 *    vector       - interrupt vector number
219 *    new_handler  - replacement ISR for this vector number
220 *    old_handler  - pointer to former ISR for this vector number
221 *
222 *  Output parameters:
223 *    *old_handler - former ISR for this vector number
224 *
225 */
226
227void _CPU_ISR_install_vector(
228  uint32_t    vector,
229  proc_ptr    new_handler,
230  proc_ptr   *old_handler
231)
232{
233   uint32_t   real_vector;
234   proc_ptr   ignored;
235
236  /*
237   *  Get the "real" trap number for this vector ignoring the synchronous
238   *  versus asynchronous indicator included with our vector numbers.
239   */
240
241   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
242
243   /*
244    *  Return the previous ISR handler.
245    */
246
247   *old_handler = _ISR_Vector_table[ real_vector ];
248
249   /*
250    *  Install the wrapper so this ISR can be invoked properly.
251    */
252
253   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
254
255   /*
256    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
257    *  be used by the _ISR_Handler so the user gets control.
258    */
259
260    _ISR_Vector_table[ real_vector ] = new_handler;
261}
262
263/*PAGE
264 *
265 *  _CPU_Context_Initialize
266 *
267 *  This kernel routine initializes the basic non-FP context area associated
268 *  with each thread.
269 *
270 *  Input parameters:
271 *    the_context  - pointer to the context area
272 *    stack_base   - address of memory for the SPARC
273 *    size         - size in bytes of the stack area
274 *    new_level    - interrupt level for this context area
275 *    entry_point  - the starting execution point for this this context
276 *    is_fp        - TRUE if this context is associated with an FP thread
277 *
278 *  Output parameters: NONE
279 */
280
281void _CPU_Context_Initialize(
282  Context_Control  *the_context,
283  uint32_t         *stack_base,
284  uint32_t          size,
285  uint32_t          new_level,
286  void             *entry_point,
287  boolean           is_fp
288)
289{
290    uint32_t     stack_high;  /* highest "stack aligned" address */
291    uint32_t     the_size;
292    uint32_t     tmp_psr;
293 
294    /*
295     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
296     *  based on the stack_high address. 
297     */
298 
299    stack_high = ((uint32_t  )(stack_base) + size);
300    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
301 
302    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
303 
304    /*
305     *  See the README in this directory for a diagram of the stack.
306     */
307 
308    the_context->o7    = ((uint32_t  ) entry_point) - 8;
309    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
310    the_context->i6_fp = stack_high;
311
312    /*
313     *  Build the PSR for the task.  Most everything can be 0 and the
314     *  CWP is corrected during the context switch.
315     *
316     *  The EF bit determines if the floating point unit is available.
317     *  The FPU is ONLY enabled if the context is associated with an FP task
318     *  and this SPARC model has an FPU.
319     */
320
321    sparc_get_psr( tmp_psr );
322    tmp_psr &= ~SPARC_PSR_PIL_MASK;
323    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
324    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
325   
326#if (SPARC_HAS_FPU == 1)
327    /*
328     *  If this bit is not set, then a task gets a fault when it accesses
329     *  a floating point register.  This is a nice way to detect floating
330     *  point tasks which are not currently declared as such.
331     */
332
333    if ( is_fp )
334      tmp_psr |= SPARC_PSR_EF_MASK;
335#endif
336    the_context->psr = tmp_psr;
337
338  /*
339   *  Since THIS thread is being created, there is no way that THIS
340   *  thread can have an _ISR_Dispatch stack frame on its stack.
341   */
342    the_context->isr_dispatch_disable = 0;
343}
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