source: rtems/cpukit/score/cpu/sparc/cpu.c @ 8e87c6e9

4.104.114.84.9
Last change on this file since 8e87c6e9 was 8e87c6e9, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 3, 2002 at 2:16:32 PM

2002-04-01 Ralf Corsepius <corsepiu@…>

  • cpu.c: Remove call to sparc_init_tbr/NO_TABLE_MOVE.
  • rtems/score/cpu.h: Remove NO_TABLE_MOVE conditional code.
  • Property mode set to 100644
File size: 9.0 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/rtems/cache.h>
17
18/*
19 *  This initializes the set of opcodes placed in each trap
20 *  table entry.  The routine which installs a handler is responsible
21 *  for filling in the fields for the _handler address and the _vector
22 *  trap type.
23 *
24 *  The constants following this structure are masks for the fields which
25 *  must be filled in when the handler is installed.
26 */
27
28const CPU_Trap_table_entry _CPU_Trap_slot_template = {
29  0xa1480000,      /* mov   %psr, %l0           */
30  0x29000000,      /* sethi %hi(_handler), %l4  */
31  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
32  0xa6102000       /* mov   _vector, %l3        */
33};
34
35/*PAGE
36 *
37 *  _CPU_Initialize
38 *
39 *  This routine performs processor dependent initialization.
40 *
41 *  Input Parameters:
42 *    cpu_table       - CPU table to initialize
43 *    thread_dispatch - address of disptaching routine
44 *
45 *  Output Parameters: NONE
46 *
47 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
48 *        The SPARC's assembly code can reference it directly with no problems.
49 */
50
51void _CPU_Initialize(
52  rtems_cpu_table  *cpu_table,
53  void            (*thread_dispatch)      /* ignored on this CPU */
54)
55{
56  void                  *pointer;
57
58#if (SPARC_HAS_FPU == 1)
59
60  /*
61   *  This seems to be the most appropriate way to obtain an initial
62   *  FP context on the SPARC.  The NULL fp context is copied it to
63   *  the task's FP context during Context_Initialize.
64   */
65
66  pointer = &_CPU_Null_fp_context;
67  _CPU_Context_save_fp( &pointer );
68#endif
69
70  /*
71   *  Grab our own copy of the user's CPU table.
72   */
73
74  _CPU_Table = *cpu_table;
75}
76
77/*PAGE
78 *
79 *  _CPU_ISR_Get_level
80 *
81 *  Input Parameters: NONE
82 *
83 *  Output Parameters:
84 *    returns the current interrupt level (PIL field of the PSR)
85 */
86 
87unsigned32 _CPU_ISR_Get_level( void )
88{
89  unsigned32 level;
90 
91  sparc_get_interrupt_level( level );
92 
93  return level;
94}
95
96/*PAGE
97 *
98 *  _CPU_ISR_install_raw_handler
99 *
100 *  This routine installs the specified handler as a "raw" non-executive
101 *  supported trap handler (a.k.a. interrupt service routine).
102 *
103 *  Input Parameters:
104 *    vector      - trap table entry number plus synchronous
105 *                    vs. asynchronous information
106 *    new_handler - address of the handler to be installed
107 *    old_handler - pointer to an address of the handler previously installed
108 *
109 *  Output Parameters: NONE
110 *    *new_handler - address of the handler previously installed
111 *
112 *  NOTE:
113 *
114 *  On the SPARC, there are really only 256 vectors.  However, the executive
115 *  has no easy, fast, reliable way to determine which traps are synchronous
116 *  and which are asynchronous.  By default, synchronous traps return to the
117 *  instruction which caused the interrupt.  So if you install a software
118 *  trap handler as an executive interrupt handler (which is desirable since
119 *  RTEMS takes care of window and register issues), then the executive needs
120 *  to know that the return address is to the trap rather than the instruction
121 *  following the trap.
122 *
123 *  So vectors 0 through 255 are treated as regular asynchronous traps which
124 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
125 *  by the executive to be synchronous and to require that the return address
126 *  be fudged.
127 *
128 *  If you use this mechanism to install a trap handler which must reexecute
129 *  the instruction which caused the trap, then it should be installed as
130 *  an asynchronous trap.  This will avoid the executive changing the return
131 *  address.
132 */
133 
134void _CPU_ISR_install_raw_handler(
135  unsigned32  vector,
136  proc_ptr    new_handler,
137  proc_ptr   *old_handler
138)
139{
140  unsigned32             real_vector;
141  CPU_Trap_table_entry  *tbr;
142  CPU_Trap_table_entry  *slot;
143  unsigned32             u32_tbr;
144  unsigned32             u32_handler;
145
146  /*
147   *  Get the "real" trap number for this vector ignoring the synchronous
148   *  versus asynchronous indicator included with our vector numbers.
149   */
150
151  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
152
153  /*
154   *  Get the current base address of the trap table and calculate a pointer
155   *  to the slot we are interested in.
156   */
157
158  sparc_get_tbr( u32_tbr );
159
160  u32_tbr &= 0xfffff000;
161
162  tbr = (CPU_Trap_table_entry *) u32_tbr;
163
164  slot = &tbr[ real_vector ];
165
166  /*
167   *  Get the address of the old_handler from the trap table.
168   *
169   *  NOTE: The old_handler returned will be bogus if it does not follow
170   *        the RTEMS model.
171   */
172
173#define HIGH_BITS_MASK   0xFFFFFC00
174#define HIGH_BITS_SHIFT  10
175#define LOW_BITS_MASK    0x000003FF
176
177  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
178    u32_handler = 
179      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
180      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
181    *old_handler = (proc_ptr) u32_handler;
182  } else
183    *old_handler = 0;
184
185  /*
186   *  Copy the template to the slot and then fix it.
187   */
188
189  *slot = _CPU_Trap_slot_template;
190
191  u32_handler = (unsigned32) new_handler;
192
193  slot->mov_vector_l3 |= vector;
194  slot->sethi_of_handler_to_l4 |= 
195    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
196  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
197
198  /* need to flush icache after this !!! */
199
200  rtems_cache_invalidate_entire_instruction();
201
202}
203
204/*PAGE
205 *
206 *  _CPU_ISR_install_vector
207 *
208 *  This kernel routine installs the RTEMS handler for the
209 *  specified vector.
210 *
211 *  Input parameters:
212 *    vector       - interrupt vector number
213 *    new_handler  - replacement ISR for this vector number
214 *    old_handler  - pointer to former ISR for this vector number
215 *
216 *  Output parameters:
217 *    *old_handler - former ISR for this vector number
218 *
219 */
220
221void _CPU_ISR_install_vector(
222  unsigned32  vector,
223  proc_ptr    new_handler,
224  proc_ptr   *old_handler
225)
226{
227   unsigned32 real_vector;
228   proc_ptr   ignored;
229
230  /*
231   *  Get the "real" trap number for this vector ignoring the synchronous
232   *  versus asynchronous indicator included with our vector numbers.
233   */
234
235   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
236
237   /*
238    *  Return the previous ISR handler.
239    */
240
241   *old_handler = _ISR_Vector_table[ real_vector ];
242
243   /*
244    *  Install the wrapper so this ISR can be invoked properly.
245    */
246
247   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
248
249   /*
250    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
251    *  be used by the _ISR_Handler so the user gets control.
252    */
253
254    _ISR_Vector_table[ real_vector ] = new_handler;
255}
256
257/*PAGE
258 *
259 *  _CPU_Context_Initialize
260 *
261 *  This kernel routine initializes the basic non-FP context area associated
262 *  with each thread.
263 *
264 *  Input parameters:
265 *    the_context  - pointer to the context area
266 *    stack_base   - address of memory for the SPARC
267 *    size         - size in bytes of the stack area
268 *    new_level    - interrupt level for this context area
269 *    entry_point  - the starting execution point for this this context
270 *    is_fp        - TRUE if this context is associated with an FP thread
271 *
272 *  Output parameters: NONE
273 */
274
275void _CPU_Context_Initialize(
276  Context_Control  *the_context,
277  unsigned32       *stack_base,
278  unsigned32        size,
279  unsigned32        new_level,
280  void             *entry_point,
281  boolean           is_fp
282)
283{
284    unsigned32   stack_high;  /* highest "stack aligned" address */
285    unsigned32   the_size;
286    unsigned32   tmp_psr;
287 
288    /*
289     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
290     *  based on the stack_high address. 
291     */
292 
293    stack_high = ((unsigned32)(stack_base) + size);
294    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
295 
296    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
297 
298    /*
299     *  See the README in this directory for a diagram of the stack.
300     */
301 
302    the_context->o7    = ((unsigned32) entry_point) - 8;
303    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
304    the_context->i6_fp = stack_high;
305
306    /*
307     *  Build the PSR for the task.  Most everything can be 0 and the
308     *  CWP is corrected during the context switch.
309     *
310     *  The EF bit determines if the floating point unit is available.
311     *  The FPU is ONLY enabled if the context is associated with an FP task
312     *  and this SPARC model has an FPU.
313     */
314
315    sparc_get_psr( tmp_psr );
316    tmp_psr &= ~SPARC_PSR_PIL_MASK;
317    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
318    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
319   
320#if (SPARC_HAS_FPU == 1)
321    /*
322     *  If this bit is not set, then a task gets a fault when it accesses
323     *  a floating point register.  This is a nice way to detect floating
324     *  point tasks which are not currently declared as such.
325     */
326
327    if ( is_fp )
328      tmp_psr |= SPARC_PSR_EF_MASK;
329#endif
330    the_context->psr = tmp_psr;
331}
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