source: rtems/cpukit/score/cpu/sparc/cpu.c @ 75f09e5

4.104.114.84.95
Last change on this file since 75f09e5 was 75f09e5, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 21, 1996 at 2:43:34 PM

Dispersal of internal thread handler resulted in IDLE thread becoming
part of the Thread Handler. This required the name of the optional
CPU dependent IDLE thread implementation to change.

  • Property mode set to 100644
File size: 11.0 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
5 *  On-Line Applications Research Corporation (OAR).
6 *  All rights assigned to U.S. Government, 1994.
7 *
8 *  This material may be reproduced by or for the U.S. Government pursuant
9 *  to the copyright license under the clause at DFARS 252.227-7013.  This
10 *  notice must appear in all copies of this file and its derivatives.
11 *
12 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
13 *  Research Corporation (OAR) under contract to the European Space
14 *  Agency (ESA).
15 *
16 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
17 *  European Space Agency.
18 *
19 *  $Id$
20 */
21
22#include <rtems/system.h>
23#include <rtems/score/isr.h>
24
25#if defined(erc32)
26#include <erc32.h>
27#endif
28
29/*
30 *  This initializes the set of opcodes placed in each trap
31 *  table entry.  The routine which installs a handler is responsible
32 *  for filling in the fields for the _handler address and the _vector
33 *  trap type.
34 *
35 *  The constants following this structure are masks for the fields which
36 *  must be filled in when the handler is installed.
37 */
38
39const CPU_Trap_table_entry _CPU_Trap_slot_template = {
40  0xa1480000,      /* mov   %psr, %l0           */
41  0x29000000,      /* sethi %hi(_handler), %l4  */
42  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
43  0xa6102000       /* mov   _vector, %l3        */
44};
45
46/*PAGE
47 *
48 *  _CPU_Initialize
49 *
50 *  This routine performs processor dependent initialization.
51 *
52 *  Input Parameters:
53 *    cpu_table       - CPU table to initialize
54 *    thread_dispatch - address of disptaching routine
55 *
56 *  Output Parameters: NONE
57 *
58 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
59 *        The SPARC's assembly code can reference it directly with no problems.
60 */
61
62void _CPU_Initialize(
63  rtems_cpu_table  *cpu_table,
64  void            (*thread_dispatch)      /* ignored on this CPU */
65)
66{
67  void                  *pointer;
68  unsigned32             trap_table_start;
69  unsigned32             tbr_value;
70  CPU_Trap_table_entry  *old_tbr;
71  CPU_Trap_table_entry  *trap_table;
72
73  /*
74   *  Install the executive's trap table.  All entries from the original
75   *  trap table are copied into the executive's trap table.  This is essential
76   *  since this preserves critical trap handlers such as the window underflow
77   *  and overflow handlers.  It is the responsibility of the BSP to provide
78   *  install these in the initial trap table.
79   */
80 
81  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
82  if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
83    trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & 
84                       ~(SPARC_TRAP_TABLE_ALIGNMENT-1);
85
86  trap_table = (CPU_Trap_table_entry *) trap_table_start;
87
88  sparc_get_tbr( tbr_value );
89
90  old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
91
92  memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
93
94  sparc_set_tbr( trap_table_start );
95
96  /*
97   *  This seems to be the most appropriate way to obtain an initial
98   *  FP context on the SPARC.  The NULL fp context is copied it to
99   *  the task's FP context during Context_Initialize.
100   */
101
102  pointer = &_CPU_Null_fp_context;
103  _CPU_Context_save_fp( &pointer );
104
105  /*
106   *  Grab our own copy of the user's CPU table.
107   */
108
109  _CPU_Table = *cpu_table;
110
111#if defined(erc32)
112
113  /*
114   *  ERC32 specific initialization
115   */
116
117  _ERC32_MEC_Timer_Control_Mirror = 0;
118  ERC32_MEC.Timer_Control = 0;
119
120  ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
121
122#endif
123
124}
125
126/*PAGE
127 *
128 *  _CPU_ISR_Get_level
129 *
130 *  Input Parameters: NONE
131 *
132 *  Output Parameters:
133 *    returns the current interrupt level (PIL field of the PSR)
134 */
135 
136unsigned32 _CPU_ISR_Get_level( void )
137{
138  unsigned32 level;
139 
140  sparc_get_interrupt_level( level );
141 
142  return level;
143}
144
145/*PAGE
146 *
147 *  _CPU_ISR_install_raw_handler
148 *
149 *  This routine installs the specified handler as a "raw" non-executive
150 *  supported trap handler (a.k.a. interrupt service routine).
151 *
152 *  Input Parameters:
153 *    vector      - trap table entry number plus synchronous
154 *                    vs. asynchronous information
155 *    new_handler - address of the handler to be installed
156 *    old_handler - pointer to an address of the handler previously installed
157 *
158 *  Output Parameters: NONE
159 *    *new_handler - address of the handler previously installed
160 *
161 *  NOTE:
162 *
163 *  On the SPARC, there are really only 256 vectors.  However, the executive
164 *  has no easy, fast, reliable way to determine which traps are synchronous
165 *  and which are asynchronous.  By default, synchronous traps return to the
166 *  instruction which caused the interrupt.  So if you install a software
167 *  trap handler as an executive interrupt handler (which is desirable since
168 *  RTEMS takes care of window and register issues), then the executive needs
169 *  to know that the return address is to the trap rather than the instruction
170 *  following the trap.
171 *
172 *  So vectors 0 through 255 are treated as regular asynchronous traps which
173 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
174 *  by the executive to be synchronous and to require that the return address
175 *  be fudged.
176 *
177 *  If you use this mechanism to install a trap handler which must reexecute
178 *  the instruction which caused the trap, then it should be installed as
179 *  an asynchronous trap.  This will avoid the executive changing the return
180 *  address.
181 */
182 
183void _CPU_ISR_install_raw_handler(
184  unsigned32  vector,
185  proc_ptr    new_handler,
186  proc_ptr   *old_handler
187)
188{
189  unsigned32             real_vector;
190  CPU_Trap_table_entry  *tbr;
191  CPU_Trap_table_entry  *slot;
192  unsigned32             u32_tbr;
193  unsigned32             u32_handler;
194
195  /*
196   *  Get the "real" trap number for this vector ignoring the synchronous
197   *  versus asynchronous indicator included with our vector numbers.
198   */
199
200  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
201
202  /*
203   *  Get the current base address of the trap table and calculate a pointer
204   *  to the slot we are interested in.
205   */
206
207  sparc_get_tbr( u32_tbr );
208
209  u32_tbr &= 0xfffff000;
210
211  tbr = (CPU_Trap_table_entry *) u32_tbr;
212
213  slot = &tbr[ real_vector ];
214
215  /*
216   *  Get the address of the old_handler from the trap table.
217   *
218   *  NOTE: The old_handler returned will be bogus if it does not follow
219   *        the RTEMS model.
220   */
221
222#define HIGH_BITS_MASK   0xFFFFFC00
223#define HIGH_BITS_SHIFT  10
224#define LOW_BITS_MASK    0x000003FF
225
226  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
227    u32_handler = 
228      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
229      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
230    *old_handler = (proc_ptr) u32_handler;
231  } else
232    *old_handler = 0;
233
234  /*
235   *  Copy the template to the slot and then fix it.
236   */
237
238  *slot = _CPU_Trap_slot_template;
239
240  u32_handler = (unsigned32) new_handler;
241
242  slot->mov_vector_l3 |= vector;
243  slot->sethi_of_handler_to_l4 |= 
244    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
245  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
246}
247
248/*PAGE
249 *
250 *  _CPU_ISR_install_vector
251 *
252 *  This kernel routine installs the RTEMS handler for the
253 *  specified vector.
254 *
255 *  Input parameters:
256 *    vector       - interrupt vector number
257 *    new_handler  - replacement ISR for this vector number
258 *    old_handler  - pointer to former ISR for this vector number
259 *
260 *  Output parameters:
261 *    *old_handler - former ISR for this vector number
262 *
263 */
264
265void _CPU_ISR_install_vector(
266  unsigned32  vector,
267  proc_ptr    new_handler,
268  proc_ptr   *old_handler
269)
270{
271   unsigned32 real_vector;
272   proc_ptr   ignored;
273
274  /*
275   *  Get the "real" trap number for this vector ignoring the synchronous
276   *  versus asynchronous indicator included with our vector numbers.
277   */
278
279   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
280
281   /*
282    *  Return the previous ISR handler.
283    */
284
285   *old_handler = _ISR_Vector_table[ real_vector ];
286
287   /*
288    *  Install the wrapper so this ISR can be invoked properly.
289    */
290
291   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
292
293   /*
294    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
295    *  be used by the _ISR_Handler so the user gets control.
296    */
297
298    _ISR_Vector_table[ real_vector ] = new_handler;
299}
300
301/*PAGE
302 *
303 *  _CPU_Context_Initialize
304 *
305 *  This kernel routine initializes the basic non-FP context area associated
306 *  with each thread.
307 *
308 *  Input parameters:
309 *    the_context  - pointer to the context area
310 *    stack_base   - address of memory for the SPARC
311 *    size         - size in bytes of the stack area
312 *    new_level    - interrupt level for this context area
313 *    entry_point  - the starting execution point for this this context
314 *    is_fp        - TRUE if this context is associated with an FP thread
315 *
316 *  Output parameters: NONE
317 */
318
319void _CPU_Context_Initialize(
320  Context_Control  *the_context,
321  unsigned32       *stack_base,
322  unsigned32        size,
323  unsigned32        new_level,
324  void             *entry_point,
325  boolean           is_fp
326)
327{
328    unsigned32   stack_high;  /* highest "stack aligned" address */
329    unsigned32   the_size;
330    unsigned32   tmp_psr;
331 
332    /*
333     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
334     *  based on the stack_high address. 
335     */
336 
337    stack_high = ((unsigned32)(stack_base) + size);
338    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
339 
340    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
341 
342    /*
343     *  See the README in this directory for a diagram of the stack.
344     */
345 
346    the_context->o7    = ((unsigned32) entry_point) - 8;
347    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
348    the_context->i6_fp = stack_high;
349
350    /*
351     *  Build the PSR for the task.  Most everything can be 0 and the
352     *  CWP is corrected during the context switch.
353     *
354     *  The EF bit determines if the floating point unit is available.
355     *  The FPU is ONLY enabled if the context is associated with an FP task
356     *  and this SPARC model has an FPU.
357     */
358
359    sparc_get_psr( tmp_psr );
360    tmp_psr &= ~SPARC_PSR_PIL_MASK;
361    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
362    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
363   
364#if (SPARC_HAS_FPU == 1)
365    /*
366     *  If this bit is not set, then a task gets a fault when it accesses
367     *  a floating point register.  This is a nice way to detect floating
368     *  point tasks which are not currently declared as such.
369     */
370
371    if ( is_fp )
372      tmp_psr |= SPARC_PSR_EF_MASK;
373#endif
374    the_context->psr = tmp_psr;
375}
376
377/*PAGE
378 *
379 *  _CPU_Thread_Idle_body
380 *
381 *  Some SPARC implementations have low power, sleep, or idle modes.  This
382 *  tries to take advantage of those models. 
383 */
384 
385#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
386
387/*
388 *  This is the implementation for the erc32.
389 *
390 *  NOTE: Low power mode was enabled at initialization time.
391 */
392
393#if defined(erc32)
394
395void _CPU_Thread_Idle_body( void )
396{
397  while (1) {
398    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
399  }
400}
401
402#endif
403
404#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
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