source: rtems/cpukit/score/cpu/sparc/cpu.c @ 60b791ad

4.104.114.84.95
Last change on this file since 60b791ad was 60b791ad, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 17, 1998 at 11:46:28 PM

updated copyright to 1998

  • Property mode set to 100644
File size: 10.9 KB
Line 
1/*
2 *  SPARC Dependent Source
3 *
4 *  COPYRIGHT (c) 1989-1998.
5 *  On-Line Applications Research Corporation (OAR).
6 *  Copyright assigned to U.S. Government, 1994.
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
13 *  Research Corporation (OAR) under contract to the European Space
14 *  Agency (ESA).
15 *
16 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
17 *  European Space Agency.
18 *
19 *  $Id$
20 */
21
22#include <rtems/system.h>
23#include <rtems/score/isr.h>
24
25#if defined(erc32)
26#include <erc32.h>
27#endif
28
29/*
30 *  This initializes the set of opcodes placed in each trap
31 *  table entry.  The routine which installs a handler is responsible
32 *  for filling in the fields for the _handler address and the _vector
33 *  trap type.
34 *
35 *  The constants following this structure are masks for the fields which
36 *  must be filled in when the handler is installed.
37 */
38
39const CPU_Trap_table_entry _CPU_Trap_slot_template = {
40  0xa1480000,      /* mov   %psr, %l0           */
41  0x29000000,      /* sethi %hi(_handler), %l4  */
42  0x81c52000,      /* jmp   %l4 + %lo(_handler) */
43  0xa6102000       /* mov   _vector, %l3        */
44};
45
46/*PAGE
47 *
48 *  _CPU_Initialize
49 *
50 *  This routine performs processor dependent initialization.
51 *
52 *  Input Parameters:
53 *    cpu_table       - CPU table to initialize
54 *    thread_dispatch - address of disptaching routine
55 *
56 *  Output Parameters: NONE
57 *
58 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
59 *        The SPARC's assembly code can reference it directly with no problems.
60 */
61
62void _CPU_Initialize(
63  rtems_cpu_table  *cpu_table,
64  void            (*thread_dispatch)      /* ignored on this CPU */
65)
66{
67  void                  *pointer;
68
69#ifndef NO_TABLE_MOVE
70  unsigned32             trap_table_start;
71  unsigned32             tbr_value;
72  CPU_Trap_table_entry  *old_tbr;
73  CPU_Trap_table_entry  *trap_table;
74
75  /*
76   *  Install the executive's trap table.  All entries from the original
77   *  trap table are copied into the executive's trap table.  This is essential
78   *  since this preserves critical trap handlers such as the window underflow
79   *  and overflow handlers.  It is the responsibility of the BSP to provide
80   *  install these in the initial trap table.
81   */
82
83 
84  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
85  if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
86    trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) & 
87                       ~(SPARC_TRAP_TABLE_ALIGNMENT-1);
88
89  trap_table = (CPU_Trap_table_entry *) trap_table_start;
90
91  sparc_get_tbr( tbr_value );
92
93  old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
94
95  memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
96
97  sparc_set_tbr( trap_table_start );
98
99#endif
100
101  /*
102   *  This seems to be the most appropriate way to obtain an initial
103   *  FP context on the SPARC.  The NULL fp context is copied it to
104   *  the task's FP context during Context_Initialize.
105   */
106
107  pointer = &_CPU_Null_fp_context;
108  _CPU_Context_save_fp( &pointer );
109
110  /*
111   *  Grab our own copy of the user's CPU table.
112   */
113
114  _CPU_Table = *cpu_table;
115
116#if defined(erc32)
117
118  /*
119   *  ERC32 specific initialization
120   */
121
122  _ERC32_MEC_Timer_Control_Mirror = 0;
123  ERC32_MEC.Timer_Control = 0;
124
125  ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
126
127#endif
128
129}
130
131/*PAGE
132 *
133 *  _CPU_ISR_Get_level
134 *
135 *  Input Parameters: NONE
136 *
137 *  Output Parameters:
138 *    returns the current interrupt level (PIL field of the PSR)
139 */
140 
141unsigned32 _CPU_ISR_Get_level( void )
142{
143  unsigned32 level;
144 
145  sparc_get_interrupt_level( level );
146 
147  return level;
148}
149
150/*PAGE
151 *
152 *  _CPU_ISR_install_raw_handler
153 *
154 *  This routine installs the specified handler as a "raw" non-executive
155 *  supported trap handler (a.k.a. interrupt service routine).
156 *
157 *  Input Parameters:
158 *    vector      - trap table entry number plus synchronous
159 *                    vs. asynchronous information
160 *    new_handler - address of the handler to be installed
161 *    old_handler - pointer to an address of the handler previously installed
162 *
163 *  Output Parameters: NONE
164 *    *new_handler - address of the handler previously installed
165 *
166 *  NOTE:
167 *
168 *  On the SPARC, there are really only 256 vectors.  However, the executive
169 *  has no easy, fast, reliable way to determine which traps are synchronous
170 *  and which are asynchronous.  By default, synchronous traps return to the
171 *  instruction which caused the interrupt.  So if you install a software
172 *  trap handler as an executive interrupt handler (which is desirable since
173 *  RTEMS takes care of window and register issues), then the executive needs
174 *  to know that the return address is to the trap rather than the instruction
175 *  following the trap.
176 *
177 *  So vectors 0 through 255 are treated as regular asynchronous traps which
178 *  provide the "correct" return address.  Vectors 256 through 512 are assumed
179 *  by the executive to be synchronous and to require that the return address
180 *  be fudged.
181 *
182 *  If you use this mechanism to install a trap handler which must reexecute
183 *  the instruction which caused the trap, then it should be installed as
184 *  an asynchronous trap.  This will avoid the executive changing the return
185 *  address.
186 */
187 
188void _CPU_ISR_install_raw_handler(
189  unsigned32  vector,
190  proc_ptr    new_handler,
191  proc_ptr   *old_handler
192)
193{
194  unsigned32             real_vector;
195  CPU_Trap_table_entry  *tbr;
196  CPU_Trap_table_entry  *slot;
197  unsigned32             u32_tbr;
198  unsigned32             u32_handler;
199
200  /*
201   *  Get the "real" trap number for this vector ignoring the synchronous
202   *  versus asynchronous indicator included with our vector numbers.
203   */
204
205  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
206
207  /*
208   *  Get the current base address of the trap table and calculate a pointer
209   *  to the slot we are interested in.
210   */
211
212  sparc_get_tbr( u32_tbr );
213
214  u32_tbr &= 0xfffff000;
215
216  tbr = (CPU_Trap_table_entry *) u32_tbr;
217
218  slot = &tbr[ real_vector ];
219
220  /*
221   *  Get the address of the old_handler from the trap table.
222   *
223   *  NOTE: The old_handler returned will be bogus if it does not follow
224   *        the RTEMS model.
225   */
226
227#define HIGH_BITS_MASK   0xFFFFFC00
228#define HIGH_BITS_SHIFT  10
229#define LOW_BITS_MASK    0x000003FF
230
231  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
232    u32_handler = 
233      ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
234      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
235    *old_handler = (proc_ptr) u32_handler;
236  } else
237    *old_handler = 0;
238
239  /*
240   *  Copy the template to the slot and then fix it.
241   */
242
243  *slot = _CPU_Trap_slot_template;
244
245  u32_handler = (unsigned32) new_handler;
246
247  slot->mov_vector_l3 |= vector;
248  slot->sethi_of_handler_to_l4 |= 
249    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
250  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
251}
252
253/*PAGE
254 *
255 *  _CPU_ISR_install_vector
256 *
257 *  This kernel routine installs the RTEMS handler for the
258 *  specified vector.
259 *
260 *  Input parameters:
261 *    vector       - interrupt vector number
262 *    new_handler  - replacement ISR for this vector number
263 *    old_handler  - pointer to former ISR for this vector number
264 *
265 *  Output parameters:
266 *    *old_handler - former ISR for this vector number
267 *
268 */
269
270void _CPU_ISR_install_vector(
271  unsigned32  vector,
272  proc_ptr    new_handler,
273  proc_ptr   *old_handler
274)
275{
276   unsigned32 real_vector;
277   proc_ptr   ignored;
278
279  /*
280   *  Get the "real" trap number for this vector ignoring the synchronous
281   *  versus asynchronous indicator included with our vector numbers.
282   */
283
284   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
285
286   /*
287    *  Return the previous ISR handler.
288    */
289
290   *old_handler = _ISR_Vector_table[ real_vector ];
291
292   /*
293    *  Install the wrapper so this ISR can be invoked properly.
294    */
295
296   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
297
298   /*
299    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
300    *  be used by the _ISR_Handler so the user gets control.
301    */
302
303    _ISR_Vector_table[ real_vector ] = new_handler;
304}
305
306/*PAGE
307 *
308 *  _CPU_Context_Initialize
309 *
310 *  This kernel routine initializes the basic non-FP context area associated
311 *  with each thread.
312 *
313 *  Input parameters:
314 *    the_context  - pointer to the context area
315 *    stack_base   - address of memory for the SPARC
316 *    size         - size in bytes of the stack area
317 *    new_level    - interrupt level for this context area
318 *    entry_point  - the starting execution point for this this context
319 *    is_fp        - TRUE if this context is associated with an FP thread
320 *
321 *  Output parameters: NONE
322 */
323
324void _CPU_Context_Initialize(
325  Context_Control  *the_context,
326  unsigned32       *stack_base,
327  unsigned32        size,
328  unsigned32        new_level,
329  void             *entry_point,
330  boolean           is_fp
331)
332{
333    unsigned32   stack_high;  /* highest "stack aligned" address */
334    unsigned32   the_size;
335    unsigned32   tmp_psr;
336 
337    /*
338     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
339     *  based on the stack_high address. 
340     */
341 
342    stack_high = ((unsigned32)(stack_base) + size);
343    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
344 
345    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
346 
347    /*
348     *  See the README in this directory for a diagram of the stack.
349     */
350 
351    the_context->o7    = ((unsigned32) entry_point) - 8;
352    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
353    the_context->i6_fp = stack_high;
354
355    /*
356     *  Build the PSR for the task.  Most everything can be 0 and the
357     *  CWP is corrected during the context switch.
358     *
359     *  The EF bit determines if the floating point unit is available.
360     *  The FPU is ONLY enabled if the context is associated with an FP task
361     *  and this SPARC model has an FPU.
362     */
363
364    sparc_get_psr( tmp_psr );
365    tmp_psr &= ~SPARC_PSR_PIL_MASK;
366    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
367    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
368   
369#if (SPARC_HAS_FPU == 1)
370    /*
371     *  If this bit is not set, then a task gets a fault when it accesses
372     *  a floating point register.  This is a nice way to detect floating
373     *  point tasks which are not currently declared as such.
374     */
375
376    if ( is_fp )
377      tmp_psr |= SPARC_PSR_EF_MASK;
378#endif
379    the_context->psr = tmp_psr;
380}
381
382/*PAGE
383 *
384 *  _CPU_Thread_Idle_body
385 *
386 *  Some SPARC implementations have low power, sleep, or idle modes.  This
387 *  tries to take advantage of those models. 
388 */
389 
390#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
391
392/*
393 *  This is the implementation for the erc32.
394 *
395 *  NOTE: Low power mode was enabled at initialization time.
396 */
397
398#if defined(erc32)
399
400void _CPU_Thread_Idle_body( void )
401{
402  while (1) {
403    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
404  }
405}
406
407#endif
408
409#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
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